1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2020 Marvell International Ltd. 4 * 5 * Configuration and status register (CSR) type definitions for 6 * Octeon agl. 7 * 8 */ 9 10 #ifndef __CVMX_AGL_DEFS_H__ 11 #define __CVMX_AGL_DEFS_H__ 12 13 #define CVMX_AGL_GMX_BAD_REG (0x00011800E0000518ull) 14 #define CVMX_AGL_GMX_BIST (0x00011800E0000400ull) 15 #define CVMX_AGL_GMX_DRV_CTL (0x00011800E00007F0ull) 16 #define CVMX_AGL_GMX_INF_MODE (0x00011800E00007F8ull) 17 #define CVMX_AGL_GMX_PRTX_CFG(offset) (0x00011800E0000010ull + ((offset) & 1) * 2048) 18 #define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) (0x00011800E0000180ull + ((offset) & 1) * 2048) 19 #define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) (0x00011800E0000188ull + ((offset) & 1) * 2048) 20 #define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) (0x00011800E0000190ull + ((offset) & 1) * 2048) 21 #define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) (0x00011800E0000198ull + ((offset) & 1) * 2048) 22 #define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) (0x00011800E00001A0ull + ((offset) & 1) * 2048) 23 #define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) (0x00011800E00001A8ull + ((offset) & 1) * 2048) 24 #define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) (0x00011800E0000108ull + ((offset) & 1) * 2048) 25 #define CVMX_AGL_GMX_RXX_ADR_CTL(offset) (0x00011800E0000100ull + ((offset) & 1) * 2048) 26 #define CVMX_AGL_GMX_RXX_DECISION(offset) (0x00011800E0000040ull + ((offset) & 1) * 2048) 27 #define CVMX_AGL_GMX_RXX_FRM_CHK(offset) (0x00011800E0000020ull + ((offset) & 1) * 2048) 28 #define CVMX_AGL_GMX_RXX_FRM_CTL(offset) (0x00011800E0000018ull + ((offset) & 1) * 2048) 29 #define CVMX_AGL_GMX_RXX_FRM_MAX(offset) (0x00011800E0000030ull + ((offset) & 1) * 2048) 30 #define CVMX_AGL_GMX_RXX_FRM_MIN(offset) (0x00011800E0000028ull + ((offset) & 1) * 2048) 31 #define CVMX_AGL_GMX_RXX_IFG(offset) (0x00011800E0000058ull + ((offset) & 1) * 2048) 32 #define CVMX_AGL_GMX_RXX_INT_EN(offset) (0x00011800E0000008ull + ((offset) & 1) * 2048) 33 #define CVMX_AGL_GMX_RXX_INT_REG(offset) (0x00011800E0000000ull + ((offset) & 1) * 2048) 34 #define CVMX_AGL_GMX_RXX_JABBER(offset) (0x00011800E0000038ull + ((offset) & 1) * 2048) 35 #define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) (0x00011800E0000068ull + ((offset) & 1) * 2048) 36 #define CVMX_AGL_GMX_RXX_RX_INBND(offset) (0x00011800E0000060ull + ((offset) & 1) * 2048) 37 #define CVMX_AGL_GMX_RXX_STATS_CTL(offset) (0x00011800E0000050ull + ((offset) & 1) * 2048) 38 #define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) (0x00011800E0000088ull + ((offset) & 1) * 2048) 39 #define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) (0x00011800E0000098ull + ((offset) & 1) * 2048) 40 #define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) (0x00011800E00000A8ull + ((offset) & 1) * 2048) 41 #define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) (0x00011800E00000B8ull + ((offset) & 1) * 2048) 42 #define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) (0x00011800E0000080ull + ((offset) & 1) * 2048) 43 #define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) (0x00011800E00000C0ull + ((offset) & 1) * 2048) 44 #define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) (0x00011800E0000090ull + ((offset) & 1) * 2048) 45 #define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) (0x00011800E00000A0ull + ((offset) & 1) * 2048) 46 #define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) (0x00011800E00000B0ull + ((offset) & 1) * 2048) 47 #define CVMX_AGL_GMX_RXX_UDD_SKP(offset) (0x00011800E0000048ull + ((offset) & 1) * 2048) 48 #define CVMX_AGL_GMX_RX_BP_DROPX(offset) (0x00011800E0000420ull + ((offset) & 1) * 8) 49 #define CVMX_AGL_GMX_RX_BP_OFFX(offset) (0x00011800E0000460ull + ((offset) & 1) * 8) 50 #define CVMX_AGL_GMX_RX_BP_ONX(offset) (0x00011800E0000440ull + ((offset) & 1) * 8) 51 #define CVMX_AGL_GMX_RX_PRT_INFO (0x00011800E00004E8ull) 52 #define CVMX_AGL_GMX_RX_TX_STATUS (0x00011800E00007E8ull) 53 #define CVMX_AGL_GMX_SMACX(offset) (0x00011800E0000230ull + ((offset) & 1) * 2048) 54 #define CVMX_AGL_GMX_STAT_BP (0x00011800E0000520ull) 55 #define CVMX_AGL_GMX_TXX_APPEND(offset) (0x00011800E0000218ull + ((offset) & 1) * 2048) 56 #define CVMX_AGL_GMX_TXX_CLK(offset) (0x00011800E0000208ull + ((offset) & 1) * 2048) 57 #define CVMX_AGL_GMX_TXX_CTL(offset) (0x00011800E0000270ull + ((offset) & 1) * 2048) 58 #define CVMX_AGL_GMX_TXX_MIN_PKT(offset) (0x00011800E0000240ull + ((offset) & 1) * 2048) 59 #define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) (0x00011800E0000248ull + ((offset) & 1) * 2048) 60 #define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) (0x00011800E0000238ull + ((offset) & 1) * 2048) 61 #define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) (0x00011800E0000258ull + ((offset) & 1) * 2048) 62 #define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) (0x00011800E0000260ull + ((offset) & 1) * 2048) 63 #define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) (0x00011800E0000250ull + ((offset) & 1) * 2048) 64 #define CVMX_AGL_GMX_TXX_STAT0(offset) (0x00011800E0000280ull + ((offset) & 1) * 2048) 65 #define CVMX_AGL_GMX_TXX_STAT1(offset) (0x00011800E0000288ull + ((offset) & 1) * 2048) 66 #define CVMX_AGL_GMX_TXX_STAT2(offset) (0x00011800E0000290ull + ((offset) & 1) * 2048) 67 #define CVMX_AGL_GMX_TXX_STAT3(offset) (0x00011800E0000298ull + ((offset) & 1) * 2048) 68 #define CVMX_AGL_GMX_TXX_STAT4(offset) (0x00011800E00002A0ull + ((offset) & 1) * 2048) 69 #define CVMX_AGL_GMX_TXX_STAT5(offset) (0x00011800E00002A8ull + ((offset) & 1) * 2048) 70 #define CVMX_AGL_GMX_TXX_STAT6(offset) (0x00011800E00002B0ull + ((offset) & 1) * 2048) 71 #define CVMX_AGL_GMX_TXX_STAT7(offset) (0x00011800E00002B8ull + ((offset) & 1) * 2048) 72 #define CVMX_AGL_GMX_TXX_STAT8(offset) (0x00011800E00002C0ull + ((offset) & 1) * 2048) 73 #define CVMX_AGL_GMX_TXX_STAT9(offset) (0x00011800E00002C8ull + ((offset) & 1) * 2048) 74 #define CVMX_AGL_GMX_TXX_STATS_CTL(offset) (0x00011800E0000268ull + ((offset) & 1) * 2048) 75 #define CVMX_AGL_GMX_TXX_THRESH(offset) (0x00011800E0000210ull + ((offset) & 1) * 2048) 76 #define CVMX_AGL_GMX_TX_BP (0x00011800E00004D0ull) 77 #define CVMX_AGL_GMX_TX_COL_ATTEMPT (0x00011800E0000498ull) 78 #define CVMX_AGL_GMX_TX_IFG (0x00011800E0000488ull) 79 #define CVMX_AGL_GMX_TX_INT_EN (0x00011800E0000508ull) 80 #define CVMX_AGL_GMX_TX_INT_REG (0x00011800E0000500ull) 81 #define CVMX_AGL_GMX_TX_JAM (0x00011800E0000490ull) 82 #define CVMX_AGL_GMX_TX_LFSR (0x00011800E00004F8ull) 83 #define CVMX_AGL_GMX_TX_OVR_BP (0x00011800E00004C8ull) 84 #define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC (0x00011800E00004A0ull) 85 #define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE (0x00011800E00004A8ull) 86 #define CVMX_AGL_GMX_WOL_CTL (0x00011800E0000780ull) 87 #define CVMX_AGL_PRTX_CTL(offset) (0x00011800E0002000ull + ((offset) & 1) * 8) 88 89 /** 90 * cvmx_agl_gmx_bad_reg 91 * 92 * AGL_GMX_BAD_REG = A collection of things that have gone very, very wrong 93 * 94 * 95 * Notes: 96 * OUT_OVR[0], LOSTSTAT[0], OVRFLW, TXPOP, TXPSH will be reset when MIX0_CTL[RESET] is set to 1. 97 * OUT_OVR[1], LOSTSTAT[1], OVRFLW1, TXPOP1, TXPSH1 will be reset when MIX1_CTL[RESET] is set to 1. 98 * STATOVR will be reset when both MIX0/1_CTL[RESET] are set to 1. 99 */ 100 union cvmx_agl_gmx_bad_reg { 101 u64 u64; 102 struct cvmx_agl_gmx_bad_reg_s { 103 u64 reserved_38_63 : 26; 104 u64 txpsh1 : 1; 105 u64 txpop1 : 1; 106 u64 ovrflw1 : 1; 107 u64 txpsh : 1; 108 u64 txpop : 1; 109 u64 ovrflw : 1; 110 u64 reserved_27_31 : 5; 111 u64 statovr : 1; 112 u64 reserved_24_25 : 2; 113 u64 loststat : 2; 114 u64 reserved_4_21 : 18; 115 u64 out_ovr : 2; 116 u64 reserved_0_1 : 2; 117 } s; 118 struct cvmx_agl_gmx_bad_reg_cn52xx { 119 u64 reserved_38_63 : 26; 120 u64 txpsh1 : 1; 121 u64 txpop1 : 1; 122 u64 ovrflw1 : 1; 123 u64 txpsh : 1; 124 u64 txpop : 1; 125 u64 ovrflw : 1; 126 u64 reserved_27_31 : 5; 127 u64 statovr : 1; 128 u64 reserved_23_25 : 3; 129 u64 loststat : 1; 130 u64 reserved_4_21 : 18; 131 u64 out_ovr : 2; 132 u64 reserved_0_1 : 2; 133 } cn52xx; 134 struct cvmx_agl_gmx_bad_reg_cn52xx cn52xxp1; 135 struct cvmx_agl_gmx_bad_reg_cn56xx { 136 u64 reserved_35_63 : 29; 137 u64 txpsh : 1; 138 u64 txpop : 1; 139 u64 ovrflw : 1; 140 u64 reserved_27_31 : 5; 141 u64 statovr : 1; 142 u64 reserved_23_25 : 3; 143 u64 loststat : 1; 144 u64 reserved_3_21 : 19; 145 u64 out_ovr : 1; 146 u64 reserved_0_1 : 2; 147 } cn56xx; 148 struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1; 149 struct cvmx_agl_gmx_bad_reg_s cn61xx; 150 struct cvmx_agl_gmx_bad_reg_s cn63xx; 151 struct cvmx_agl_gmx_bad_reg_s cn63xxp1; 152 struct cvmx_agl_gmx_bad_reg_s cn66xx; 153 struct cvmx_agl_gmx_bad_reg_s cn68xx; 154 struct cvmx_agl_gmx_bad_reg_s cn68xxp1; 155 struct cvmx_agl_gmx_bad_reg_cn56xx cn70xx; 156 struct cvmx_agl_gmx_bad_reg_cn56xx cn70xxp1; 157 }; 158 159 typedef union cvmx_agl_gmx_bad_reg cvmx_agl_gmx_bad_reg_t; 160 161 /** 162 * cvmx_agl_gmx_bist 163 * 164 * AGL_GMX_BIST = GMX BIST Results 165 * 166 * 167 * Notes: 168 * Not reset when MIX*_CTL[RESET] is set to 1. 169 * 170 */ 171 union cvmx_agl_gmx_bist { 172 u64 u64; 173 struct cvmx_agl_gmx_bist_s { 174 u64 reserved_25_63 : 39; 175 u64 status : 25; 176 } s; 177 struct cvmx_agl_gmx_bist_cn52xx { 178 u64 reserved_10_63 : 54; 179 u64 status : 10; 180 } cn52xx; 181 struct cvmx_agl_gmx_bist_cn52xx cn52xxp1; 182 struct cvmx_agl_gmx_bist_cn52xx cn56xx; 183 struct cvmx_agl_gmx_bist_cn52xx cn56xxp1; 184 struct cvmx_agl_gmx_bist_s cn61xx; 185 struct cvmx_agl_gmx_bist_s cn63xx; 186 struct cvmx_agl_gmx_bist_s cn63xxp1; 187 struct cvmx_agl_gmx_bist_s cn66xx; 188 struct cvmx_agl_gmx_bist_s cn68xx; 189 struct cvmx_agl_gmx_bist_s cn68xxp1; 190 struct cvmx_agl_gmx_bist_s cn70xx; 191 struct cvmx_agl_gmx_bist_s cn70xxp1; 192 }; 193 194 typedef union cvmx_agl_gmx_bist cvmx_agl_gmx_bist_t; 195 196 /** 197 * cvmx_agl_gmx_drv_ctl 198 * 199 * AGL_GMX_DRV_CTL = GMX Drive Control 200 * 201 * 202 * Notes: 203 * NCTL, PCTL, BYP_EN will be reset when MIX0_CTL[RESET] is set to 1. 204 * NCTL1, PCTL1, BYP_EN1 will be reset when MIX1_CTL[RESET] is set to 1. 205 */ 206 union cvmx_agl_gmx_drv_ctl { 207 u64 u64; 208 struct cvmx_agl_gmx_drv_ctl_s { 209 u64 reserved_49_63 : 15; 210 u64 byp_en1 : 1; 211 u64 reserved_45_47 : 3; 212 u64 pctl1 : 5; 213 u64 reserved_37_39 : 3; 214 u64 nctl1 : 5; 215 u64 reserved_17_31 : 15; 216 u64 byp_en : 1; 217 u64 reserved_13_15 : 3; 218 u64 pctl : 5; 219 u64 reserved_5_7 : 3; 220 u64 nctl : 5; 221 } s; 222 struct cvmx_agl_gmx_drv_ctl_s cn52xx; 223 struct cvmx_agl_gmx_drv_ctl_s cn52xxp1; 224 struct cvmx_agl_gmx_drv_ctl_cn56xx { 225 u64 reserved_17_63 : 47; 226 u64 byp_en : 1; 227 u64 reserved_13_15 : 3; 228 u64 pctl : 5; 229 u64 reserved_5_7 : 3; 230 u64 nctl : 5; 231 } cn56xx; 232 struct cvmx_agl_gmx_drv_ctl_cn56xx cn56xxp1; 233 }; 234 235 typedef union cvmx_agl_gmx_drv_ctl cvmx_agl_gmx_drv_ctl_t; 236 237 /** 238 * cvmx_agl_gmx_inf_mode 239 * 240 * AGL_GMX_INF_MODE = Interface Mode 241 * 242 * 243 * Notes: 244 * Not reset when MIX*_CTL[RESET] is set to 1. 245 * 246 */ 247 union cvmx_agl_gmx_inf_mode { 248 u64 u64; 249 struct cvmx_agl_gmx_inf_mode_s { 250 u64 reserved_2_63 : 62; 251 u64 en : 1; 252 u64 reserved_0_0 : 1; 253 } s; 254 struct cvmx_agl_gmx_inf_mode_s cn52xx; 255 struct cvmx_agl_gmx_inf_mode_s cn52xxp1; 256 struct cvmx_agl_gmx_inf_mode_s cn56xx; 257 struct cvmx_agl_gmx_inf_mode_s cn56xxp1; 258 }; 259 260 typedef union cvmx_agl_gmx_inf_mode cvmx_agl_gmx_inf_mode_t; 261 262 /** 263 * cvmx_agl_gmx_prt#_cfg 264 * 265 * AGL_GMX_PRT_CFG = Port description 266 * 267 * 268 * Notes: 269 * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 270 * 271 */ 272 union cvmx_agl_gmx_prtx_cfg { 273 u64 u64; 274 struct cvmx_agl_gmx_prtx_cfg_s { 275 u64 reserved_14_63 : 50; 276 u64 tx_idle : 1; 277 u64 rx_idle : 1; 278 u64 reserved_9_11 : 3; 279 u64 speed_msb : 1; 280 u64 reserved_7_7 : 1; 281 u64 burst : 1; 282 u64 tx_en : 1; 283 u64 rx_en : 1; 284 u64 slottime : 1; 285 u64 duplex : 1; 286 u64 speed : 1; 287 u64 en : 1; 288 } s; 289 struct cvmx_agl_gmx_prtx_cfg_cn52xx { 290 u64 reserved_6_63 : 58; 291 u64 tx_en : 1; 292 u64 rx_en : 1; 293 u64 slottime : 1; 294 u64 duplex : 1; 295 u64 speed : 1; 296 u64 en : 1; 297 } cn52xx; 298 struct cvmx_agl_gmx_prtx_cfg_cn52xx cn52xxp1; 299 struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xx; 300 struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xxp1; 301 struct cvmx_agl_gmx_prtx_cfg_s cn61xx; 302 struct cvmx_agl_gmx_prtx_cfg_s cn63xx; 303 struct cvmx_agl_gmx_prtx_cfg_s cn63xxp1; 304 struct cvmx_agl_gmx_prtx_cfg_s cn66xx; 305 struct cvmx_agl_gmx_prtx_cfg_s cn68xx; 306 struct cvmx_agl_gmx_prtx_cfg_s cn68xxp1; 307 struct cvmx_agl_gmx_prtx_cfg_s cn70xx; 308 struct cvmx_agl_gmx_prtx_cfg_s cn70xxp1; 309 }; 310 311 typedef union cvmx_agl_gmx_prtx_cfg cvmx_agl_gmx_prtx_cfg_t; 312 313 /** 314 * cvmx_agl_gmx_rx#_adr_cam0 315 * 316 * AGL_GMX_RX_ADR_CAM = Address Filtering Control 317 * 318 */ 319 union cvmx_agl_gmx_rxx_adr_cam0 { 320 u64 u64; 321 struct cvmx_agl_gmx_rxx_adr_cam0_s { 322 u64 adr : 64; 323 } s; 324 struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xx; 325 struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1; 326 struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx; 327 struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1; 328 struct cvmx_agl_gmx_rxx_adr_cam0_s cn61xx; 329 struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xx; 330 struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xxp1; 331 struct cvmx_agl_gmx_rxx_adr_cam0_s cn66xx; 332 struct cvmx_agl_gmx_rxx_adr_cam0_s cn68xx; 333 struct cvmx_agl_gmx_rxx_adr_cam0_s cn68xxp1; 334 struct cvmx_agl_gmx_rxx_adr_cam0_s cn70xx; 335 struct cvmx_agl_gmx_rxx_adr_cam0_s cn70xxp1; 336 }; 337 338 typedef union cvmx_agl_gmx_rxx_adr_cam0 cvmx_agl_gmx_rxx_adr_cam0_t; 339 340 /** 341 * cvmx_agl_gmx_rx#_adr_cam1 342 * 343 * AGL_GMX_RX_ADR_CAM = Address Filtering Control 344 * 345 */ 346 union cvmx_agl_gmx_rxx_adr_cam1 { 347 u64 u64; 348 struct cvmx_agl_gmx_rxx_adr_cam1_s { 349 u64 adr : 64; 350 } s; 351 struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xx; 352 struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1; 353 struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx; 354 struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1; 355 struct cvmx_agl_gmx_rxx_adr_cam1_s cn61xx; 356 struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xx; 357 struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xxp1; 358 struct cvmx_agl_gmx_rxx_adr_cam1_s cn66xx; 359 struct cvmx_agl_gmx_rxx_adr_cam1_s cn68xx; 360 struct cvmx_agl_gmx_rxx_adr_cam1_s cn68xxp1; 361 struct cvmx_agl_gmx_rxx_adr_cam1_s cn70xx; 362 struct cvmx_agl_gmx_rxx_adr_cam1_s cn70xxp1; 363 }; 364 365 typedef union cvmx_agl_gmx_rxx_adr_cam1 cvmx_agl_gmx_rxx_adr_cam1_t; 366 367 /** 368 * cvmx_agl_gmx_rx#_adr_cam2 369 * 370 * AGL_GMX_RX_ADR_CAM = Address Filtering Control 371 * 372 */ 373 union cvmx_agl_gmx_rxx_adr_cam2 { 374 u64 u64; 375 struct cvmx_agl_gmx_rxx_adr_cam2_s { 376 u64 adr : 64; 377 } s; 378 struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xx; 379 struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1; 380 struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx; 381 struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1; 382 struct cvmx_agl_gmx_rxx_adr_cam2_s cn61xx; 383 struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xx; 384 struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xxp1; 385 struct cvmx_agl_gmx_rxx_adr_cam2_s cn66xx; 386 struct cvmx_agl_gmx_rxx_adr_cam2_s cn68xx; 387 struct cvmx_agl_gmx_rxx_adr_cam2_s cn68xxp1; 388 struct cvmx_agl_gmx_rxx_adr_cam2_s cn70xx; 389 struct cvmx_agl_gmx_rxx_adr_cam2_s cn70xxp1; 390 }; 391 392 typedef union cvmx_agl_gmx_rxx_adr_cam2 cvmx_agl_gmx_rxx_adr_cam2_t; 393 394 /** 395 * cvmx_agl_gmx_rx#_adr_cam3 396 * 397 * AGL_GMX_RX_ADR_CAM = Address Filtering Control 398 * 399 */ 400 union cvmx_agl_gmx_rxx_adr_cam3 { 401 u64 u64; 402 struct cvmx_agl_gmx_rxx_adr_cam3_s { 403 u64 adr : 64; 404 } s; 405 struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xx; 406 struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1; 407 struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx; 408 struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1; 409 struct cvmx_agl_gmx_rxx_adr_cam3_s cn61xx; 410 struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xx; 411 struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xxp1; 412 struct cvmx_agl_gmx_rxx_adr_cam3_s cn66xx; 413 struct cvmx_agl_gmx_rxx_adr_cam3_s cn68xx; 414 struct cvmx_agl_gmx_rxx_adr_cam3_s cn68xxp1; 415 struct cvmx_agl_gmx_rxx_adr_cam3_s cn70xx; 416 struct cvmx_agl_gmx_rxx_adr_cam3_s cn70xxp1; 417 }; 418 419 typedef union cvmx_agl_gmx_rxx_adr_cam3 cvmx_agl_gmx_rxx_adr_cam3_t; 420 421 /** 422 * cvmx_agl_gmx_rx#_adr_cam4 423 * 424 * AGL_GMX_RX_ADR_CAM = Address Filtering Control 425 * 426 */ 427 union cvmx_agl_gmx_rxx_adr_cam4 { 428 u64 u64; 429 struct cvmx_agl_gmx_rxx_adr_cam4_s { 430 u64 adr : 64; 431 } s; 432 struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xx; 433 struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1; 434 struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx; 435 struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1; 436 struct cvmx_agl_gmx_rxx_adr_cam4_s cn61xx; 437 struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xx; 438 struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xxp1; 439 struct cvmx_agl_gmx_rxx_adr_cam4_s cn66xx; 440 struct cvmx_agl_gmx_rxx_adr_cam4_s cn68xx; 441 struct cvmx_agl_gmx_rxx_adr_cam4_s cn68xxp1; 442 struct cvmx_agl_gmx_rxx_adr_cam4_s cn70xx; 443 struct cvmx_agl_gmx_rxx_adr_cam4_s cn70xxp1; 444 }; 445 446 typedef union cvmx_agl_gmx_rxx_adr_cam4 cvmx_agl_gmx_rxx_adr_cam4_t; 447 448 /** 449 * cvmx_agl_gmx_rx#_adr_cam5 450 * 451 * AGL_GMX_RX_ADR_CAM = Address Filtering Control 452 * 453 */ 454 union cvmx_agl_gmx_rxx_adr_cam5 { 455 u64 u64; 456 struct cvmx_agl_gmx_rxx_adr_cam5_s { 457 u64 adr : 64; 458 } s; 459 struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xx; 460 struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1; 461 struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx; 462 struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1; 463 struct cvmx_agl_gmx_rxx_adr_cam5_s cn61xx; 464 struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xx; 465 struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xxp1; 466 struct cvmx_agl_gmx_rxx_adr_cam5_s cn66xx; 467 struct cvmx_agl_gmx_rxx_adr_cam5_s cn68xx; 468 struct cvmx_agl_gmx_rxx_adr_cam5_s cn68xxp1; 469 struct cvmx_agl_gmx_rxx_adr_cam5_s cn70xx; 470 struct cvmx_agl_gmx_rxx_adr_cam5_s cn70xxp1; 471 }; 472 473 typedef union cvmx_agl_gmx_rxx_adr_cam5 cvmx_agl_gmx_rxx_adr_cam5_t; 474 475 /** 476 * cvmx_agl_gmx_rx#_adr_cam_en 477 * 478 * AGL_GMX_RX_ADR_CAM_EN = Address Filtering Control Enable 479 * 480 * 481 * Notes: 482 * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 483 * 484 */ 485 union cvmx_agl_gmx_rxx_adr_cam_en { 486 u64 u64; 487 struct cvmx_agl_gmx_rxx_adr_cam_en_s { 488 u64 reserved_8_63 : 56; 489 u64 en : 8; 490 } s; 491 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xx; 492 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1; 493 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx; 494 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1; 495 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn61xx; 496 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xx; 497 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xxp1; 498 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn66xx; 499 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn68xx; 500 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn68xxp1; 501 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn70xx; 502 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn70xxp1; 503 }; 504 505 typedef union cvmx_agl_gmx_rxx_adr_cam_en cvmx_agl_gmx_rxx_adr_cam_en_t; 506 507 /** 508 * cvmx_agl_gmx_rx#_adr_ctl 509 * 510 * AGL_GMX_RX_ADR_CTL = Address Filtering Control 511 * 512 * 513 * Notes: 514 * * ALGORITHM 515 * Here is some pseudo code that represents the address filter behavior. 516 * 517 * @verbatim 518 * bool dmac_addr_filter(uint8 prt, uint48 dmac) [ 519 * ASSERT(prt >= 0 && prt <= 3); 520 * if (is_bcst(dmac)) // broadcast accept 521 * return (AGL_GMX_RX[prt]_ADR_CTL[BCST] ? ACCEPT : REJECT); 522 * if (is_mcst(dmac) & AGL_GMX_RX[prt]_ADR_CTL[MCST] == 1) // multicast reject 523 * return REJECT; 524 * if (is_mcst(dmac) & AGL_GMX_RX[prt]_ADR_CTL[MCST] == 2) // multicast accept 525 * return ACCEPT; 526 * 527 * cam_hit = 0; 528 * 529 * for (i=0; i<8; i++) [ 530 * if (AGL_GMX_RX[prt]_ADR_CAM_EN[EN<i>] == 0) 531 * continue; 532 * uint48 unswizzled_mac_adr = 0x0; 533 * for (j=5; j>=0; j--) [ 534 * unswizzled_mac_adr = (unswizzled_mac_adr << 8) | AGL_GMX_RX[prt]_ADR_CAM[j][ADR<i*8+7:i*8>]; 535 * ] 536 * if (unswizzled_mac_adr == dmac) [ 537 * cam_hit = 1; 538 * break; 539 * ] 540 * ] 541 * 542 * if (cam_hit) 543 * return (AGL_GMX_RX[prt]_ADR_CTL[CAM_MODE] ? ACCEPT : REJECT); 544 * else 545 * return (AGL_GMX_RX[prt]_ADR_CTL[CAM_MODE] ? REJECT : ACCEPT); 546 * ] 547 * @endverbatim 548 * 549 * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 550 */ 551 union cvmx_agl_gmx_rxx_adr_ctl { 552 u64 u64; 553 struct cvmx_agl_gmx_rxx_adr_ctl_s { 554 u64 reserved_4_63 : 60; 555 u64 cam_mode : 1; 556 u64 mcst : 2; 557 u64 bcst : 1; 558 } s; 559 struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xx; 560 struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1; 561 struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx; 562 struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1; 563 struct cvmx_agl_gmx_rxx_adr_ctl_s cn61xx; 564 struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xx; 565 struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xxp1; 566 struct cvmx_agl_gmx_rxx_adr_ctl_s cn66xx; 567 struct cvmx_agl_gmx_rxx_adr_ctl_s cn68xx; 568 struct cvmx_agl_gmx_rxx_adr_ctl_s cn68xxp1; 569 struct cvmx_agl_gmx_rxx_adr_ctl_s cn70xx; 570 struct cvmx_agl_gmx_rxx_adr_ctl_s cn70xxp1; 571 }; 572 573 typedef union cvmx_agl_gmx_rxx_adr_ctl cvmx_agl_gmx_rxx_adr_ctl_t; 574 575 /** 576 * cvmx_agl_gmx_rx#_decision 577 * 578 * AGL_GMX_RX_DECISION = The byte count to decide when to accept or filter a packet 579 * 580 * 581 * Notes: 582 * As each byte in a packet is received by GMX, the L2 byte count is compared 583 * against the AGL_GMX_RX_DECISION[CNT]. The L2 byte count is the number of bytes 584 * from the beginning of the L2 header (DMAC). In normal operation, the L2 585 * header begins after the PREAMBLE+SFD (AGL_GMX_RX_FRM_CTL[PRE_CHK]=1) and any 586 * optional UDD skip data (AGL_GMX_RX_UDD_SKP[LEN]). 587 * 588 * When AGL_GMX_RX_FRM_CTL[PRE_CHK] is clear, PREAMBLE+SFD are prepended to the 589 * packet and would require UDD skip length to account for them. 590 * 591 * L2 Size 592 * Port Mode <=AGL_GMX_RX_DECISION bytes (default=24) >AGL_GMX_RX_DECISION bytes (default=24) 593 * 594 * MII/Full Duplex accept packet apply filters 595 * no filtering is applied accept packet based on DMAC and PAUSE packet filters 596 * 597 * MII/Half Duplex drop packet apply filters 598 * packet is unconditionally dropped accept packet based on DMAC 599 * 600 * where l2_size = MAX(0, total_packet_size - AGL_GMX_RX_UDD_SKP[LEN] - ((AGL_GMX_RX_FRM_CTL[PRE_CHK]==1)*8) 601 * 602 * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 603 */ 604 union cvmx_agl_gmx_rxx_decision { 605 u64 u64; 606 struct cvmx_agl_gmx_rxx_decision_s { 607 u64 reserved_5_63 : 59; 608 u64 cnt : 5; 609 } s; 610 struct cvmx_agl_gmx_rxx_decision_s cn52xx; 611 struct cvmx_agl_gmx_rxx_decision_s cn52xxp1; 612 struct cvmx_agl_gmx_rxx_decision_s cn56xx; 613 struct cvmx_agl_gmx_rxx_decision_s cn56xxp1; 614 struct cvmx_agl_gmx_rxx_decision_s cn61xx; 615 struct cvmx_agl_gmx_rxx_decision_s cn63xx; 616 struct cvmx_agl_gmx_rxx_decision_s cn63xxp1; 617 struct cvmx_agl_gmx_rxx_decision_s cn66xx; 618 struct cvmx_agl_gmx_rxx_decision_s cn68xx; 619 struct cvmx_agl_gmx_rxx_decision_s cn68xxp1; 620 struct cvmx_agl_gmx_rxx_decision_s cn70xx; 621 struct cvmx_agl_gmx_rxx_decision_s cn70xxp1; 622 }; 623 624 typedef union cvmx_agl_gmx_rxx_decision cvmx_agl_gmx_rxx_decision_t; 625 626 /** 627 * cvmx_agl_gmx_rx#_frm_chk 628 * 629 * AGL_GMX_RX_FRM_CHK = Which frame errors will set the ERR bit of the frame 630 * 631 * 632 * Notes: 633 * If AGL_GMX_RX_UDD_SKP[LEN] != 0, then LENERR will be forced to zero in HW. 634 * 635 * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 636 */ 637 union cvmx_agl_gmx_rxx_frm_chk { 638 u64 u64; 639 struct cvmx_agl_gmx_rxx_frm_chk_s { 640 u64 reserved_10_63 : 54; 641 u64 niberr : 1; 642 u64 skperr : 1; 643 u64 rcverr : 1; 644 u64 lenerr : 1; 645 u64 alnerr : 1; 646 u64 fcserr : 1; 647 u64 jabber : 1; 648 u64 maxerr : 1; 649 u64 carext : 1; 650 u64 minerr : 1; 651 } s; 652 struct cvmx_agl_gmx_rxx_frm_chk_cn52xx { 653 u64 reserved_9_63 : 55; 654 u64 skperr : 1; 655 u64 rcverr : 1; 656 u64 lenerr : 1; 657 u64 alnerr : 1; 658 u64 fcserr : 1; 659 u64 jabber : 1; 660 u64 maxerr : 1; 661 u64 reserved_1_1 : 1; 662 u64 minerr : 1; 663 } cn52xx; 664 struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn52xxp1; 665 struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xx; 666 struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xxp1; 667 struct cvmx_agl_gmx_rxx_frm_chk_s cn61xx; 668 struct cvmx_agl_gmx_rxx_frm_chk_s cn63xx; 669 struct cvmx_agl_gmx_rxx_frm_chk_s cn63xxp1; 670 struct cvmx_agl_gmx_rxx_frm_chk_s cn66xx; 671 struct cvmx_agl_gmx_rxx_frm_chk_s cn68xx; 672 struct cvmx_agl_gmx_rxx_frm_chk_s cn68xxp1; 673 struct cvmx_agl_gmx_rxx_frm_chk_s cn70xx; 674 struct cvmx_agl_gmx_rxx_frm_chk_s cn70xxp1; 675 }; 676 677 typedef union cvmx_agl_gmx_rxx_frm_chk cvmx_agl_gmx_rxx_frm_chk_t; 678 679 /** 680 * cvmx_agl_gmx_rx#_frm_ctl 681 * 682 * AGL_GMX_RX_FRM_CTL = Frame Control 683 * 684 * 685 * Notes: 686 * * PRE_STRP 687 * When PRE_CHK is set (indicating that the PREAMBLE will be sent), PRE_STRP 688 * determines if the PREAMBLE+SFD bytes are thrown away or sent to the Octane 689 * core as part of the packet. 690 * 691 * In either mode, the PREAMBLE+SFD bytes are not counted toward the packet 692 * size when checking against the MIN and MAX bounds. Furthermore, the bytes 693 * are skipped when locating the start of the L2 header for DMAC and Control 694 * frame recognition. 695 * 696 * * CTL_BCK/CTL_DRP 697 * These bits control how the HW handles incoming PAUSE packets. Here are 698 * the most common modes of operation: 699 * CTL_BCK=1,CTL_DRP=1 - HW does it all 700 * CTL_BCK=0,CTL_DRP=0 - SW sees all pause frames 701 * CTL_BCK=0,CTL_DRP=1 - all pause frames are completely ignored 702 * 703 * These control bits should be set to CTL_BCK=0,CTL_DRP=0 in halfdup mode. 704 * Since PAUSE packets only apply to fulldup operation, any PAUSE packet 705 * would constitute an exception which should be handled by the processing 706 * cores. PAUSE packets should not be forwarded. 707 * 708 * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 709 */ 710 union cvmx_agl_gmx_rxx_frm_ctl { 711 u64 u64; 712 struct cvmx_agl_gmx_rxx_frm_ctl_s { 713 u64 reserved_13_63 : 51; 714 u64 ptp_mode : 1; 715 u64 reserved_11_11 : 1; 716 u64 null_dis : 1; 717 u64 pre_align : 1; 718 u64 pad_len : 1; 719 u64 vlan_len : 1; 720 u64 pre_free : 1; 721 u64 ctl_smac : 1; 722 u64 ctl_mcst : 1; 723 u64 ctl_bck : 1; 724 u64 ctl_drp : 1; 725 u64 pre_strp : 1; 726 u64 pre_chk : 1; 727 } s; 728 struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx { 729 u64 reserved_10_63 : 54; 730 u64 pre_align : 1; 731 u64 pad_len : 1; 732 u64 vlan_len : 1; 733 u64 pre_free : 1; 734 u64 ctl_smac : 1; 735 u64 ctl_mcst : 1; 736 u64 ctl_bck : 1; 737 u64 ctl_drp : 1; 738 u64 pre_strp : 1; 739 u64 pre_chk : 1; 740 } cn52xx; 741 struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn52xxp1; 742 struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xx; 743 struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xxp1; 744 struct cvmx_agl_gmx_rxx_frm_ctl_s cn61xx; 745 struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xx; 746 struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xxp1; 747 struct cvmx_agl_gmx_rxx_frm_ctl_s cn66xx; 748 struct cvmx_agl_gmx_rxx_frm_ctl_s cn68xx; 749 struct cvmx_agl_gmx_rxx_frm_ctl_s cn68xxp1; 750 struct cvmx_agl_gmx_rxx_frm_ctl_s cn70xx; 751 struct cvmx_agl_gmx_rxx_frm_ctl_s cn70xxp1; 752 }; 753 754 typedef union cvmx_agl_gmx_rxx_frm_ctl cvmx_agl_gmx_rxx_frm_ctl_t; 755 756 /** 757 * cvmx_agl_gmx_rx#_frm_max 758 * 759 * AGL_GMX_RX_FRM_MAX = Frame Max length 760 * 761 * 762 * Notes: 763 * When changing the LEN field, be sure that LEN does not exceed 764 * AGL_GMX_RX_JABBER[CNT]. Failure to meet this constraint will cause packets that 765 * are within the maximum length parameter to be rejected because they exceed 766 * the AGL_GMX_RX_JABBER[CNT] limit. 767 * 768 * Notes: 769 * 770 * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 771 */ 772 union cvmx_agl_gmx_rxx_frm_max { 773 u64 u64; 774 struct cvmx_agl_gmx_rxx_frm_max_s { 775 u64 reserved_16_63 : 48; 776 u64 len : 16; 777 } s; 778 struct cvmx_agl_gmx_rxx_frm_max_s cn52xx; 779 struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1; 780 struct cvmx_agl_gmx_rxx_frm_max_s cn56xx; 781 struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1; 782 struct cvmx_agl_gmx_rxx_frm_max_s cn61xx; 783 struct cvmx_agl_gmx_rxx_frm_max_s cn63xx; 784 struct cvmx_agl_gmx_rxx_frm_max_s cn63xxp1; 785 struct cvmx_agl_gmx_rxx_frm_max_s cn66xx; 786 struct cvmx_agl_gmx_rxx_frm_max_s cn68xx; 787 struct cvmx_agl_gmx_rxx_frm_max_s cn68xxp1; 788 struct cvmx_agl_gmx_rxx_frm_max_s cn70xx; 789 struct cvmx_agl_gmx_rxx_frm_max_s cn70xxp1; 790 }; 791 792 typedef union cvmx_agl_gmx_rxx_frm_max cvmx_agl_gmx_rxx_frm_max_t; 793 794 /** 795 * cvmx_agl_gmx_rx#_frm_min 796 * 797 * AGL_GMX_RX_FRM_MIN = Frame Min length 798 * 799 * 800 * Notes: 801 * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 802 * 803 */ 804 union cvmx_agl_gmx_rxx_frm_min { 805 u64 u64; 806 struct cvmx_agl_gmx_rxx_frm_min_s { 807 u64 reserved_16_63 : 48; 808 u64 len : 16; 809 } s; 810 struct cvmx_agl_gmx_rxx_frm_min_s cn52xx; 811 struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1; 812 struct cvmx_agl_gmx_rxx_frm_min_s cn56xx; 813 struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1; 814 struct cvmx_agl_gmx_rxx_frm_min_s cn61xx; 815 struct cvmx_agl_gmx_rxx_frm_min_s cn63xx; 816 struct cvmx_agl_gmx_rxx_frm_min_s cn63xxp1; 817 struct cvmx_agl_gmx_rxx_frm_min_s cn66xx; 818 struct cvmx_agl_gmx_rxx_frm_min_s cn68xx; 819 struct cvmx_agl_gmx_rxx_frm_min_s cn68xxp1; 820 struct cvmx_agl_gmx_rxx_frm_min_s cn70xx; 821 struct cvmx_agl_gmx_rxx_frm_min_s cn70xxp1; 822 }; 823 824 typedef union cvmx_agl_gmx_rxx_frm_min cvmx_agl_gmx_rxx_frm_min_t; 825 826 /** 827 * cvmx_agl_gmx_rx#_ifg 828 * 829 * AGL_GMX_RX_IFG = RX Min IFG 830 * 831 * 832 * Notes: 833 * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 834 * 835 */ 836 union cvmx_agl_gmx_rxx_ifg { 837 u64 u64; 838 struct cvmx_agl_gmx_rxx_ifg_s { 839 u64 reserved_4_63 : 60; 840 u64 ifg : 4; 841 } s; 842 struct cvmx_agl_gmx_rxx_ifg_s cn52xx; 843 struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1; 844 struct cvmx_agl_gmx_rxx_ifg_s cn56xx; 845 struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1; 846 struct cvmx_agl_gmx_rxx_ifg_s cn61xx; 847 struct cvmx_agl_gmx_rxx_ifg_s cn63xx; 848 struct cvmx_agl_gmx_rxx_ifg_s cn63xxp1; 849 struct cvmx_agl_gmx_rxx_ifg_s cn66xx; 850 struct cvmx_agl_gmx_rxx_ifg_s cn68xx; 851 struct cvmx_agl_gmx_rxx_ifg_s cn68xxp1; 852 struct cvmx_agl_gmx_rxx_ifg_s cn70xx; 853 struct cvmx_agl_gmx_rxx_ifg_s cn70xxp1; 854 }; 855 856 typedef union cvmx_agl_gmx_rxx_ifg cvmx_agl_gmx_rxx_ifg_t; 857 858 /** 859 * cvmx_agl_gmx_rx#_int_en 860 * 861 * AGL_GMX_RX_INT_EN = Interrupt Enable 862 * 863 * 864 * Notes: 865 * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 866 * 867 */ 868 union cvmx_agl_gmx_rxx_int_en { 869 u64 u64; 870 struct cvmx_agl_gmx_rxx_int_en_s { 871 u64 reserved_30_63 : 34; 872 u64 wol : 1; 873 u64 reserved_20_28 : 9; 874 u64 pause_drp : 1; 875 u64 phy_dupx : 1; 876 u64 phy_spd : 1; 877 u64 phy_link : 1; 878 u64 ifgerr : 1; 879 u64 coldet : 1; 880 u64 falerr : 1; 881 u64 rsverr : 1; 882 u64 pcterr : 1; 883 u64 ovrerr : 1; 884 u64 niberr : 1; 885 u64 skperr : 1; 886 u64 rcverr : 1; 887 u64 lenerr : 1; 888 u64 alnerr : 1; 889 u64 fcserr : 1; 890 u64 jabber : 1; 891 u64 maxerr : 1; 892 u64 carext : 1; 893 u64 minerr : 1; 894 } s; 895 struct cvmx_agl_gmx_rxx_int_en_cn52xx { 896 u64 reserved_20_63 : 44; 897 u64 pause_drp : 1; 898 u64 reserved_16_18 : 3; 899 u64 ifgerr : 1; 900 u64 coldet : 1; 901 u64 falerr : 1; 902 u64 rsverr : 1; 903 u64 pcterr : 1; 904 u64 ovrerr : 1; 905 u64 reserved_9_9 : 1; 906 u64 skperr : 1; 907 u64 rcverr : 1; 908 u64 lenerr : 1; 909 u64 alnerr : 1; 910 u64 fcserr : 1; 911 u64 jabber : 1; 912 u64 maxerr : 1; 913 u64 reserved_1_1 : 1; 914 u64 minerr : 1; 915 } cn52xx; 916 struct cvmx_agl_gmx_rxx_int_en_cn52xx cn52xxp1; 917 struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xx; 918 struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xxp1; 919 struct cvmx_agl_gmx_rxx_int_en_cn61xx { 920 u64 reserved_20_63 : 44; 921 u64 pause_drp : 1; 922 u64 phy_dupx : 1; 923 u64 phy_spd : 1; 924 u64 phy_link : 1; 925 u64 ifgerr : 1; 926 u64 coldet : 1; 927 u64 falerr : 1; 928 u64 rsverr : 1; 929 u64 pcterr : 1; 930 u64 ovrerr : 1; 931 u64 niberr : 1; 932 u64 skperr : 1; 933 u64 rcverr : 1; 934 u64 lenerr : 1; 935 u64 alnerr : 1; 936 u64 fcserr : 1; 937 u64 jabber : 1; 938 u64 maxerr : 1; 939 u64 carext : 1; 940 u64 minerr : 1; 941 } cn61xx; 942 struct cvmx_agl_gmx_rxx_int_en_cn61xx cn63xx; 943 struct cvmx_agl_gmx_rxx_int_en_cn61xx cn63xxp1; 944 struct cvmx_agl_gmx_rxx_int_en_cn61xx cn66xx; 945 struct cvmx_agl_gmx_rxx_int_en_cn61xx cn68xx; 946 struct cvmx_agl_gmx_rxx_int_en_cn61xx cn68xxp1; 947 struct cvmx_agl_gmx_rxx_int_en_s cn70xx; 948 struct cvmx_agl_gmx_rxx_int_en_s cn70xxp1; 949 }; 950 951 typedef union cvmx_agl_gmx_rxx_int_en cvmx_agl_gmx_rxx_int_en_t; 952 953 /** 954 * cvmx_agl_gmx_rx#_int_reg 955 * 956 * AGL_GMX_RX_INT_REG = Interrupt Register 957 * 958 * 959 * Notes: 960 * (1) exceptions will only be raised to the control processor if the 961 * corresponding bit in the AGL_GMX_RX_INT_EN register is set. 962 * 963 * (2) exception conditions 10:0 can also set the rcv/opcode in the received 964 * packet's workQ entry. The AGL_GMX_RX_FRM_CHK register provides a bit mask 965 * for configuring which conditions set the error. 966 * 967 * (3) in half duplex operation, the expectation is that collisions will appear 968 * as MINERRs. 969 * 970 * (4) JABBER - An RX Jabber error indicates that a packet was received which 971 * is longer than the maximum allowed packet as defined by the 972 * system. GMX will truncate the packet at the JABBER count. 973 * Failure to do so could lead to system instabilty. 974 * 975 * (6) MAXERR - for untagged frames, the total frame DA+SA+TL+DATA+PAD+FCS > 976 * AGL_GMX_RX_FRM_MAX. For tagged frames, DA+SA+VLAN+TL+DATA+PAD+FCS 977 * > AGL_GMX_RX_FRM_MAX + 4*VLAN_VAL + 4*VLAN_STACKED. 978 * 979 * (7) MINERR - total frame DA+SA+TL+DATA+PAD+FCS < AGL_GMX_RX_FRM_MIN. 980 * 981 * (8) ALNERR - Indicates that the packet received was not an integer number of 982 * bytes. If FCS checking is enabled, ALNERR will only assert if 983 * the FCS is bad. If FCS checking is disabled, ALNERR will 984 * assert in all non-integer frame cases. 985 * 986 * (9) Collisions - Collisions can only occur in half-duplex mode. A collision 987 * is assumed by the receiver when the received 988 * frame < AGL_GMX_RX_FRM_MIN - this is normally a MINERR 989 * 990 * (A) LENERR - Length errors occur when the received packet does not match the 991 * length field. LENERR is only checked for packets between 64 992 * and 1500 bytes. For untagged frames, the length must exact 993 * match. For tagged frames the length or length+4 must match. 994 * 995 * (B) PCTERR - checks that the frame begins with a valid PREAMBLE sequence. 996 * Does not check the number of PREAMBLE cycles. 997 * 998 * (C) OVRERR - 999 * 1000 * OVRERR is an architectural assertion check internal to GMX to 1001 * make sure no assumption was violated. In a correctly operating 1002 * system, this interrupt can never fire. 1003 * 1004 * GMX has an internal arbiter which selects which of 4 ports to 1005 * buffer in the main RX FIFO. If we normally buffer 8 bytes, 1006 * then each port will typically push a tick every 8 cycles - if 1007 * the packet interface is going as fast as possible. If there 1008 * are four ports, they push every two cycles. So that's the 1009 * assumption. That the inbound module will always be able to 1010 * consume the tick before another is produced. If that doesn't 1011 * happen - that's when OVRERR will assert. 1012 * 1013 * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 1014 */ 1015 union cvmx_agl_gmx_rxx_int_reg { 1016 u64 u64; 1017 struct cvmx_agl_gmx_rxx_int_reg_s { 1018 u64 reserved_30_63 : 34; 1019 u64 wol : 1; 1020 u64 reserved_20_28 : 9; 1021 u64 pause_drp : 1; 1022 u64 phy_dupx : 1; 1023 u64 phy_spd : 1; 1024 u64 phy_link : 1; 1025 u64 ifgerr : 1; 1026 u64 coldet : 1; 1027 u64 falerr : 1; 1028 u64 rsverr : 1; 1029 u64 pcterr : 1; 1030 u64 ovrerr : 1; 1031 u64 niberr : 1; 1032 u64 skperr : 1; 1033 u64 rcverr : 1; 1034 u64 lenerr : 1; 1035 u64 alnerr : 1; 1036 u64 fcserr : 1; 1037 u64 jabber : 1; 1038 u64 maxerr : 1; 1039 u64 carext : 1; 1040 u64 minerr : 1; 1041 } s; 1042 struct cvmx_agl_gmx_rxx_int_reg_cn52xx { 1043 u64 reserved_20_63 : 44; 1044 u64 pause_drp : 1; 1045 u64 reserved_16_18 : 3; 1046 u64 ifgerr : 1; 1047 u64 coldet : 1; 1048 u64 falerr : 1; 1049 u64 rsverr : 1; 1050 u64 pcterr : 1; 1051 u64 ovrerr : 1; 1052 u64 reserved_9_9 : 1; 1053 u64 skperr : 1; 1054 u64 rcverr : 1; 1055 u64 lenerr : 1; 1056 u64 alnerr : 1; 1057 u64 fcserr : 1; 1058 u64 jabber : 1; 1059 u64 maxerr : 1; 1060 u64 reserved_1_1 : 1; 1061 u64 minerr : 1; 1062 } cn52xx; 1063 struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn52xxp1; 1064 struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xx; 1065 struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xxp1; 1066 struct cvmx_agl_gmx_rxx_int_reg_cn61xx { 1067 u64 reserved_20_63 : 44; 1068 u64 pause_drp : 1; 1069 u64 phy_dupx : 1; 1070 u64 phy_spd : 1; 1071 u64 phy_link : 1; 1072 u64 ifgerr : 1; 1073 u64 coldet : 1; 1074 u64 falerr : 1; 1075 u64 rsverr : 1; 1076 u64 pcterr : 1; 1077 u64 ovrerr : 1; 1078 u64 niberr : 1; 1079 u64 skperr : 1; 1080 u64 rcverr : 1; 1081 u64 lenerr : 1; 1082 u64 alnerr : 1; 1083 u64 fcserr : 1; 1084 u64 jabber : 1; 1085 u64 maxerr : 1; 1086 u64 carext : 1; 1087 u64 minerr : 1; 1088 } cn61xx; 1089 struct cvmx_agl_gmx_rxx_int_reg_cn61xx cn63xx; 1090 struct cvmx_agl_gmx_rxx_int_reg_cn61xx cn63xxp1; 1091 struct cvmx_agl_gmx_rxx_int_reg_cn61xx cn66xx; 1092 struct cvmx_agl_gmx_rxx_int_reg_cn61xx cn68xx; 1093 struct cvmx_agl_gmx_rxx_int_reg_cn61xx cn68xxp1; 1094 struct cvmx_agl_gmx_rxx_int_reg_s cn70xx; 1095 struct cvmx_agl_gmx_rxx_int_reg_s cn70xxp1; 1096 }; 1097 1098 typedef union cvmx_agl_gmx_rxx_int_reg cvmx_agl_gmx_rxx_int_reg_t; 1099 1100 /** 1101 * cvmx_agl_gmx_rx#_jabber 1102 * 1103 * AGL_GMX_RX_JABBER = The max size packet after which GMX will truncate 1104 * 1105 * 1106 * Notes: 1107 * CNT must be 8-byte aligned such that CNT[2:0] == 0 1108 * 1109 * The packet that will be sent to the packet input logic will have an 1110 * additionl 8 bytes if AGL_GMX_RX_FRM_CTL[PRE_CHK] is set and 1111 * AGL_GMX_RX_FRM_CTL[PRE_STRP] is clear. The max packet that will be sent is 1112 * defined as... 1113 * 1114 * max_sized_packet = AGL_GMX_RX_JABBER[CNT]+((AGL_GMX_RX_FRM_CTL[PRE_CHK] & !AGL_GMX_RX_FRM_CTL[PRE_STRP])*8) 1115 * 1116 * Be sure the CNT field value is at least as large as the 1117 * AGL_GMX_RX_FRM_MAX[LEN] value. Failure to meet this constraint will cause 1118 * packets that are within the AGL_GMX_RX_FRM_MAX[LEN] length to be rejected 1119 * because they exceed the CNT limit. 1120 * 1121 * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 1122 */ 1123 union cvmx_agl_gmx_rxx_jabber { 1124 u64 u64; 1125 struct cvmx_agl_gmx_rxx_jabber_s { 1126 u64 reserved_16_63 : 48; 1127 u64 cnt : 16; 1128 } s; 1129 struct cvmx_agl_gmx_rxx_jabber_s cn52xx; 1130 struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1; 1131 struct cvmx_agl_gmx_rxx_jabber_s cn56xx; 1132 struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1; 1133 struct cvmx_agl_gmx_rxx_jabber_s cn61xx; 1134 struct cvmx_agl_gmx_rxx_jabber_s cn63xx; 1135 struct cvmx_agl_gmx_rxx_jabber_s cn63xxp1; 1136 struct cvmx_agl_gmx_rxx_jabber_s cn66xx; 1137 struct cvmx_agl_gmx_rxx_jabber_s cn68xx; 1138 struct cvmx_agl_gmx_rxx_jabber_s cn68xxp1; 1139 struct cvmx_agl_gmx_rxx_jabber_s cn70xx; 1140 struct cvmx_agl_gmx_rxx_jabber_s cn70xxp1; 1141 }; 1142 1143 typedef union cvmx_agl_gmx_rxx_jabber cvmx_agl_gmx_rxx_jabber_t; 1144 1145 /** 1146 * cvmx_agl_gmx_rx#_pause_drop_time 1147 * 1148 * AGL_GMX_RX_PAUSE_DROP_TIME = The TIME field in a PAUSE Packet which was dropped due to GMX RX FIFO full condition 1149 * 1150 * 1151 * Notes: 1152 * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 1153 * 1154 */ 1155 union cvmx_agl_gmx_rxx_pause_drop_time { 1156 u64 u64; 1157 struct cvmx_agl_gmx_rxx_pause_drop_time_s { 1158 u64 reserved_16_63 : 48; 1159 u64 status : 16; 1160 } s; 1161 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xx; 1162 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1; 1163 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx; 1164 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1; 1165 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn61xx; 1166 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xx; 1167 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xxp1; 1168 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn66xx; 1169 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn68xx; 1170 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn68xxp1; 1171 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn70xx; 1172 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn70xxp1; 1173 }; 1174 1175 typedef union cvmx_agl_gmx_rxx_pause_drop_time cvmx_agl_gmx_rxx_pause_drop_time_t; 1176 1177 /** 1178 * cvmx_agl_gmx_rx#_rx_inbnd 1179 * 1180 * AGL_GMX_RX_INBND = RGMII InBand Link Status 1181 * 1182 */ 1183 union cvmx_agl_gmx_rxx_rx_inbnd { 1184 u64 u64; 1185 struct cvmx_agl_gmx_rxx_rx_inbnd_s { 1186 u64 reserved_4_63 : 60; 1187 u64 duplex : 1; 1188 u64 speed : 2; 1189 u64 status : 1; 1190 } s; 1191 struct cvmx_agl_gmx_rxx_rx_inbnd_s cn61xx; 1192 struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xx; 1193 struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xxp1; 1194 struct cvmx_agl_gmx_rxx_rx_inbnd_s cn66xx; 1195 struct cvmx_agl_gmx_rxx_rx_inbnd_s cn68xx; 1196 struct cvmx_agl_gmx_rxx_rx_inbnd_s cn68xxp1; 1197 struct cvmx_agl_gmx_rxx_rx_inbnd_s cn70xx; 1198 struct cvmx_agl_gmx_rxx_rx_inbnd_s cn70xxp1; 1199 }; 1200 1201 typedef union cvmx_agl_gmx_rxx_rx_inbnd cvmx_agl_gmx_rxx_rx_inbnd_t; 1202 1203 /** 1204 * cvmx_agl_gmx_rx#_stats_ctl 1205 * 1206 * AGL_GMX_RX_STATS_CTL = RX Stats Control register 1207 * 1208 * 1209 * Notes: 1210 * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 1211 * 1212 */ 1213 union cvmx_agl_gmx_rxx_stats_ctl { 1214 u64 u64; 1215 struct cvmx_agl_gmx_rxx_stats_ctl_s { 1216 u64 reserved_1_63 : 63; 1217 u64 rd_clr : 1; 1218 } s; 1219 struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xx; 1220 struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1; 1221 struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx; 1222 struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1; 1223 struct cvmx_agl_gmx_rxx_stats_ctl_s cn61xx; 1224 struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xx; 1225 struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xxp1; 1226 struct cvmx_agl_gmx_rxx_stats_ctl_s cn66xx; 1227 struct cvmx_agl_gmx_rxx_stats_ctl_s cn68xx; 1228 struct cvmx_agl_gmx_rxx_stats_ctl_s cn68xxp1; 1229 struct cvmx_agl_gmx_rxx_stats_ctl_s cn70xx; 1230 struct cvmx_agl_gmx_rxx_stats_ctl_s cn70xxp1; 1231 }; 1232 1233 typedef union cvmx_agl_gmx_rxx_stats_ctl cvmx_agl_gmx_rxx_stats_ctl_t; 1234 1235 /** 1236 * cvmx_agl_gmx_rx#_stats_octs 1237 * 1238 * Notes: 1239 * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set 1240 * - Counters will wrap 1241 * - Not reset when MIX*_CTL[RESET] is set to 1. 1242 */ 1243 union cvmx_agl_gmx_rxx_stats_octs { 1244 u64 u64; 1245 struct cvmx_agl_gmx_rxx_stats_octs_s { 1246 u64 reserved_48_63 : 16; 1247 u64 cnt : 48; 1248 } s; 1249 struct cvmx_agl_gmx_rxx_stats_octs_s cn52xx; 1250 struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1; 1251 struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx; 1252 struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1; 1253 struct cvmx_agl_gmx_rxx_stats_octs_s cn61xx; 1254 struct cvmx_agl_gmx_rxx_stats_octs_s cn63xx; 1255 struct cvmx_agl_gmx_rxx_stats_octs_s cn63xxp1; 1256 struct cvmx_agl_gmx_rxx_stats_octs_s cn66xx; 1257 struct cvmx_agl_gmx_rxx_stats_octs_s cn68xx; 1258 struct cvmx_agl_gmx_rxx_stats_octs_s cn68xxp1; 1259 struct cvmx_agl_gmx_rxx_stats_octs_s cn70xx; 1260 struct cvmx_agl_gmx_rxx_stats_octs_s cn70xxp1; 1261 }; 1262 1263 typedef union cvmx_agl_gmx_rxx_stats_octs cvmx_agl_gmx_rxx_stats_octs_t; 1264 1265 /** 1266 * cvmx_agl_gmx_rx#_stats_octs_ctl 1267 * 1268 * Notes: 1269 * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set 1270 * - Counters will wrap 1271 * - Not reset when MIX*_CTL[RESET] is set to 1. 1272 */ 1273 union cvmx_agl_gmx_rxx_stats_octs_ctl { 1274 u64 u64; 1275 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s { 1276 u64 reserved_48_63 : 16; 1277 u64 cnt : 48; 1278 } s; 1279 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xx; 1280 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1; 1281 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx; 1282 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1; 1283 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn61xx; 1284 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xx; 1285 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xxp1; 1286 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn66xx; 1287 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn68xx; 1288 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn68xxp1; 1289 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn70xx; 1290 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn70xxp1; 1291 }; 1292 1293 typedef union cvmx_agl_gmx_rxx_stats_octs_ctl cvmx_agl_gmx_rxx_stats_octs_ctl_t; 1294 1295 /** 1296 * cvmx_agl_gmx_rx#_stats_octs_dmac 1297 * 1298 * Notes: 1299 * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set 1300 * - Counters will wrap 1301 * - Not reset when MIX*_CTL[RESET] is set to 1. 1302 */ 1303 union cvmx_agl_gmx_rxx_stats_octs_dmac { 1304 u64 u64; 1305 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s { 1306 u64 reserved_48_63 : 16; 1307 u64 cnt : 48; 1308 } s; 1309 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xx; 1310 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1; 1311 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx; 1312 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1; 1313 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn61xx; 1314 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xx; 1315 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xxp1; 1316 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn66xx; 1317 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn68xx; 1318 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn68xxp1; 1319 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn70xx; 1320 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn70xxp1; 1321 }; 1322 1323 typedef union cvmx_agl_gmx_rxx_stats_octs_dmac cvmx_agl_gmx_rxx_stats_octs_dmac_t; 1324 1325 /** 1326 * cvmx_agl_gmx_rx#_stats_octs_drp 1327 * 1328 * Notes: 1329 * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set 1330 * - Counters will wrap 1331 * - Not reset when MIX*_CTL[RESET] is set to 1. 1332 */ 1333 union cvmx_agl_gmx_rxx_stats_octs_drp { 1334 u64 u64; 1335 struct cvmx_agl_gmx_rxx_stats_octs_drp_s { 1336 u64 reserved_48_63 : 16; 1337 u64 cnt : 48; 1338 } s; 1339 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xx; 1340 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1; 1341 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx; 1342 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1; 1343 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn61xx; 1344 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xx; 1345 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xxp1; 1346 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn66xx; 1347 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn68xx; 1348 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn68xxp1; 1349 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn70xx; 1350 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn70xxp1; 1351 }; 1352 1353 typedef union cvmx_agl_gmx_rxx_stats_octs_drp cvmx_agl_gmx_rxx_stats_octs_drp_t; 1354 1355 /** 1356 * cvmx_agl_gmx_rx#_stats_pkts 1357 * 1358 * Count of good received packets - packets that are not recognized as PAUSE 1359 * packets, dropped due the DMAC filter, dropped due FIFO full status, or 1360 * have any other OPCODE (FCS, Length, etc). 1361 */ 1362 union cvmx_agl_gmx_rxx_stats_pkts { 1363 u64 u64; 1364 struct cvmx_agl_gmx_rxx_stats_pkts_s { 1365 u64 reserved_32_63 : 32; 1366 u64 cnt : 32; 1367 } s; 1368 struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xx; 1369 struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1; 1370 struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx; 1371 struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1; 1372 struct cvmx_agl_gmx_rxx_stats_pkts_s cn61xx; 1373 struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xx; 1374 struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xxp1; 1375 struct cvmx_agl_gmx_rxx_stats_pkts_s cn66xx; 1376 struct cvmx_agl_gmx_rxx_stats_pkts_s cn68xx; 1377 struct cvmx_agl_gmx_rxx_stats_pkts_s cn68xxp1; 1378 struct cvmx_agl_gmx_rxx_stats_pkts_s cn70xx; 1379 struct cvmx_agl_gmx_rxx_stats_pkts_s cn70xxp1; 1380 }; 1381 1382 typedef union cvmx_agl_gmx_rxx_stats_pkts cvmx_agl_gmx_rxx_stats_pkts_t; 1383 1384 /** 1385 * cvmx_agl_gmx_rx#_stats_pkts_bad 1386 * 1387 * Count of all packets received with some error that were not dropped 1388 * either due to the dmac filter or lack of room in the receive FIFO. 1389 */ 1390 union cvmx_agl_gmx_rxx_stats_pkts_bad { 1391 u64 u64; 1392 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s { 1393 u64 reserved_32_63 : 32; 1394 u64 cnt : 32; 1395 } s; 1396 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xx; 1397 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1; 1398 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx; 1399 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1; 1400 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn61xx; 1401 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xx; 1402 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xxp1; 1403 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn66xx; 1404 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn68xx; 1405 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn68xxp1; 1406 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn70xx; 1407 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn70xxp1; 1408 }; 1409 1410 typedef union cvmx_agl_gmx_rxx_stats_pkts_bad cvmx_agl_gmx_rxx_stats_pkts_bad_t; 1411 1412 /** 1413 * cvmx_agl_gmx_rx#_stats_pkts_ctl 1414 * 1415 * Count of all packets received that were recognized as Flow Control or 1416 * PAUSE packets. PAUSE packets with any kind of error are counted in 1417 * AGL_GMX_RX_STATS_PKTS_BAD. Pause packets can be optionally dropped or 1418 * forwarded based on the AGL_GMX_RX_FRM_CTL[CTL_DRP] bit. This count 1419 * increments regardless of whether the packet is dropped. Pause packets 1420 * will never be counted in AGL_GMX_RX_STATS_PKTS. Packets dropped due the dmac 1421 * filter will be counted in AGL_GMX_RX_STATS_PKTS_DMAC and not here. 1422 */ 1423 union cvmx_agl_gmx_rxx_stats_pkts_ctl { 1424 u64 u64; 1425 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s { 1426 u64 reserved_32_63 : 32; 1427 u64 cnt : 32; 1428 } s; 1429 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xx; 1430 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1; 1431 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx; 1432 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1; 1433 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn61xx; 1434 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xx; 1435 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xxp1; 1436 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn66xx; 1437 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn68xx; 1438 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn68xxp1; 1439 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn70xx; 1440 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn70xxp1; 1441 }; 1442 1443 typedef union cvmx_agl_gmx_rxx_stats_pkts_ctl cvmx_agl_gmx_rxx_stats_pkts_ctl_t; 1444 1445 /** 1446 * cvmx_agl_gmx_rx#_stats_pkts_dmac 1447 * 1448 * Count of all packets received that were dropped by the dmac filter. 1449 * Packets that match the DMAC will be dropped and counted here regardless 1450 * of if they were bad packets. These packets will never be counted in 1451 * AGL_GMX_RX_STATS_PKTS. 1452 * Some packets that were not able to satisify the DECISION_CNT may not 1453 * actually be dropped by Octeon, but they will be counted here as if they 1454 * were dropped. 1455 */ 1456 union cvmx_agl_gmx_rxx_stats_pkts_dmac { 1457 u64 u64; 1458 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s { 1459 u64 reserved_32_63 : 32; 1460 u64 cnt : 32; 1461 } s; 1462 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xx; 1463 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1; 1464 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx; 1465 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1; 1466 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn61xx; 1467 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xx; 1468 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xxp1; 1469 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn66xx; 1470 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn68xx; 1471 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn68xxp1; 1472 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn70xx; 1473 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn70xxp1; 1474 }; 1475 1476 typedef union cvmx_agl_gmx_rxx_stats_pkts_dmac cvmx_agl_gmx_rxx_stats_pkts_dmac_t; 1477 1478 /** 1479 * cvmx_agl_gmx_rx#_stats_pkts_drp 1480 * 1481 * Count of all packets received that were dropped due to a full receive 1482 * FIFO. This counts good and bad packets received - all packets dropped by 1483 * the FIFO. It does not count packets dropped by the dmac or pause packet 1484 * filters. 1485 */ 1486 union cvmx_agl_gmx_rxx_stats_pkts_drp { 1487 u64 u64; 1488 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s { 1489 u64 reserved_32_63 : 32; 1490 u64 cnt : 32; 1491 } s; 1492 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xx; 1493 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1; 1494 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx; 1495 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1; 1496 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn61xx; 1497 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xx; 1498 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xxp1; 1499 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn66xx; 1500 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn68xx; 1501 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn68xxp1; 1502 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn70xx; 1503 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn70xxp1; 1504 }; 1505 1506 typedef union cvmx_agl_gmx_rxx_stats_pkts_drp cvmx_agl_gmx_rxx_stats_pkts_drp_t; 1507 1508 /** 1509 * cvmx_agl_gmx_rx#_udd_skp 1510 * 1511 * AGL_GMX_RX_UDD_SKP = Amount of User-defined data before the start of the L2 data 1512 * 1513 * 1514 * Notes: 1515 * (1) The skip bytes are part of the packet and will be sent down the NCB 1516 * packet interface and will be handled by PKI. 1517 * 1518 * (2) The system can determine if the UDD bytes are included in the FCS check 1519 * by using the FCSSEL field - if the FCS check is enabled. 1520 * 1521 * (3) Assume that the preamble/sfd is always at the start of the frame - even 1522 * before UDD bytes. In most cases, there will be no preamble in these 1523 * cases since it will be MII to MII communication without a PHY 1524 * involved. 1525 * 1526 * (4) We can still do address filtering and control packet filtering is the 1527 * user desires. 1528 * 1529 * (5) UDD_SKP must be 0 in half-duplex operation unless 1530 * AGL_GMX_RX_FRM_CTL[PRE_CHK] is clear. If AGL_GMX_RX_FRM_CTL[PRE_CHK] is set, 1531 * then UDD_SKP will normally be 8. 1532 * 1533 * (6) In all cases, the UDD bytes will be sent down the packet interface as 1534 * part of the packet. The UDD bytes are never stripped from the actual 1535 * packet. 1536 * 1537 * (7) If LEN != 0, then AGL_GMX_RX_FRM_CHK[LENERR] will be disabled and AGL_GMX_RX_INT_REG[LENERR] will be zero 1538 * 1539 * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 1540 */ 1541 union cvmx_agl_gmx_rxx_udd_skp { 1542 u64 u64; 1543 struct cvmx_agl_gmx_rxx_udd_skp_s { 1544 u64 reserved_9_63 : 55; 1545 u64 fcssel : 1; 1546 u64 reserved_7_7 : 1; 1547 u64 len : 7; 1548 } s; 1549 struct cvmx_agl_gmx_rxx_udd_skp_s cn52xx; 1550 struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1; 1551 struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx; 1552 struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1; 1553 struct cvmx_agl_gmx_rxx_udd_skp_s cn61xx; 1554 struct cvmx_agl_gmx_rxx_udd_skp_s cn63xx; 1555 struct cvmx_agl_gmx_rxx_udd_skp_s cn63xxp1; 1556 struct cvmx_agl_gmx_rxx_udd_skp_s cn66xx; 1557 struct cvmx_agl_gmx_rxx_udd_skp_s cn68xx; 1558 struct cvmx_agl_gmx_rxx_udd_skp_s cn68xxp1; 1559 struct cvmx_agl_gmx_rxx_udd_skp_s cn70xx; 1560 struct cvmx_agl_gmx_rxx_udd_skp_s cn70xxp1; 1561 }; 1562 1563 typedef union cvmx_agl_gmx_rxx_udd_skp cvmx_agl_gmx_rxx_udd_skp_t; 1564 1565 /** 1566 * cvmx_agl_gmx_rx_bp_drop# 1567 * 1568 * AGL_GMX_RX_BP_DROP = FIFO mark for packet drop 1569 * 1570 * 1571 * Notes: 1572 * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 1573 * 1574 */ 1575 union cvmx_agl_gmx_rx_bp_dropx { 1576 u64 u64; 1577 struct cvmx_agl_gmx_rx_bp_dropx_s { 1578 u64 reserved_6_63 : 58; 1579 u64 mark : 6; 1580 } s; 1581 struct cvmx_agl_gmx_rx_bp_dropx_s cn52xx; 1582 struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1; 1583 struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx; 1584 struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1; 1585 struct cvmx_agl_gmx_rx_bp_dropx_s cn61xx; 1586 struct cvmx_agl_gmx_rx_bp_dropx_s cn63xx; 1587 struct cvmx_agl_gmx_rx_bp_dropx_s cn63xxp1; 1588 struct cvmx_agl_gmx_rx_bp_dropx_s cn66xx; 1589 struct cvmx_agl_gmx_rx_bp_dropx_s cn68xx; 1590 struct cvmx_agl_gmx_rx_bp_dropx_s cn68xxp1; 1591 struct cvmx_agl_gmx_rx_bp_dropx_s cn70xx; 1592 struct cvmx_agl_gmx_rx_bp_dropx_s cn70xxp1; 1593 }; 1594 1595 typedef union cvmx_agl_gmx_rx_bp_dropx cvmx_agl_gmx_rx_bp_dropx_t; 1596 1597 /** 1598 * cvmx_agl_gmx_rx_bp_off# 1599 * 1600 * AGL_GMX_RX_BP_OFF = Lowater mark for packet drop 1601 * 1602 * 1603 * Notes: 1604 * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 1605 * 1606 */ 1607 union cvmx_agl_gmx_rx_bp_offx { 1608 u64 u64; 1609 struct cvmx_agl_gmx_rx_bp_offx_s { 1610 u64 reserved_6_63 : 58; 1611 u64 mark : 6; 1612 } s; 1613 struct cvmx_agl_gmx_rx_bp_offx_s cn52xx; 1614 struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1; 1615 struct cvmx_agl_gmx_rx_bp_offx_s cn56xx; 1616 struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1; 1617 struct cvmx_agl_gmx_rx_bp_offx_s cn61xx; 1618 struct cvmx_agl_gmx_rx_bp_offx_s cn63xx; 1619 struct cvmx_agl_gmx_rx_bp_offx_s cn63xxp1; 1620 struct cvmx_agl_gmx_rx_bp_offx_s cn66xx; 1621 struct cvmx_agl_gmx_rx_bp_offx_s cn68xx; 1622 struct cvmx_agl_gmx_rx_bp_offx_s cn68xxp1; 1623 struct cvmx_agl_gmx_rx_bp_offx_s cn70xx; 1624 struct cvmx_agl_gmx_rx_bp_offx_s cn70xxp1; 1625 }; 1626 1627 typedef union cvmx_agl_gmx_rx_bp_offx cvmx_agl_gmx_rx_bp_offx_t; 1628 1629 /** 1630 * cvmx_agl_gmx_rx_bp_on# 1631 * 1632 * AGL_GMX_RX_BP_ON = Hiwater mark for port/interface backpressure 1633 * 1634 * 1635 * Notes: 1636 * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 1637 * 1638 */ 1639 union cvmx_agl_gmx_rx_bp_onx { 1640 u64 u64; 1641 struct cvmx_agl_gmx_rx_bp_onx_s { 1642 u64 reserved_9_63 : 55; 1643 u64 mark : 9; 1644 } s; 1645 struct cvmx_agl_gmx_rx_bp_onx_s cn52xx; 1646 struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1; 1647 struct cvmx_agl_gmx_rx_bp_onx_s cn56xx; 1648 struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1; 1649 struct cvmx_agl_gmx_rx_bp_onx_s cn61xx; 1650 struct cvmx_agl_gmx_rx_bp_onx_s cn63xx; 1651 struct cvmx_agl_gmx_rx_bp_onx_s cn63xxp1; 1652 struct cvmx_agl_gmx_rx_bp_onx_s cn66xx; 1653 struct cvmx_agl_gmx_rx_bp_onx_s cn68xx; 1654 struct cvmx_agl_gmx_rx_bp_onx_s cn68xxp1; 1655 struct cvmx_agl_gmx_rx_bp_onx_s cn70xx; 1656 struct cvmx_agl_gmx_rx_bp_onx_s cn70xxp1; 1657 }; 1658 1659 typedef union cvmx_agl_gmx_rx_bp_onx cvmx_agl_gmx_rx_bp_onx_t; 1660 1661 /** 1662 * cvmx_agl_gmx_rx_prt_info 1663 * 1664 * AGL_GMX_RX_PRT_INFO = state information for the ports 1665 * 1666 * 1667 * Notes: 1668 * COMMIT[0], DROP[0] will be reset when MIX0_CTL[RESET] is set to 1. 1669 * COMMIT[1], DROP[1] will be reset when MIX1_CTL[RESET] is set to 1. 1670 */ 1671 union cvmx_agl_gmx_rx_prt_info { 1672 u64 u64; 1673 struct cvmx_agl_gmx_rx_prt_info_s { 1674 u64 reserved_18_63 : 46; 1675 u64 drop : 2; 1676 u64 reserved_2_15 : 14; 1677 u64 commit : 2; 1678 } s; 1679 struct cvmx_agl_gmx_rx_prt_info_s cn52xx; 1680 struct cvmx_agl_gmx_rx_prt_info_s cn52xxp1; 1681 struct cvmx_agl_gmx_rx_prt_info_cn56xx { 1682 u64 reserved_17_63 : 47; 1683 u64 drop : 1; 1684 u64 reserved_1_15 : 15; 1685 u64 commit : 1; 1686 } cn56xx; 1687 struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1; 1688 struct cvmx_agl_gmx_rx_prt_info_s cn61xx; 1689 struct cvmx_agl_gmx_rx_prt_info_s cn63xx; 1690 struct cvmx_agl_gmx_rx_prt_info_s cn63xxp1; 1691 struct cvmx_agl_gmx_rx_prt_info_s cn66xx; 1692 struct cvmx_agl_gmx_rx_prt_info_s cn68xx; 1693 struct cvmx_agl_gmx_rx_prt_info_s cn68xxp1; 1694 struct cvmx_agl_gmx_rx_prt_info_cn56xx cn70xx; 1695 struct cvmx_agl_gmx_rx_prt_info_cn56xx cn70xxp1; 1696 }; 1697 1698 typedef union cvmx_agl_gmx_rx_prt_info cvmx_agl_gmx_rx_prt_info_t; 1699 1700 /** 1701 * cvmx_agl_gmx_rx_tx_status 1702 * 1703 * AGL_GMX_RX_TX_STATUS = GMX RX/TX Status 1704 * 1705 * 1706 * Notes: 1707 * RX[0], TX[0] will be reset when MIX0_CTL[RESET] is set to 1. 1708 * RX[1], TX[1] will be reset when MIX1_CTL[RESET] is set to 1. 1709 */ 1710 union cvmx_agl_gmx_rx_tx_status { 1711 u64 u64; 1712 struct cvmx_agl_gmx_rx_tx_status_s { 1713 u64 reserved_6_63 : 58; 1714 u64 tx : 2; 1715 u64 reserved_2_3 : 2; 1716 u64 rx : 2; 1717 } s; 1718 struct cvmx_agl_gmx_rx_tx_status_s cn52xx; 1719 struct cvmx_agl_gmx_rx_tx_status_s cn52xxp1; 1720 struct cvmx_agl_gmx_rx_tx_status_cn56xx { 1721 u64 reserved_5_63 : 59; 1722 u64 tx : 1; 1723 u64 reserved_1_3 : 3; 1724 u64 rx : 1; 1725 } cn56xx; 1726 struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1; 1727 struct cvmx_agl_gmx_rx_tx_status_s cn61xx; 1728 struct cvmx_agl_gmx_rx_tx_status_s cn63xx; 1729 struct cvmx_agl_gmx_rx_tx_status_s cn63xxp1; 1730 struct cvmx_agl_gmx_rx_tx_status_s cn66xx; 1731 struct cvmx_agl_gmx_rx_tx_status_s cn68xx; 1732 struct cvmx_agl_gmx_rx_tx_status_s cn68xxp1; 1733 struct cvmx_agl_gmx_rx_tx_status_cn56xx cn70xx; 1734 struct cvmx_agl_gmx_rx_tx_status_cn56xx cn70xxp1; 1735 }; 1736 1737 typedef union cvmx_agl_gmx_rx_tx_status cvmx_agl_gmx_rx_tx_status_t; 1738 1739 /** 1740 * cvmx_agl_gmx_smac# 1741 * 1742 * AGL_GMX_SMAC = Packet SMAC 1743 * 1744 * 1745 * Notes: 1746 * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 1747 * 1748 */ 1749 union cvmx_agl_gmx_smacx { 1750 u64 u64; 1751 struct cvmx_agl_gmx_smacx_s { 1752 u64 reserved_48_63 : 16; 1753 u64 smac : 48; 1754 } s; 1755 struct cvmx_agl_gmx_smacx_s cn52xx; 1756 struct cvmx_agl_gmx_smacx_s cn52xxp1; 1757 struct cvmx_agl_gmx_smacx_s cn56xx; 1758 struct cvmx_agl_gmx_smacx_s cn56xxp1; 1759 struct cvmx_agl_gmx_smacx_s cn61xx; 1760 struct cvmx_agl_gmx_smacx_s cn63xx; 1761 struct cvmx_agl_gmx_smacx_s cn63xxp1; 1762 struct cvmx_agl_gmx_smacx_s cn66xx; 1763 struct cvmx_agl_gmx_smacx_s cn68xx; 1764 struct cvmx_agl_gmx_smacx_s cn68xxp1; 1765 struct cvmx_agl_gmx_smacx_s cn70xx; 1766 struct cvmx_agl_gmx_smacx_s cn70xxp1; 1767 }; 1768 1769 typedef union cvmx_agl_gmx_smacx cvmx_agl_gmx_smacx_t; 1770 1771 /** 1772 * cvmx_agl_gmx_stat_bp 1773 * 1774 * AGL_GMX_STAT_BP = Number of cycles that the TX/Stats block has help up operation 1775 * 1776 * 1777 * Notes: 1778 * Additionally reset when both MIX0/1_CTL[RESET] are set to 1. 1779 * 1780 * 1781 * 1782 * It has no relationship with the TX FIFO per se. The TX engine sends packets 1783 * from PKO and upon completion, sends a command to the TX stats block for an 1784 * update based on the packet size. The stats operation can take a few cycles - 1785 * normally not enough to be visible considering the 64B min packet size that is 1786 * ethernet convention. 1787 * 1788 * In the rare case in which SW attempted to schedule really, really, small packets 1789 * or the sclk (6xxx) is running ass-slow, then the stats updates may not happen in 1790 * real time and can back up the TX engine. 1791 * 1792 * This counter is the number of cycles in which the TX engine was stalled. In 1793 * normal operation, it should always be zeros. 1794 */ 1795 union cvmx_agl_gmx_stat_bp { 1796 u64 u64; 1797 struct cvmx_agl_gmx_stat_bp_s { 1798 u64 reserved_17_63 : 47; 1799 u64 bp : 1; 1800 u64 cnt : 16; 1801 } s; 1802 struct cvmx_agl_gmx_stat_bp_s cn52xx; 1803 struct cvmx_agl_gmx_stat_bp_s cn52xxp1; 1804 struct cvmx_agl_gmx_stat_bp_s cn56xx; 1805 struct cvmx_agl_gmx_stat_bp_s cn56xxp1; 1806 struct cvmx_agl_gmx_stat_bp_s cn61xx; 1807 struct cvmx_agl_gmx_stat_bp_s cn63xx; 1808 struct cvmx_agl_gmx_stat_bp_s cn63xxp1; 1809 struct cvmx_agl_gmx_stat_bp_s cn66xx; 1810 struct cvmx_agl_gmx_stat_bp_s cn68xx; 1811 struct cvmx_agl_gmx_stat_bp_s cn68xxp1; 1812 struct cvmx_agl_gmx_stat_bp_s cn70xx; 1813 struct cvmx_agl_gmx_stat_bp_s cn70xxp1; 1814 }; 1815 1816 typedef union cvmx_agl_gmx_stat_bp cvmx_agl_gmx_stat_bp_t; 1817 1818 /** 1819 * cvmx_agl_gmx_tx#_append 1820 * 1821 * AGL_GMX_TX_APPEND = Packet TX Append Control 1822 * 1823 * 1824 * Notes: 1825 * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 1826 * 1827 */ 1828 union cvmx_agl_gmx_txx_append { 1829 u64 u64; 1830 struct cvmx_agl_gmx_txx_append_s { 1831 u64 reserved_4_63 : 60; 1832 u64 force_fcs : 1; 1833 u64 fcs : 1; 1834 u64 pad : 1; 1835 u64 preamble : 1; 1836 } s; 1837 struct cvmx_agl_gmx_txx_append_s cn52xx; 1838 struct cvmx_agl_gmx_txx_append_s cn52xxp1; 1839 struct cvmx_agl_gmx_txx_append_s cn56xx; 1840 struct cvmx_agl_gmx_txx_append_s cn56xxp1; 1841 struct cvmx_agl_gmx_txx_append_s cn61xx; 1842 struct cvmx_agl_gmx_txx_append_s cn63xx; 1843 struct cvmx_agl_gmx_txx_append_s cn63xxp1; 1844 struct cvmx_agl_gmx_txx_append_s cn66xx; 1845 struct cvmx_agl_gmx_txx_append_s cn68xx; 1846 struct cvmx_agl_gmx_txx_append_s cn68xxp1; 1847 struct cvmx_agl_gmx_txx_append_s cn70xx; 1848 struct cvmx_agl_gmx_txx_append_s cn70xxp1; 1849 }; 1850 1851 typedef union cvmx_agl_gmx_txx_append cvmx_agl_gmx_txx_append_t; 1852 1853 /** 1854 * cvmx_agl_gmx_tx#_clk 1855 * 1856 * AGL_GMX_TX_CLK = RGMII TX Clock Generation Register 1857 * 1858 * 1859 * Notes: 1860 * Normal Programming Values: 1861 * (1) RGMII, 1000Mbs (AGL_GMX_PRT_CFG[SPEED]==1), CLK_CNT == 1 1862 * (2) RGMII, 10/100Mbs (AGL_GMX_PRT_CFG[SPEED]==0), CLK_CNT == 50/5 1863 * (3) MII, 10/100Mbs (AGL_GMX_PRT_CFG[SPEED]==0), CLK_CNT == 1 1864 * 1865 * RGMII Example: 1866 * Given a 125MHz PLL reference clock... 1867 * CLK_CNT == 1 ==> 125.0MHz TXC clock period (8ns* 1) 1868 * CLK_CNT == 5 ==> 25.0MHz TXC clock period (8ns* 5) 1869 * CLK_CNT == 50 ==> 2.5MHz TXC clock period (8ns*50) 1870 * 1871 * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 1872 */ 1873 union cvmx_agl_gmx_txx_clk { 1874 u64 u64; 1875 struct cvmx_agl_gmx_txx_clk_s { 1876 u64 reserved_6_63 : 58; 1877 u64 clk_cnt : 6; 1878 } s; 1879 struct cvmx_agl_gmx_txx_clk_s cn61xx; 1880 struct cvmx_agl_gmx_txx_clk_s cn63xx; 1881 struct cvmx_agl_gmx_txx_clk_s cn63xxp1; 1882 struct cvmx_agl_gmx_txx_clk_s cn66xx; 1883 struct cvmx_agl_gmx_txx_clk_s cn68xx; 1884 struct cvmx_agl_gmx_txx_clk_s cn68xxp1; 1885 struct cvmx_agl_gmx_txx_clk_s cn70xx; 1886 struct cvmx_agl_gmx_txx_clk_s cn70xxp1; 1887 }; 1888 1889 typedef union cvmx_agl_gmx_txx_clk cvmx_agl_gmx_txx_clk_t; 1890 1891 /** 1892 * cvmx_agl_gmx_tx#_ctl 1893 * 1894 * AGL_GMX_TX_CTL = TX Control register 1895 * 1896 * 1897 * Notes: 1898 * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 1899 * 1900 */ 1901 union cvmx_agl_gmx_txx_ctl { 1902 u64 u64; 1903 struct cvmx_agl_gmx_txx_ctl_s { 1904 u64 reserved_2_63 : 62; 1905 u64 xsdef_en : 1; 1906 u64 xscol_en : 1; 1907 } s; 1908 struct cvmx_agl_gmx_txx_ctl_s cn52xx; 1909 struct cvmx_agl_gmx_txx_ctl_s cn52xxp1; 1910 struct cvmx_agl_gmx_txx_ctl_s cn56xx; 1911 struct cvmx_agl_gmx_txx_ctl_s cn56xxp1; 1912 struct cvmx_agl_gmx_txx_ctl_s cn61xx; 1913 struct cvmx_agl_gmx_txx_ctl_s cn63xx; 1914 struct cvmx_agl_gmx_txx_ctl_s cn63xxp1; 1915 struct cvmx_agl_gmx_txx_ctl_s cn66xx; 1916 struct cvmx_agl_gmx_txx_ctl_s cn68xx; 1917 struct cvmx_agl_gmx_txx_ctl_s cn68xxp1; 1918 struct cvmx_agl_gmx_txx_ctl_s cn70xx; 1919 struct cvmx_agl_gmx_txx_ctl_s cn70xxp1; 1920 }; 1921 1922 typedef union cvmx_agl_gmx_txx_ctl cvmx_agl_gmx_txx_ctl_t; 1923 1924 /** 1925 * cvmx_agl_gmx_tx#_min_pkt 1926 * 1927 * AGL_GMX_TX_MIN_PKT = Packet TX Min Size Packet (PAD upto min size) 1928 * 1929 * 1930 * Notes: 1931 * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 1932 * 1933 */ 1934 union cvmx_agl_gmx_txx_min_pkt { 1935 u64 u64; 1936 struct cvmx_agl_gmx_txx_min_pkt_s { 1937 u64 reserved_8_63 : 56; 1938 u64 min_size : 8; 1939 } s; 1940 struct cvmx_agl_gmx_txx_min_pkt_s cn52xx; 1941 struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1; 1942 struct cvmx_agl_gmx_txx_min_pkt_s cn56xx; 1943 struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1; 1944 struct cvmx_agl_gmx_txx_min_pkt_s cn61xx; 1945 struct cvmx_agl_gmx_txx_min_pkt_s cn63xx; 1946 struct cvmx_agl_gmx_txx_min_pkt_s cn63xxp1; 1947 struct cvmx_agl_gmx_txx_min_pkt_s cn66xx; 1948 struct cvmx_agl_gmx_txx_min_pkt_s cn68xx; 1949 struct cvmx_agl_gmx_txx_min_pkt_s cn68xxp1; 1950 struct cvmx_agl_gmx_txx_min_pkt_s cn70xx; 1951 struct cvmx_agl_gmx_txx_min_pkt_s cn70xxp1; 1952 }; 1953 1954 typedef union cvmx_agl_gmx_txx_min_pkt cvmx_agl_gmx_txx_min_pkt_t; 1955 1956 /** 1957 * cvmx_agl_gmx_tx#_pause_pkt_interval 1958 * 1959 * AGL_GMX_TX_PAUSE_PKT_INTERVAL = Packet TX Pause Packet transmission interval - how often PAUSE packets will be sent 1960 * 1961 * 1962 * Notes: 1963 * Choosing proper values of AGL_GMX_TX_PAUSE_PKT_TIME[TIME] and 1964 * AGL_GMX_TX_PAUSE_PKT_INTERVAL[INTERVAL] can be challenging to the system 1965 * designer. It is suggested that TIME be much greater than INTERVAL and 1966 * AGL_GMX_TX_PAUSE_ZERO[SEND] be set. This allows a periodic refresh of the PAUSE 1967 * count and then when the backpressure condition is lifted, a PAUSE packet 1968 * with TIME==0 will be sent indicating that Octane is ready for additional 1969 * data. 1970 * 1971 * If the system chooses to not set AGL_GMX_TX_PAUSE_ZERO[SEND], then it is 1972 * suggested that TIME and INTERVAL are programmed such that they satisify the 1973 * following rule... 1974 * 1975 * INTERVAL <= TIME - (largest_pkt_size + IFG + pause_pkt_size) 1976 * 1977 * where largest_pkt_size is that largest packet that the system can send 1978 * (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size 1979 * of the PAUSE packet (normally 64B). 1980 * 1981 * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 1982 */ 1983 union cvmx_agl_gmx_txx_pause_pkt_interval { 1984 u64 u64; 1985 struct cvmx_agl_gmx_txx_pause_pkt_interval_s { 1986 u64 reserved_16_63 : 48; 1987 u64 interval : 16; 1988 } s; 1989 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xx; 1990 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1; 1991 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx; 1992 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1; 1993 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn61xx; 1994 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xx; 1995 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xxp1; 1996 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn66xx; 1997 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn68xx; 1998 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn68xxp1; 1999 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn70xx; 2000 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn70xxp1; 2001 }; 2002 2003 typedef union cvmx_agl_gmx_txx_pause_pkt_interval cvmx_agl_gmx_txx_pause_pkt_interval_t; 2004 2005 /** 2006 * cvmx_agl_gmx_tx#_pause_pkt_time 2007 * 2008 * AGL_GMX_TX_PAUSE_PKT_TIME = Packet TX Pause Packet pause_time field 2009 * 2010 * 2011 * Notes: 2012 * Choosing proper values of AGL_GMX_TX_PAUSE_PKT_TIME[TIME] and 2013 * AGL_GMX_TX_PAUSE_PKT_INTERVAL[INTERVAL] can be challenging to the system 2014 * designer. It is suggested that TIME be much greater than INTERVAL and 2015 * AGL_GMX_TX_PAUSE_ZERO[SEND] be set. This allows a periodic refresh of the PAUSE 2016 * count and then when the backpressure condition is lifted, a PAUSE packet 2017 * with TIME==0 will be sent indicating that Octane is ready for additional 2018 * data. 2019 * 2020 * If the system chooses to not set AGL_GMX_TX_PAUSE_ZERO[SEND], then it is 2021 * suggested that TIME and INTERVAL are programmed such that they satisify the 2022 * following rule... 2023 * 2024 * INTERVAL <= TIME - (largest_pkt_size + IFG + pause_pkt_size) 2025 * 2026 * where largest_pkt_size is that largest packet that the system can send 2027 * (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size 2028 * of the PAUSE packet (normally 64B). 2029 * 2030 * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 2031 */ 2032 union cvmx_agl_gmx_txx_pause_pkt_time { 2033 u64 u64; 2034 struct cvmx_agl_gmx_txx_pause_pkt_time_s { 2035 u64 reserved_16_63 : 48; 2036 u64 time : 16; 2037 } s; 2038 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xx; 2039 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1; 2040 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx; 2041 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1; 2042 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn61xx; 2043 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xx; 2044 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xxp1; 2045 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn66xx; 2046 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn68xx; 2047 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn68xxp1; 2048 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn70xx; 2049 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn70xxp1; 2050 }; 2051 2052 typedef union cvmx_agl_gmx_txx_pause_pkt_time cvmx_agl_gmx_txx_pause_pkt_time_t; 2053 2054 /** 2055 * cvmx_agl_gmx_tx#_pause_togo 2056 * 2057 * AGL_GMX_TX_PAUSE_TOGO = Packet TX Amount of time remaining to backpressure 2058 * 2059 * 2060 * Notes: 2061 * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 2062 * 2063 */ 2064 union cvmx_agl_gmx_txx_pause_togo { 2065 u64 u64; 2066 struct cvmx_agl_gmx_txx_pause_togo_s { 2067 u64 reserved_16_63 : 48; 2068 u64 time : 16; 2069 } s; 2070 struct cvmx_agl_gmx_txx_pause_togo_s cn52xx; 2071 struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1; 2072 struct cvmx_agl_gmx_txx_pause_togo_s cn56xx; 2073 struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1; 2074 struct cvmx_agl_gmx_txx_pause_togo_s cn61xx; 2075 struct cvmx_agl_gmx_txx_pause_togo_s cn63xx; 2076 struct cvmx_agl_gmx_txx_pause_togo_s cn63xxp1; 2077 struct cvmx_agl_gmx_txx_pause_togo_s cn66xx; 2078 struct cvmx_agl_gmx_txx_pause_togo_s cn68xx; 2079 struct cvmx_agl_gmx_txx_pause_togo_s cn68xxp1; 2080 struct cvmx_agl_gmx_txx_pause_togo_s cn70xx; 2081 struct cvmx_agl_gmx_txx_pause_togo_s cn70xxp1; 2082 }; 2083 2084 typedef union cvmx_agl_gmx_txx_pause_togo cvmx_agl_gmx_txx_pause_togo_t; 2085 2086 /** 2087 * cvmx_agl_gmx_tx#_pause_zero 2088 * 2089 * AGL_GMX_TX_PAUSE_ZERO = Packet TX Amount of time remaining to backpressure 2090 * 2091 * 2092 * Notes: 2093 * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 2094 * 2095 */ 2096 union cvmx_agl_gmx_txx_pause_zero { 2097 u64 u64; 2098 struct cvmx_agl_gmx_txx_pause_zero_s { 2099 u64 reserved_1_63 : 63; 2100 u64 send : 1; 2101 } s; 2102 struct cvmx_agl_gmx_txx_pause_zero_s cn52xx; 2103 struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1; 2104 struct cvmx_agl_gmx_txx_pause_zero_s cn56xx; 2105 struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1; 2106 struct cvmx_agl_gmx_txx_pause_zero_s cn61xx; 2107 struct cvmx_agl_gmx_txx_pause_zero_s cn63xx; 2108 struct cvmx_agl_gmx_txx_pause_zero_s cn63xxp1; 2109 struct cvmx_agl_gmx_txx_pause_zero_s cn66xx; 2110 struct cvmx_agl_gmx_txx_pause_zero_s cn68xx; 2111 struct cvmx_agl_gmx_txx_pause_zero_s cn68xxp1; 2112 struct cvmx_agl_gmx_txx_pause_zero_s cn70xx; 2113 struct cvmx_agl_gmx_txx_pause_zero_s cn70xxp1; 2114 }; 2115 2116 typedef union cvmx_agl_gmx_txx_pause_zero cvmx_agl_gmx_txx_pause_zero_t; 2117 2118 /** 2119 * cvmx_agl_gmx_tx#_soft_pause 2120 * 2121 * AGL_GMX_TX_SOFT_PAUSE = Packet TX Software Pause 2122 * 2123 * 2124 * Notes: 2125 * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 2126 * 2127 */ 2128 union cvmx_agl_gmx_txx_soft_pause { 2129 u64 u64; 2130 struct cvmx_agl_gmx_txx_soft_pause_s { 2131 u64 reserved_16_63 : 48; 2132 u64 time : 16; 2133 } s; 2134 struct cvmx_agl_gmx_txx_soft_pause_s cn52xx; 2135 struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1; 2136 struct cvmx_agl_gmx_txx_soft_pause_s cn56xx; 2137 struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1; 2138 struct cvmx_agl_gmx_txx_soft_pause_s cn61xx; 2139 struct cvmx_agl_gmx_txx_soft_pause_s cn63xx; 2140 struct cvmx_agl_gmx_txx_soft_pause_s cn63xxp1; 2141 struct cvmx_agl_gmx_txx_soft_pause_s cn66xx; 2142 struct cvmx_agl_gmx_txx_soft_pause_s cn68xx; 2143 struct cvmx_agl_gmx_txx_soft_pause_s cn68xxp1; 2144 struct cvmx_agl_gmx_txx_soft_pause_s cn70xx; 2145 struct cvmx_agl_gmx_txx_soft_pause_s cn70xxp1; 2146 }; 2147 2148 typedef union cvmx_agl_gmx_txx_soft_pause cvmx_agl_gmx_txx_soft_pause_t; 2149 2150 /** 2151 * cvmx_agl_gmx_tx#_stat0 2152 * 2153 * AGL_GMX_TX_STAT0 = AGL_GMX_TX_STATS_XSDEF / AGL_GMX_TX_STATS_XSCOL 2154 * 2155 * 2156 * Notes: 2157 * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set 2158 * - Counters will wrap 2159 * - Not reset when MIX*_CTL[RESET] is set to 1. 2160 */ 2161 union cvmx_agl_gmx_txx_stat0 { 2162 u64 u64; 2163 struct cvmx_agl_gmx_txx_stat0_s { 2164 u64 xsdef : 32; 2165 u64 xscol : 32; 2166 } s; 2167 struct cvmx_agl_gmx_txx_stat0_s cn52xx; 2168 struct cvmx_agl_gmx_txx_stat0_s cn52xxp1; 2169 struct cvmx_agl_gmx_txx_stat0_s cn56xx; 2170 struct cvmx_agl_gmx_txx_stat0_s cn56xxp1; 2171 struct cvmx_agl_gmx_txx_stat0_s cn61xx; 2172 struct cvmx_agl_gmx_txx_stat0_s cn63xx; 2173 struct cvmx_agl_gmx_txx_stat0_s cn63xxp1; 2174 struct cvmx_agl_gmx_txx_stat0_s cn66xx; 2175 struct cvmx_agl_gmx_txx_stat0_s cn68xx; 2176 struct cvmx_agl_gmx_txx_stat0_s cn68xxp1; 2177 struct cvmx_agl_gmx_txx_stat0_s cn70xx; 2178 struct cvmx_agl_gmx_txx_stat0_s cn70xxp1; 2179 }; 2180 2181 typedef union cvmx_agl_gmx_txx_stat0 cvmx_agl_gmx_txx_stat0_t; 2182 2183 /** 2184 * cvmx_agl_gmx_tx#_stat1 2185 * 2186 * AGL_GMX_TX_STAT1 = AGL_GMX_TX_STATS_SCOL / AGL_GMX_TX_STATS_MCOL 2187 * 2188 * 2189 * Notes: 2190 * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set 2191 * - Counters will wrap 2192 * - Not reset when MIX*_CTL[RESET] is set to 1. 2193 */ 2194 union cvmx_agl_gmx_txx_stat1 { 2195 u64 u64; 2196 struct cvmx_agl_gmx_txx_stat1_s { 2197 u64 scol : 32; 2198 u64 mcol : 32; 2199 } s; 2200 struct cvmx_agl_gmx_txx_stat1_s cn52xx; 2201 struct cvmx_agl_gmx_txx_stat1_s cn52xxp1; 2202 struct cvmx_agl_gmx_txx_stat1_s cn56xx; 2203 struct cvmx_agl_gmx_txx_stat1_s cn56xxp1; 2204 struct cvmx_agl_gmx_txx_stat1_s cn61xx; 2205 struct cvmx_agl_gmx_txx_stat1_s cn63xx; 2206 struct cvmx_agl_gmx_txx_stat1_s cn63xxp1; 2207 struct cvmx_agl_gmx_txx_stat1_s cn66xx; 2208 struct cvmx_agl_gmx_txx_stat1_s cn68xx; 2209 struct cvmx_agl_gmx_txx_stat1_s cn68xxp1; 2210 struct cvmx_agl_gmx_txx_stat1_s cn70xx; 2211 struct cvmx_agl_gmx_txx_stat1_s cn70xxp1; 2212 }; 2213 2214 typedef union cvmx_agl_gmx_txx_stat1 cvmx_agl_gmx_txx_stat1_t; 2215 2216 /** 2217 * cvmx_agl_gmx_tx#_stat2 2218 * 2219 * AGL_GMX_TX_STAT2 = AGL_GMX_TX_STATS_OCTS 2220 * 2221 * 2222 * Notes: 2223 * - Octect counts are the sum of all data transmitted on the wire including 2224 * packet data, pad bytes, fcs bytes, pause bytes, and jam bytes. The octect 2225 * counts do not include PREAMBLE byte or EXTEND cycles. 2226 * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set 2227 * - Counters will wrap 2228 * - Not reset when MIX*_CTL[RESET] is set to 1. 2229 */ 2230 union cvmx_agl_gmx_txx_stat2 { 2231 u64 u64; 2232 struct cvmx_agl_gmx_txx_stat2_s { 2233 u64 reserved_48_63 : 16; 2234 u64 octs : 48; 2235 } s; 2236 struct cvmx_agl_gmx_txx_stat2_s cn52xx; 2237 struct cvmx_agl_gmx_txx_stat2_s cn52xxp1; 2238 struct cvmx_agl_gmx_txx_stat2_s cn56xx; 2239 struct cvmx_agl_gmx_txx_stat2_s cn56xxp1; 2240 struct cvmx_agl_gmx_txx_stat2_s cn61xx; 2241 struct cvmx_agl_gmx_txx_stat2_s cn63xx; 2242 struct cvmx_agl_gmx_txx_stat2_s cn63xxp1; 2243 struct cvmx_agl_gmx_txx_stat2_s cn66xx; 2244 struct cvmx_agl_gmx_txx_stat2_s cn68xx; 2245 struct cvmx_agl_gmx_txx_stat2_s cn68xxp1; 2246 struct cvmx_agl_gmx_txx_stat2_s cn70xx; 2247 struct cvmx_agl_gmx_txx_stat2_s cn70xxp1; 2248 }; 2249 2250 typedef union cvmx_agl_gmx_txx_stat2 cvmx_agl_gmx_txx_stat2_t; 2251 2252 /** 2253 * cvmx_agl_gmx_tx#_stat3 2254 * 2255 * AGL_GMX_TX_STAT3 = AGL_GMX_TX_STATS_PKTS 2256 * 2257 * 2258 * Notes: 2259 * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set 2260 * - Counters will wrap 2261 * - Not reset when MIX*_CTL[RESET] is set to 1. 2262 */ 2263 union cvmx_agl_gmx_txx_stat3 { 2264 u64 u64; 2265 struct cvmx_agl_gmx_txx_stat3_s { 2266 u64 reserved_32_63 : 32; 2267 u64 pkts : 32; 2268 } s; 2269 struct cvmx_agl_gmx_txx_stat3_s cn52xx; 2270 struct cvmx_agl_gmx_txx_stat3_s cn52xxp1; 2271 struct cvmx_agl_gmx_txx_stat3_s cn56xx; 2272 struct cvmx_agl_gmx_txx_stat3_s cn56xxp1; 2273 struct cvmx_agl_gmx_txx_stat3_s cn61xx; 2274 struct cvmx_agl_gmx_txx_stat3_s cn63xx; 2275 struct cvmx_agl_gmx_txx_stat3_s cn63xxp1; 2276 struct cvmx_agl_gmx_txx_stat3_s cn66xx; 2277 struct cvmx_agl_gmx_txx_stat3_s cn68xx; 2278 struct cvmx_agl_gmx_txx_stat3_s cn68xxp1; 2279 struct cvmx_agl_gmx_txx_stat3_s cn70xx; 2280 struct cvmx_agl_gmx_txx_stat3_s cn70xxp1; 2281 }; 2282 2283 typedef union cvmx_agl_gmx_txx_stat3 cvmx_agl_gmx_txx_stat3_t; 2284 2285 /** 2286 * cvmx_agl_gmx_tx#_stat4 2287 * 2288 * AGL_GMX_TX_STAT4 = AGL_GMX_TX_STATS_HIST1 (64) / AGL_GMX_TX_STATS_HIST0 (<64) 2289 * 2290 * 2291 * Notes: 2292 * - Packet length is the sum of all data transmitted on the wire for the given 2293 * packet including packet data, pad bytes, fcs bytes, pause bytes, and jam 2294 * bytes. The octect counts do not include PREAMBLE byte or EXTEND cycles. 2295 * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set 2296 * - Counters will wrap 2297 * - Not reset when MIX*_CTL[RESET] is set to 1. 2298 */ 2299 union cvmx_agl_gmx_txx_stat4 { 2300 u64 u64; 2301 struct cvmx_agl_gmx_txx_stat4_s { 2302 u64 hist1 : 32; 2303 u64 hist0 : 32; 2304 } s; 2305 struct cvmx_agl_gmx_txx_stat4_s cn52xx; 2306 struct cvmx_agl_gmx_txx_stat4_s cn52xxp1; 2307 struct cvmx_agl_gmx_txx_stat4_s cn56xx; 2308 struct cvmx_agl_gmx_txx_stat4_s cn56xxp1; 2309 struct cvmx_agl_gmx_txx_stat4_s cn61xx; 2310 struct cvmx_agl_gmx_txx_stat4_s cn63xx; 2311 struct cvmx_agl_gmx_txx_stat4_s cn63xxp1; 2312 struct cvmx_agl_gmx_txx_stat4_s cn66xx; 2313 struct cvmx_agl_gmx_txx_stat4_s cn68xx; 2314 struct cvmx_agl_gmx_txx_stat4_s cn68xxp1; 2315 struct cvmx_agl_gmx_txx_stat4_s cn70xx; 2316 struct cvmx_agl_gmx_txx_stat4_s cn70xxp1; 2317 }; 2318 2319 typedef union cvmx_agl_gmx_txx_stat4 cvmx_agl_gmx_txx_stat4_t; 2320 2321 /** 2322 * cvmx_agl_gmx_tx#_stat5 2323 * 2324 * AGL_GMX_TX_STAT5 = AGL_GMX_TX_STATS_HIST3 (128- 255) / AGL_GMX_TX_STATS_HIST2 (65- 127) 2325 * 2326 * 2327 * Notes: 2328 * - Packet length is the sum of all data transmitted on the wire for the given 2329 * packet including packet data, pad bytes, fcs bytes, pause bytes, and jam 2330 * bytes. The octect counts do not include PREAMBLE byte or EXTEND cycles. 2331 * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set 2332 * - Counters will wrap 2333 * - Not reset when MIX*_CTL[RESET] is set to 1. 2334 */ 2335 union cvmx_agl_gmx_txx_stat5 { 2336 u64 u64; 2337 struct cvmx_agl_gmx_txx_stat5_s { 2338 u64 hist3 : 32; 2339 u64 hist2 : 32; 2340 } s; 2341 struct cvmx_agl_gmx_txx_stat5_s cn52xx; 2342 struct cvmx_agl_gmx_txx_stat5_s cn52xxp1; 2343 struct cvmx_agl_gmx_txx_stat5_s cn56xx; 2344 struct cvmx_agl_gmx_txx_stat5_s cn56xxp1; 2345 struct cvmx_agl_gmx_txx_stat5_s cn61xx; 2346 struct cvmx_agl_gmx_txx_stat5_s cn63xx; 2347 struct cvmx_agl_gmx_txx_stat5_s cn63xxp1; 2348 struct cvmx_agl_gmx_txx_stat5_s cn66xx; 2349 struct cvmx_agl_gmx_txx_stat5_s cn68xx; 2350 struct cvmx_agl_gmx_txx_stat5_s cn68xxp1; 2351 struct cvmx_agl_gmx_txx_stat5_s cn70xx; 2352 struct cvmx_agl_gmx_txx_stat5_s cn70xxp1; 2353 }; 2354 2355 typedef union cvmx_agl_gmx_txx_stat5 cvmx_agl_gmx_txx_stat5_t; 2356 2357 /** 2358 * cvmx_agl_gmx_tx#_stat6 2359 * 2360 * AGL_GMX_TX_STAT6 = AGL_GMX_TX_STATS_HIST5 (512-1023) / AGL_GMX_TX_STATS_HIST4 (256-511) 2361 * 2362 * 2363 * Notes: 2364 * - Packet length is the sum of all data transmitted on the wire for the given 2365 * packet including packet data, pad bytes, fcs bytes, pause bytes, and jam 2366 * bytes. The octect counts do not include PREAMBLE byte or EXTEND cycles. 2367 * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set 2368 * - Counters will wrap 2369 * - Not reset when MIX*_CTL[RESET] is set to 1. 2370 */ 2371 union cvmx_agl_gmx_txx_stat6 { 2372 u64 u64; 2373 struct cvmx_agl_gmx_txx_stat6_s { 2374 u64 hist5 : 32; 2375 u64 hist4 : 32; 2376 } s; 2377 struct cvmx_agl_gmx_txx_stat6_s cn52xx; 2378 struct cvmx_agl_gmx_txx_stat6_s cn52xxp1; 2379 struct cvmx_agl_gmx_txx_stat6_s cn56xx; 2380 struct cvmx_agl_gmx_txx_stat6_s cn56xxp1; 2381 struct cvmx_agl_gmx_txx_stat6_s cn61xx; 2382 struct cvmx_agl_gmx_txx_stat6_s cn63xx; 2383 struct cvmx_agl_gmx_txx_stat6_s cn63xxp1; 2384 struct cvmx_agl_gmx_txx_stat6_s cn66xx; 2385 struct cvmx_agl_gmx_txx_stat6_s cn68xx; 2386 struct cvmx_agl_gmx_txx_stat6_s cn68xxp1; 2387 struct cvmx_agl_gmx_txx_stat6_s cn70xx; 2388 struct cvmx_agl_gmx_txx_stat6_s cn70xxp1; 2389 }; 2390 2391 typedef union cvmx_agl_gmx_txx_stat6 cvmx_agl_gmx_txx_stat6_t; 2392 2393 /** 2394 * cvmx_agl_gmx_tx#_stat7 2395 * 2396 * AGL_GMX_TX_STAT7 = AGL_GMX_TX_STATS_HIST7 (1024-1518) / AGL_GMX_TX_STATS_HIST6 (>1518) 2397 * 2398 * 2399 * Notes: 2400 * - Packet length is the sum of all data transmitted on the wire for the given 2401 * packet including packet data, pad bytes, fcs bytes, pause bytes, and jam 2402 * bytes. The octect counts do not include PREAMBLE byte or EXTEND cycles. 2403 * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set 2404 * - Counters will wrap 2405 * - Not reset when MIX*_CTL[RESET] is set to 1. 2406 */ 2407 union cvmx_agl_gmx_txx_stat7 { 2408 u64 u64; 2409 struct cvmx_agl_gmx_txx_stat7_s { 2410 u64 hist7 : 32; 2411 u64 hist6 : 32; 2412 } s; 2413 struct cvmx_agl_gmx_txx_stat7_s cn52xx; 2414 struct cvmx_agl_gmx_txx_stat7_s cn52xxp1; 2415 struct cvmx_agl_gmx_txx_stat7_s cn56xx; 2416 struct cvmx_agl_gmx_txx_stat7_s cn56xxp1; 2417 struct cvmx_agl_gmx_txx_stat7_s cn61xx; 2418 struct cvmx_agl_gmx_txx_stat7_s cn63xx; 2419 struct cvmx_agl_gmx_txx_stat7_s cn63xxp1; 2420 struct cvmx_agl_gmx_txx_stat7_s cn66xx; 2421 struct cvmx_agl_gmx_txx_stat7_s cn68xx; 2422 struct cvmx_agl_gmx_txx_stat7_s cn68xxp1; 2423 struct cvmx_agl_gmx_txx_stat7_s cn70xx; 2424 struct cvmx_agl_gmx_txx_stat7_s cn70xxp1; 2425 }; 2426 2427 typedef union cvmx_agl_gmx_txx_stat7 cvmx_agl_gmx_txx_stat7_t; 2428 2429 /** 2430 * cvmx_agl_gmx_tx#_stat8 2431 * 2432 * AGL_GMX_TX_STAT8 = AGL_GMX_TX_STATS_MCST / AGL_GMX_TX_STATS_BCST 2433 * 2434 * 2435 * Notes: 2436 * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set 2437 * - Counters will wrap 2438 * - Note, GMX determines if the packet is MCST or BCST from the DMAC of the 2439 * packet. GMX assumes that the DMAC lies in the first 6 bytes of the packet 2440 * as per the 802.3 frame definition. If the system requires additional data 2441 * before the L2 header, then the MCST and BCST counters may not reflect 2442 * reality and should be ignored by software. 2443 * - Not reset when MIX*_CTL[RESET] is set to 1. 2444 */ 2445 union cvmx_agl_gmx_txx_stat8 { 2446 u64 u64; 2447 struct cvmx_agl_gmx_txx_stat8_s { 2448 u64 mcst : 32; 2449 u64 bcst : 32; 2450 } s; 2451 struct cvmx_agl_gmx_txx_stat8_s cn52xx; 2452 struct cvmx_agl_gmx_txx_stat8_s cn52xxp1; 2453 struct cvmx_agl_gmx_txx_stat8_s cn56xx; 2454 struct cvmx_agl_gmx_txx_stat8_s cn56xxp1; 2455 struct cvmx_agl_gmx_txx_stat8_s cn61xx; 2456 struct cvmx_agl_gmx_txx_stat8_s cn63xx; 2457 struct cvmx_agl_gmx_txx_stat8_s cn63xxp1; 2458 struct cvmx_agl_gmx_txx_stat8_s cn66xx; 2459 struct cvmx_agl_gmx_txx_stat8_s cn68xx; 2460 struct cvmx_agl_gmx_txx_stat8_s cn68xxp1; 2461 struct cvmx_agl_gmx_txx_stat8_s cn70xx; 2462 struct cvmx_agl_gmx_txx_stat8_s cn70xxp1; 2463 }; 2464 2465 typedef union cvmx_agl_gmx_txx_stat8 cvmx_agl_gmx_txx_stat8_t; 2466 2467 /** 2468 * cvmx_agl_gmx_tx#_stat9 2469 * 2470 * AGL_GMX_TX_STAT9 = AGL_GMX_TX_STATS_UNDFLW / AGL_GMX_TX_STATS_CTL 2471 * 2472 * 2473 * Notes: 2474 * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set 2475 * - Counters will wrap 2476 * - Not reset when MIX*_CTL[RESET] is set to 1. 2477 */ 2478 union cvmx_agl_gmx_txx_stat9 { 2479 u64 u64; 2480 struct cvmx_agl_gmx_txx_stat9_s { 2481 u64 undflw : 32; 2482 u64 ctl : 32; 2483 } s; 2484 struct cvmx_agl_gmx_txx_stat9_s cn52xx; 2485 struct cvmx_agl_gmx_txx_stat9_s cn52xxp1; 2486 struct cvmx_agl_gmx_txx_stat9_s cn56xx; 2487 struct cvmx_agl_gmx_txx_stat9_s cn56xxp1; 2488 struct cvmx_agl_gmx_txx_stat9_s cn61xx; 2489 struct cvmx_agl_gmx_txx_stat9_s cn63xx; 2490 struct cvmx_agl_gmx_txx_stat9_s cn63xxp1; 2491 struct cvmx_agl_gmx_txx_stat9_s cn66xx; 2492 struct cvmx_agl_gmx_txx_stat9_s cn68xx; 2493 struct cvmx_agl_gmx_txx_stat9_s cn68xxp1; 2494 struct cvmx_agl_gmx_txx_stat9_s cn70xx; 2495 struct cvmx_agl_gmx_txx_stat9_s cn70xxp1; 2496 }; 2497 2498 typedef union cvmx_agl_gmx_txx_stat9 cvmx_agl_gmx_txx_stat9_t; 2499 2500 /** 2501 * cvmx_agl_gmx_tx#_stats_ctl 2502 * 2503 * AGL_GMX_TX_STATS_CTL = TX Stats Control register 2504 * 2505 * 2506 * Notes: 2507 * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 2508 * 2509 */ 2510 union cvmx_agl_gmx_txx_stats_ctl { 2511 u64 u64; 2512 struct cvmx_agl_gmx_txx_stats_ctl_s { 2513 u64 reserved_1_63 : 63; 2514 u64 rd_clr : 1; 2515 } s; 2516 struct cvmx_agl_gmx_txx_stats_ctl_s cn52xx; 2517 struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1; 2518 struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx; 2519 struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1; 2520 struct cvmx_agl_gmx_txx_stats_ctl_s cn61xx; 2521 struct cvmx_agl_gmx_txx_stats_ctl_s cn63xx; 2522 struct cvmx_agl_gmx_txx_stats_ctl_s cn63xxp1; 2523 struct cvmx_agl_gmx_txx_stats_ctl_s cn66xx; 2524 struct cvmx_agl_gmx_txx_stats_ctl_s cn68xx; 2525 struct cvmx_agl_gmx_txx_stats_ctl_s cn68xxp1; 2526 struct cvmx_agl_gmx_txx_stats_ctl_s cn70xx; 2527 struct cvmx_agl_gmx_txx_stats_ctl_s cn70xxp1; 2528 }; 2529 2530 typedef union cvmx_agl_gmx_txx_stats_ctl cvmx_agl_gmx_txx_stats_ctl_t; 2531 2532 /** 2533 * cvmx_agl_gmx_tx#_thresh 2534 * 2535 * AGL_GMX_TX_THRESH = Packet TX Threshold 2536 * 2537 * 2538 * Notes: 2539 * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 2540 * 2541 */ 2542 union cvmx_agl_gmx_txx_thresh { 2543 u64 u64; 2544 struct cvmx_agl_gmx_txx_thresh_s { 2545 u64 reserved_6_63 : 58; 2546 u64 cnt : 6; 2547 } s; 2548 struct cvmx_agl_gmx_txx_thresh_s cn52xx; 2549 struct cvmx_agl_gmx_txx_thresh_s cn52xxp1; 2550 struct cvmx_agl_gmx_txx_thresh_s cn56xx; 2551 struct cvmx_agl_gmx_txx_thresh_s cn56xxp1; 2552 struct cvmx_agl_gmx_txx_thresh_s cn61xx; 2553 struct cvmx_agl_gmx_txx_thresh_s cn63xx; 2554 struct cvmx_agl_gmx_txx_thresh_s cn63xxp1; 2555 struct cvmx_agl_gmx_txx_thresh_s cn66xx; 2556 struct cvmx_agl_gmx_txx_thresh_s cn68xx; 2557 struct cvmx_agl_gmx_txx_thresh_s cn68xxp1; 2558 struct cvmx_agl_gmx_txx_thresh_s cn70xx; 2559 struct cvmx_agl_gmx_txx_thresh_s cn70xxp1; 2560 }; 2561 2562 typedef union cvmx_agl_gmx_txx_thresh cvmx_agl_gmx_txx_thresh_t; 2563 2564 /** 2565 * cvmx_agl_gmx_tx_bp 2566 * 2567 * AGL_GMX_TX_BP = Packet TX BackPressure Register 2568 * 2569 * 2570 * Notes: 2571 * BP[0] will be reset when MIX0_CTL[RESET] is set to 1. 2572 * BP[1] will be reset when MIX1_CTL[RESET] is set to 1. 2573 */ 2574 union cvmx_agl_gmx_tx_bp { 2575 u64 u64; 2576 struct cvmx_agl_gmx_tx_bp_s { 2577 u64 reserved_2_63 : 62; 2578 u64 bp : 2; 2579 } s; 2580 struct cvmx_agl_gmx_tx_bp_s cn52xx; 2581 struct cvmx_agl_gmx_tx_bp_s cn52xxp1; 2582 struct cvmx_agl_gmx_tx_bp_cn56xx { 2583 u64 reserved_1_63 : 63; 2584 u64 bp : 1; 2585 } cn56xx; 2586 struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1; 2587 struct cvmx_agl_gmx_tx_bp_s cn61xx; 2588 struct cvmx_agl_gmx_tx_bp_s cn63xx; 2589 struct cvmx_agl_gmx_tx_bp_s cn63xxp1; 2590 struct cvmx_agl_gmx_tx_bp_s cn66xx; 2591 struct cvmx_agl_gmx_tx_bp_s cn68xx; 2592 struct cvmx_agl_gmx_tx_bp_s cn68xxp1; 2593 struct cvmx_agl_gmx_tx_bp_cn56xx cn70xx; 2594 struct cvmx_agl_gmx_tx_bp_cn56xx cn70xxp1; 2595 }; 2596 2597 typedef union cvmx_agl_gmx_tx_bp cvmx_agl_gmx_tx_bp_t; 2598 2599 /** 2600 * cvmx_agl_gmx_tx_col_attempt 2601 * 2602 * AGL_GMX_TX_COL_ATTEMPT = Packet TX collision attempts before dropping frame 2603 * 2604 * 2605 * Notes: 2606 * Additionally reset when both MIX0/1_CTL[RESET] are set to 1. 2607 * 2608 */ 2609 union cvmx_agl_gmx_tx_col_attempt { 2610 u64 u64; 2611 struct cvmx_agl_gmx_tx_col_attempt_s { 2612 u64 reserved_5_63 : 59; 2613 u64 limit : 5; 2614 } s; 2615 struct cvmx_agl_gmx_tx_col_attempt_s cn52xx; 2616 struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1; 2617 struct cvmx_agl_gmx_tx_col_attempt_s cn56xx; 2618 struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1; 2619 struct cvmx_agl_gmx_tx_col_attempt_s cn61xx; 2620 struct cvmx_agl_gmx_tx_col_attempt_s cn63xx; 2621 struct cvmx_agl_gmx_tx_col_attempt_s cn63xxp1; 2622 struct cvmx_agl_gmx_tx_col_attempt_s cn66xx; 2623 struct cvmx_agl_gmx_tx_col_attempt_s cn68xx; 2624 struct cvmx_agl_gmx_tx_col_attempt_s cn68xxp1; 2625 struct cvmx_agl_gmx_tx_col_attempt_s cn70xx; 2626 struct cvmx_agl_gmx_tx_col_attempt_s cn70xxp1; 2627 }; 2628 2629 typedef union cvmx_agl_gmx_tx_col_attempt cvmx_agl_gmx_tx_col_attempt_t; 2630 2631 /** 2632 * cvmx_agl_gmx_tx_ifg 2633 * 2634 * Common 2635 * AGL_GMX_TX_IFG = Packet TX Interframe Gap 2636 */ 2637 union cvmx_agl_gmx_tx_ifg { 2638 u64 u64; 2639 struct cvmx_agl_gmx_tx_ifg_s { 2640 u64 reserved_8_63 : 56; 2641 u64 ifg2 : 4; 2642 u64 ifg1 : 4; 2643 } s; 2644 struct cvmx_agl_gmx_tx_ifg_s cn52xx; 2645 struct cvmx_agl_gmx_tx_ifg_s cn52xxp1; 2646 struct cvmx_agl_gmx_tx_ifg_s cn56xx; 2647 struct cvmx_agl_gmx_tx_ifg_s cn56xxp1; 2648 struct cvmx_agl_gmx_tx_ifg_s cn61xx; 2649 struct cvmx_agl_gmx_tx_ifg_s cn63xx; 2650 struct cvmx_agl_gmx_tx_ifg_s cn63xxp1; 2651 struct cvmx_agl_gmx_tx_ifg_s cn66xx; 2652 struct cvmx_agl_gmx_tx_ifg_s cn68xx; 2653 struct cvmx_agl_gmx_tx_ifg_s cn68xxp1; 2654 struct cvmx_agl_gmx_tx_ifg_s cn70xx; 2655 struct cvmx_agl_gmx_tx_ifg_s cn70xxp1; 2656 }; 2657 2658 typedef union cvmx_agl_gmx_tx_ifg cvmx_agl_gmx_tx_ifg_t; 2659 2660 /** 2661 * cvmx_agl_gmx_tx_int_en 2662 * 2663 * AGL_GMX_TX_INT_EN = Interrupt Enable 2664 * 2665 * 2666 * Notes: 2667 * UNDFLW[0], XSCOL[0], XSDEF[0], LATE_COL[0], PTP_LOST[0] will be reset when MIX0_CTL[RESET] is set to 1. 2668 * UNDFLW[1], XSCOL[1], XSDEF[1], LATE_COL[1], PTP_LOST[1] will be reset when MIX1_CTL[RESET] is set to 1. 2669 * PKO_NXA will bee reset when both MIX0/1_CTL[RESET] are set to 1. 2670 */ 2671 union cvmx_agl_gmx_tx_int_en { 2672 u64 u64; 2673 struct cvmx_agl_gmx_tx_int_en_s { 2674 u64 reserved_22_63 : 42; 2675 u64 ptp_lost : 2; 2676 u64 reserved_18_19 : 2; 2677 u64 late_col : 2; 2678 u64 reserved_14_15 : 2; 2679 u64 xsdef : 2; 2680 u64 reserved_10_11 : 2; 2681 u64 xscol : 2; 2682 u64 reserved_4_7 : 4; 2683 u64 undflw : 2; 2684 u64 reserved_1_1 : 1; 2685 u64 pko_nxa : 1; 2686 } s; 2687 struct cvmx_agl_gmx_tx_int_en_cn52xx { 2688 u64 reserved_18_63 : 46; 2689 u64 late_col : 2; 2690 u64 reserved_14_15 : 2; 2691 u64 xsdef : 2; 2692 u64 reserved_10_11 : 2; 2693 u64 xscol : 2; 2694 u64 reserved_4_7 : 4; 2695 u64 undflw : 2; 2696 u64 reserved_1_1 : 1; 2697 u64 pko_nxa : 1; 2698 } cn52xx; 2699 struct cvmx_agl_gmx_tx_int_en_cn52xx cn52xxp1; 2700 struct cvmx_agl_gmx_tx_int_en_cn56xx { 2701 u64 reserved_17_63 : 47; 2702 u64 late_col : 1; 2703 u64 reserved_13_15 : 3; 2704 u64 xsdef : 1; 2705 u64 reserved_9_11 : 3; 2706 u64 xscol : 1; 2707 u64 reserved_3_7 : 5; 2708 u64 undflw : 1; 2709 u64 reserved_1_1 : 1; 2710 u64 pko_nxa : 1; 2711 } cn56xx; 2712 struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1; 2713 struct cvmx_agl_gmx_tx_int_en_s cn61xx; 2714 struct cvmx_agl_gmx_tx_int_en_s cn63xx; 2715 struct cvmx_agl_gmx_tx_int_en_s cn63xxp1; 2716 struct cvmx_agl_gmx_tx_int_en_s cn66xx; 2717 struct cvmx_agl_gmx_tx_int_en_s cn68xx; 2718 struct cvmx_agl_gmx_tx_int_en_s cn68xxp1; 2719 struct cvmx_agl_gmx_tx_int_en_cn70xx { 2720 u64 reserved_21_63 : 43; 2721 u64 ptp_lost : 1; 2722 u64 reserved_17_19 : 3; 2723 u64 late_col : 1; 2724 u64 reserved_13_15 : 3; 2725 u64 xsdef : 1; 2726 u64 reserved_9_11 : 3; 2727 u64 xscol : 1; 2728 u64 reserved_3_7 : 5; 2729 u64 undflw : 1; 2730 u64 reserved_1_1 : 1; 2731 u64 pko_nxa : 1; 2732 } cn70xx; 2733 struct cvmx_agl_gmx_tx_int_en_cn70xx cn70xxp1; 2734 }; 2735 2736 typedef union cvmx_agl_gmx_tx_int_en cvmx_agl_gmx_tx_int_en_t; 2737 2738 /** 2739 * cvmx_agl_gmx_tx_int_reg 2740 * 2741 * AGL_GMX_TX_INT_REG = Interrupt Register 2742 * 2743 * 2744 * Notes: 2745 * UNDFLW[0], XSCOL[0], XSDEF[0], LATE_COL[0], PTP_LOST[0] will be reset when MIX0_CTL[RESET] is set to 1. 2746 * UNDFLW[1], XSCOL[1], XSDEF[1], LATE_COL[1], PTP_LOST[1] will be reset when MIX1_CTL[RESET] is set to 1. 2747 * PKO_NXA will bee reset when both MIX0/1_CTL[RESET] are set to 1. 2748 */ 2749 union cvmx_agl_gmx_tx_int_reg { 2750 u64 u64; 2751 struct cvmx_agl_gmx_tx_int_reg_s { 2752 u64 reserved_22_63 : 42; 2753 u64 ptp_lost : 2; 2754 u64 reserved_18_19 : 2; 2755 u64 late_col : 2; 2756 u64 reserved_14_15 : 2; 2757 u64 xsdef : 2; 2758 u64 reserved_10_11 : 2; 2759 u64 xscol : 2; 2760 u64 reserved_4_7 : 4; 2761 u64 undflw : 2; 2762 u64 reserved_1_1 : 1; 2763 u64 pko_nxa : 1; 2764 } s; 2765 struct cvmx_agl_gmx_tx_int_reg_cn52xx { 2766 u64 reserved_18_63 : 46; 2767 u64 late_col : 2; 2768 u64 reserved_14_15 : 2; 2769 u64 xsdef : 2; 2770 u64 reserved_10_11 : 2; 2771 u64 xscol : 2; 2772 u64 reserved_4_7 : 4; 2773 u64 undflw : 2; 2774 u64 reserved_1_1 : 1; 2775 u64 pko_nxa : 1; 2776 } cn52xx; 2777 struct cvmx_agl_gmx_tx_int_reg_cn52xx cn52xxp1; 2778 struct cvmx_agl_gmx_tx_int_reg_cn56xx { 2779 u64 reserved_17_63 : 47; 2780 u64 late_col : 1; 2781 u64 reserved_13_15 : 3; 2782 u64 xsdef : 1; 2783 u64 reserved_9_11 : 3; 2784 u64 xscol : 1; 2785 u64 reserved_3_7 : 5; 2786 u64 undflw : 1; 2787 u64 reserved_1_1 : 1; 2788 u64 pko_nxa : 1; 2789 } cn56xx; 2790 struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1; 2791 struct cvmx_agl_gmx_tx_int_reg_s cn61xx; 2792 struct cvmx_agl_gmx_tx_int_reg_s cn63xx; 2793 struct cvmx_agl_gmx_tx_int_reg_s cn63xxp1; 2794 struct cvmx_agl_gmx_tx_int_reg_s cn66xx; 2795 struct cvmx_agl_gmx_tx_int_reg_s cn68xx; 2796 struct cvmx_agl_gmx_tx_int_reg_s cn68xxp1; 2797 struct cvmx_agl_gmx_tx_int_reg_cn70xx { 2798 u64 reserved_21_63 : 43; 2799 u64 ptp_lost : 1; 2800 u64 reserved_17_19 : 3; 2801 u64 late_col : 1; 2802 u64 reserved_13_15 : 3; 2803 u64 xsdef : 1; 2804 u64 reserved_9_11 : 3; 2805 u64 xscol : 1; 2806 u64 reserved_3_7 : 5; 2807 u64 undflw : 1; 2808 u64 reserved_1_1 : 1; 2809 u64 pko_nxa : 1; 2810 } cn70xx; 2811 struct cvmx_agl_gmx_tx_int_reg_cn70xx cn70xxp1; 2812 }; 2813 2814 typedef union cvmx_agl_gmx_tx_int_reg cvmx_agl_gmx_tx_int_reg_t; 2815 2816 /** 2817 * cvmx_agl_gmx_tx_jam 2818 * 2819 * AGL_GMX_TX_JAM = Packet TX Jam Pattern 2820 * 2821 * 2822 * Notes: 2823 * Additionally reset when both MIX0/1_CTL[RESET] are set to 1. 2824 * 2825 */ 2826 union cvmx_agl_gmx_tx_jam { 2827 u64 u64; 2828 struct cvmx_agl_gmx_tx_jam_s { 2829 u64 reserved_8_63 : 56; 2830 u64 jam : 8; 2831 } s; 2832 struct cvmx_agl_gmx_tx_jam_s cn52xx; 2833 struct cvmx_agl_gmx_tx_jam_s cn52xxp1; 2834 struct cvmx_agl_gmx_tx_jam_s cn56xx; 2835 struct cvmx_agl_gmx_tx_jam_s cn56xxp1; 2836 struct cvmx_agl_gmx_tx_jam_s cn61xx; 2837 struct cvmx_agl_gmx_tx_jam_s cn63xx; 2838 struct cvmx_agl_gmx_tx_jam_s cn63xxp1; 2839 struct cvmx_agl_gmx_tx_jam_s cn66xx; 2840 struct cvmx_agl_gmx_tx_jam_s cn68xx; 2841 struct cvmx_agl_gmx_tx_jam_s cn68xxp1; 2842 struct cvmx_agl_gmx_tx_jam_s cn70xx; 2843 struct cvmx_agl_gmx_tx_jam_s cn70xxp1; 2844 }; 2845 2846 typedef union cvmx_agl_gmx_tx_jam cvmx_agl_gmx_tx_jam_t; 2847 2848 /** 2849 * cvmx_agl_gmx_tx_lfsr 2850 * 2851 * AGL_GMX_TX_LFSR = LFSR used to implement truncated binary exponential backoff 2852 * 2853 * 2854 * Notes: 2855 * Additionally reset when both MIX0/1_CTL[RESET] are set to 1. 2856 * 2857 */ 2858 union cvmx_agl_gmx_tx_lfsr { 2859 u64 u64; 2860 struct cvmx_agl_gmx_tx_lfsr_s { 2861 u64 reserved_16_63 : 48; 2862 u64 lfsr : 16; 2863 } s; 2864 struct cvmx_agl_gmx_tx_lfsr_s cn52xx; 2865 struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1; 2866 struct cvmx_agl_gmx_tx_lfsr_s cn56xx; 2867 struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1; 2868 struct cvmx_agl_gmx_tx_lfsr_s cn61xx; 2869 struct cvmx_agl_gmx_tx_lfsr_s cn63xx; 2870 struct cvmx_agl_gmx_tx_lfsr_s cn63xxp1; 2871 struct cvmx_agl_gmx_tx_lfsr_s cn66xx; 2872 struct cvmx_agl_gmx_tx_lfsr_s cn68xx; 2873 struct cvmx_agl_gmx_tx_lfsr_s cn68xxp1; 2874 struct cvmx_agl_gmx_tx_lfsr_s cn70xx; 2875 struct cvmx_agl_gmx_tx_lfsr_s cn70xxp1; 2876 }; 2877 2878 typedef union cvmx_agl_gmx_tx_lfsr cvmx_agl_gmx_tx_lfsr_t; 2879 2880 /** 2881 * cvmx_agl_gmx_tx_ovr_bp 2882 * 2883 * AGL_GMX_TX_OVR_BP = Packet TX Override BackPressure 2884 * 2885 * 2886 * Notes: 2887 * IGN_FULL[0], BP[0], EN[0] will be reset when MIX0_CTL[RESET] is set to 1. 2888 * IGN_FULL[1], BP[1], EN[1] will be reset when MIX1_CTL[RESET] is set to 1. 2889 */ 2890 union cvmx_agl_gmx_tx_ovr_bp { 2891 u64 u64; 2892 struct cvmx_agl_gmx_tx_ovr_bp_s { 2893 u64 reserved_10_63 : 54; 2894 u64 en : 2; 2895 u64 reserved_6_7 : 2; 2896 u64 bp : 2; 2897 u64 reserved_2_3 : 2; 2898 u64 ign_full : 2; 2899 } s; 2900 struct cvmx_agl_gmx_tx_ovr_bp_s cn52xx; 2901 struct cvmx_agl_gmx_tx_ovr_bp_s cn52xxp1; 2902 struct cvmx_agl_gmx_tx_ovr_bp_cn56xx { 2903 u64 reserved_9_63 : 55; 2904 u64 en : 1; 2905 u64 reserved_5_7 : 3; 2906 u64 bp : 1; 2907 u64 reserved_1_3 : 3; 2908 u64 ign_full : 1; 2909 } cn56xx; 2910 struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1; 2911 struct cvmx_agl_gmx_tx_ovr_bp_s cn61xx; 2912 struct cvmx_agl_gmx_tx_ovr_bp_s cn63xx; 2913 struct cvmx_agl_gmx_tx_ovr_bp_s cn63xxp1; 2914 struct cvmx_agl_gmx_tx_ovr_bp_s cn66xx; 2915 struct cvmx_agl_gmx_tx_ovr_bp_s cn68xx; 2916 struct cvmx_agl_gmx_tx_ovr_bp_s cn68xxp1; 2917 struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn70xx; 2918 struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn70xxp1; 2919 }; 2920 2921 typedef union cvmx_agl_gmx_tx_ovr_bp cvmx_agl_gmx_tx_ovr_bp_t; 2922 2923 /** 2924 * cvmx_agl_gmx_tx_pause_pkt_dmac 2925 * 2926 * AGL_GMX_TX_PAUSE_PKT_DMAC = Packet TX Pause Packet DMAC field 2927 * 2928 * 2929 * Notes: 2930 * Additionally reset when both MIX0/1_CTL[RESET] are set to 1. 2931 * 2932 */ 2933 union cvmx_agl_gmx_tx_pause_pkt_dmac { 2934 u64 u64; 2935 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s { 2936 u64 reserved_48_63 : 16; 2937 u64 dmac : 48; 2938 } s; 2939 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xx; 2940 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1; 2941 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx; 2942 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1; 2943 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn61xx; 2944 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xx; 2945 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xxp1; 2946 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn66xx; 2947 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn68xx; 2948 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn68xxp1; 2949 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn70xx; 2950 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn70xxp1; 2951 }; 2952 2953 typedef union cvmx_agl_gmx_tx_pause_pkt_dmac cvmx_agl_gmx_tx_pause_pkt_dmac_t; 2954 2955 /** 2956 * cvmx_agl_gmx_tx_pause_pkt_type 2957 * 2958 * AGL_GMX_TX_PAUSE_PKT_TYPE = Packet TX Pause Packet TYPE field 2959 * 2960 * 2961 * Notes: 2962 * Additionally reset when both MIX0/1_CTL[RESET] are set to 1. 2963 * 2964 */ 2965 union cvmx_agl_gmx_tx_pause_pkt_type { 2966 u64 u64; 2967 struct cvmx_agl_gmx_tx_pause_pkt_type_s { 2968 u64 reserved_16_63 : 48; 2969 u64 type : 16; 2970 } s; 2971 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xx; 2972 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1; 2973 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx; 2974 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1; 2975 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn61xx; 2976 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xx; 2977 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xxp1; 2978 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn66xx; 2979 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn68xx; 2980 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn68xxp1; 2981 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn70xx; 2982 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn70xxp1; 2983 }; 2984 2985 typedef union cvmx_agl_gmx_tx_pause_pkt_type cvmx_agl_gmx_tx_pause_pkt_type_t; 2986 2987 /** 2988 * cvmx_agl_gmx_wol_ctl 2989 */ 2990 union cvmx_agl_gmx_wol_ctl { 2991 u64 u64; 2992 struct cvmx_agl_gmx_wol_ctl_s { 2993 u64 reserved_33_63 : 31; 2994 u64 magic_en : 1; 2995 u64 reserved_17_31 : 15; 2996 u64 direct_en : 1; 2997 u64 reserved_1_15 : 15; 2998 u64 en : 1; 2999 } s; 3000 struct cvmx_agl_gmx_wol_ctl_s cn70xx; 3001 struct cvmx_agl_gmx_wol_ctl_s cn70xxp1; 3002 }; 3003 3004 typedef union cvmx_agl_gmx_wol_ctl cvmx_agl_gmx_wol_ctl_t; 3005 3006 /** 3007 * cvmx_agl_prt#_ctl 3008 * 3009 * AGL_PRT_CTL = AGL Port Control 3010 * 3011 * 3012 * Notes: 3013 * The RGMII timing specification requires that devices transmit clock and 3014 * data synchronously. The specification requires external sources (namely 3015 * the PC board trace routes) to introduce the appropriate 1.5 to 2.0 ns of 3016 * delay. 3017 * 3018 * To eliminate the need for the PC board delays, the MIX RGMII interface 3019 * has optional onboard DLL's for both transmit and receive. For correct 3020 * operation, at most one of the transmitter, board, or receiver involved 3021 * in an RGMII link should introduce delay. By default/reset, 3022 * the MIX RGMII receivers delay the received clock, and the MIX 3023 * RGMII transmitters do not delay the transmitted clock. Whether this 3024 * default works as-is with a given link partner depends on the behavior 3025 * of the link partner and the PC board. 3026 * 3027 * These are the possible modes of MIX RGMII receive operation: 3028 * o AGL_PRTx_CTL[CLKRX_BYP] = 0 (reset value) - The OCTEON MIX RGMII 3029 * receive interface introduces clock delay using its internal DLL. 3030 * This mode is appropriate if neither the remote 3031 * transmitter nor the PC board delays the clock. 3032 * o AGL_PRTx_CTL[CLKRX_BYP] = 1, [CLKRX_SET] = 0x0 - The OCTEON MIX 3033 * RGMII receive interface introduces no clock delay. This mode 3034 * is appropriate if either the remote transmitter or the PC board 3035 * delays the clock. 3036 * 3037 * These are the possible modes of MIX RGMII transmit operation: 3038 * o AGL_PRTx_CTL[CLKTX_BYP] = 1, [CLKTX_SET] = 0x0 (reset value) - 3039 * The OCTEON MIX RGMII transmit interface introduces no clock 3040 * delay. This mode is appropriate is either the remote receiver 3041 * or the PC board delays the clock. 3042 * o AGL_PRTx_CTL[CLKTX_BYP] = 0 - The OCTEON MIX RGMII transmit 3043 * interface introduces clock delay using its internal DLL. 3044 * This mode is appropriate if neither the remote receiver 3045 * nor the PC board delays the clock. 3046 * 3047 * AGL_PRT0_CTL will be reset when MIX0_CTL[RESET] is set to 1. 3048 * AGL_PRT1_CTL will be reset when MIX1_CTL[RESET] is set to 1. 3049 */ 3050 union cvmx_agl_prtx_ctl { 3051 u64 u64; 3052 struct cvmx_agl_prtx_ctl_s { 3053 u64 drv_byp : 1; 3054 u64 reserved_62_62 : 1; 3055 u64 cmp_pctl : 6; 3056 u64 reserved_54_55 : 2; 3057 u64 cmp_nctl : 6; 3058 u64 reserved_46_47 : 2; 3059 u64 drv_pctl : 6; 3060 u64 reserved_38_39 : 2; 3061 u64 drv_nctl : 6; 3062 u64 reserved_31_31 : 1; 3063 u64 clk_set : 7; 3064 u64 clkrx_byp : 1; 3065 u64 clkrx_set : 7; 3066 u64 clktx_byp : 1; 3067 u64 clktx_set : 7; 3068 u64 refclk_sel : 2; 3069 u64 reserved_5_5 : 1; 3070 u64 dllrst : 1; 3071 u64 comp : 1; 3072 u64 enable : 1; 3073 u64 clkrst : 1; 3074 u64 mode : 1; 3075 } s; 3076 struct cvmx_agl_prtx_ctl_cn61xx { 3077 u64 drv_byp : 1; 3078 u64 reserved_62_62 : 1; 3079 u64 cmp_pctl : 6; 3080 u64 reserved_54_55 : 2; 3081 u64 cmp_nctl : 6; 3082 u64 reserved_46_47 : 2; 3083 u64 drv_pctl : 6; 3084 u64 reserved_38_39 : 2; 3085 u64 drv_nctl : 6; 3086 u64 reserved_29_31 : 3; 3087 u64 clk_set : 5; 3088 u64 clkrx_byp : 1; 3089 u64 reserved_21_22 : 2; 3090 u64 clkrx_set : 5; 3091 u64 clktx_byp : 1; 3092 u64 reserved_13_14 : 2; 3093 u64 clktx_set : 5; 3094 u64 reserved_5_7 : 3; 3095 u64 dllrst : 1; 3096 u64 comp : 1; 3097 u64 enable : 1; 3098 u64 clkrst : 1; 3099 u64 mode : 1; 3100 } cn61xx; 3101 struct cvmx_agl_prtx_ctl_cn61xx cn63xx; 3102 struct cvmx_agl_prtx_ctl_cn61xx cn63xxp1; 3103 struct cvmx_agl_prtx_ctl_cn61xx cn66xx; 3104 struct cvmx_agl_prtx_ctl_cn61xx cn68xx; 3105 struct cvmx_agl_prtx_ctl_cn61xx cn68xxp1; 3106 struct cvmx_agl_prtx_ctl_cn70xx { 3107 u64 drv_byp : 1; 3108 u64 reserved_61_62 : 2; 3109 u64 cmp_pctl : 5; 3110 u64 reserved_53_55 : 3; 3111 u64 cmp_nctl : 5; 3112 u64 reserved_45_47 : 3; 3113 u64 drv_pctl : 5; 3114 u64 reserved_37_39 : 3; 3115 u64 drv_nctl : 5; 3116 u64 reserved_31_31 : 1; 3117 u64 clk_set : 7; 3118 u64 clkrx_byp : 1; 3119 u64 clkrx_set : 7; 3120 u64 clktx_byp : 1; 3121 u64 clktx_set : 7; 3122 u64 refclk_sel : 2; 3123 u64 reserved_5_5 : 1; 3124 u64 dllrst : 1; 3125 u64 comp : 1; 3126 u64 enable : 1; 3127 u64 clkrst : 1; 3128 u64 mode : 1; 3129 } cn70xx; 3130 struct cvmx_agl_prtx_ctl_cn70xx cn70xxp1; 3131 }; 3132 3133 typedef union cvmx_agl_prtx_ctl cvmx_agl_prtx_ctl_t; 3134 3135 #endif 3136