1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright (C) 2018 Marvell International Ltd. 4 */ 5 6 #ifndef Q_STRUCT_H 7 #define Q_STRUCT_H 8 9 /* Load transaction types for reading segment bytes specified by 10 * NIC_SEND_GATHER_S[LD_TYPE]. 11 */ 12 enum nic_send_ld_type_e { 13 NIC_SEND_LD_TYPE_E_LDD = 0x0, 14 NIC_SEND_LD_TYPE_E_LDT = 0x1, 15 NIC_SEND_LD_TYPE_E_LDWB = 0x2, 16 NIC_SEND_LD_TYPE_E_ENUM_LAST = 0x3, 17 }; 18 19 enum ether_type_algorithm { 20 ETYPE_ALG_NONE = 0x0, 21 ETYPE_ALG_SKIP = 0x1, 22 ETYPE_ALG_ENDPARSE = 0x2, 23 ETYPE_ALG_VLAN = 0x3, 24 ETYPE_ALG_VLAN_STRIP = 0x4, 25 }; 26 27 enum layer3_type { 28 L3TYPE_NONE = 0x00, 29 L3TYPE_GRH = 0x01, 30 L3TYPE_IPV4 = 0x04, 31 L3TYPE_IPV4_OPTIONS = 0x05, 32 L3TYPE_IPV6 = 0x06, 33 L3TYPE_IPV6_OPTIONS = 0x07, 34 L3TYPE_ET_STOP = 0x0D, 35 L3TYPE_OTHER = 0x0E, 36 }; 37 38 enum layer4_type { 39 L4TYPE_NONE = 0x00, 40 L4TYPE_IPSEC_ESP = 0x01, 41 L4TYPE_IPFRAG = 0x02, 42 L4TYPE_IPCOMP = 0x03, 43 L4TYPE_TCP = 0x04, 44 L4TYPE_UDP = 0x05, 45 L4TYPE_SCTP = 0x06, 46 L4TYPE_GRE = 0x07, 47 L4TYPE_ROCE_BTH = 0x08, 48 L4TYPE_OTHER = 0x0E, 49 }; 50 51 /* CPI and RSSI configuration */ 52 enum cpi_algorithm_type { 53 CPI_ALG_NONE = 0x0, 54 CPI_ALG_VLAN = 0x1, 55 CPI_ALG_VLAN16 = 0x2, 56 CPI_ALG_DIFF = 0x3, 57 }; 58 59 enum rss_algorithm_type { 60 RSS_ALG_NONE = 0x00, 61 RSS_ALG_PORT = 0x01, 62 RSS_ALG_IP = 0x02, 63 RSS_ALG_TCP_IP = 0x03, 64 RSS_ALG_UDP_IP = 0x04, 65 RSS_ALG_SCTP_IP = 0x05, 66 RSS_ALG_GRE_IP = 0x06, 67 RSS_ALG_ROCE = 0x07, 68 }; 69 70 enum rss_hash_cfg { 71 RSS_HASH_L2ETC = 0x00, 72 RSS_HASH_IP = 0x01, 73 RSS_HASH_TCP = 0x02, 74 RSS_TCP_SYN_DIS = 0x03, 75 RSS_HASH_UDP = 0x04, 76 RSS_HASH_L4ETC = 0x05, 77 RSS_HASH_ROCE = 0x06, 78 RSS_L3_BIDI = 0x07, 79 RSS_L4_BIDI = 0x08, 80 }; 81 82 /* Completion queue entry types */ 83 enum cqe_type { 84 CQE_TYPE_INVALID = 0x0, 85 CQE_TYPE_RX = 0x2, 86 CQE_TYPE_RX_SPLIT = 0x3, 87 CQE_TYPE_RX_TCP = 0x4, 88 CQE_TYPE_SEND = 0x8, 89 CQE_TYPE_SEND_PTP = 0x9, 90 }; 91 92 enum cqe_rx_tcp_status { 93 CQE_RX_STATUS_VALID_TCP_CNXT = 0x00, 94 CQE_RX_STATUS_INVALID_TCP_CNXT = 0x0F, 95 }; 96 97 enum cqe_send_status { 98 CQE_SEND_STATUS_GOOD = 0x00, 99 CQE_SEND_STATUS_DESC_FAULT = 0x01, 100 CQE_SEND_STATUS_HDR_CONS_ERR = 0x11, 101 CQE_SEND_STATUS_SUBDESC_ERR = 0x12, 102 CQE_SEND_STATUS_IMM_SIZE_OFLOW = 0x80, 103 CQE_SEND_STATUS_CRC_SEQ_ERR = 0x81, 104 CQE_SEND_STATUS_DATA_SEQ_ERR = 0x82, 105 CQE_SEND_STATUS_MEM_SEQ_ERR = 0x83, 106 CQE_SEND_STATUS_LOCK_VIOL = 0x84, 107 CQE_SEND_STATUS_LOCK_UFLOW = 0x85, 108 CQE_SEND_STATUS_DATA_FAULT = 0x86, 109 CQE_SEND_STATUS_TSTMP_CONFLICT = 0x87, 110 CQE_SEND_STATUS_TSTMP_TIMEOUT = 0x88, 111 CQE_SEND_STATUS_MEM_FAULT = 0x89, 112 CQE_SEND_STATUS_CSUM_OVERLAP = 0x8A, 113 CQE_SEND_STATUS_CSUM_OVERFLOW = 0x8B, 114 }; 115 116 enum cqe_rx_tcp_end_reason { 117 CQE_RX_TCP_END_FIN_FLAG_DET = 0, 118 CQE_RX_TCP_END_INVALID_FLAG = 1, 119 CQE_RX_TCP_END_TIMEOUT = 2, 120 CQE_RX_TCP_END_OUT_OF_SEQ = 3, 121 CQE_RX_TCP_END_PKT_ERR = 4, 122 CQE_RX_TCP_END_QS_DISABLED = 0x0F, 123 }; 124 125 /* Packet protocol level error enumeration */ 126 enum cqe_rx_err_level { 127 CQE_RX_ERRLVL_RE = 0x0, 128 CQE_RX_ERRLVL_L2 = 0x1, 129 CQE_RX_ERRLVL_L3 = 0x2, 130 CQE_RX_ERRLVL_L4 = 0x3, 131 }; 132 133 /* Packet protocol level error type enumeration */ 134 enum cqe_rx_err_opcode { 135 CQE_RX_ERR_RE_NONE = 0x0, 136 CQE_RX_ERR_RE_PARTIAL = 0x1, 137 CQE_RX_ERR_RE_JABBER = 0x2, 138 CQE_RX_ERR_RE_FCS = 0x7, 139 CQE_RX_ERR_RE_TERMINATE = 0x9, 140 CQE_RX_ERR_RE_RX_CTL = 0xb, 141 CQE_RX_ERR_PREL2_ERR = 0x1f, 142 CQE_RX_ERR_L2_FRAGMENT = 0x20, 143 CQE_RX_ERR_L2_OVERRUN = 0x21, 144 CQE_RX_ERR_L2_PFCS = 0x22, 145 CQE_RX_ERR_L2_PUNY = 0x23, 146 CQE_RX_ERR_L2_MAL = 0x24, 147 CQE_RX_ERR_L2_OVERSIZE = 0x25, 148 CQE_RX_ERR_L2_UNDERSIZE = 0x26, 149 CQE_RX_ERR_L2_LENMISM = 0x27, 150 CQE_RX_ERR_L2_PCLP = 0x28, 151 CQE_RX_ERR_IP_NOT = 0x41, 152 CQE_RX_ERR_IP_CHK = 0x42, 153 CQE_RX_ERR_IP_MAL = 0x43, 154 CQE_RX_ERR_IP_MALD = 0x44, 155 CQE_RX_ERR_IP_HOP = 0x45, 156 CQE_RX_ERR_L3_ICRC = 0x46, 157 CQE_RX_ERR_L3_PCLP = 0x47, 158 CQE_RX_ERR_L4_MAL = 0x61, 159 CQE_RX_ERR_L4_CHK = 0x62, 160 CQE_RX_ERR_UDP_LEN = 0x63, 161 CQE_RX_ERR_L4_PORT = 0x64, 162 CQE_RX_ERR_TCP_FLAG = 0x65, 163 CQE_RX_ERR_TCP_OFFSET = 0x66, 164 CQE_RX_ERR_L4_PCLP = 0x67, 165 CQE_RX_ERR_RBDR_TRUNC = 0x70, 166 }; 167 168 struct cqe_rx_t { 169 #if defined(__BIG_ENDIAN_BITFIELD) 170 u64 cqe_type:4; /* W0 */ 171 u64 stdn_fault:1; 172 u64 rsvd0:1; 173 u64 rq_qs:7; 174 u64 rq_idx:3; 175 u64 rsvd1:12; 176 u64 rss_alg:4; 177 u64 rsvd2:4; 178 u64 rb_cnt:4; 179 u64 vlan_found:1; 180 u64 vlan_stripped:1; 181 u64 vlan2_found:1; 182 u64 vlan2_stripped:1; 183 u64 l4_type:4; 184 u64 l3_type:4; 185 u64 l2_present:1; 186 u64 err_level:3; 187 u64 err_opcode:8; 188 189 u64 pkt_len:16; /* W1 */ 190 u64 l2_ptr:8; 191 u64 l3_ptr:8; 192 u64 l4_ptr:8; 193 u64 cq_pkt_len:8; 194 u64 align_pad:3; 195 u64 rsvd3:1; 196 u64 chan:12; 197 198 u64 rss_tag:32; /* W2 */ 199 u64 vlan_tci:16; 200 u64 vlan_ptr:8; 201 u64 vlan2_ptr:8; 202 203 u64 rb3_sz:16; /* W3 */ 204 u64 rb2_sz:16; 205 u64 rb1_sz:16; 206 u64 rb0_sz:16; 207 208 u64 rb7_sz:16; /* W4 */ 209 u64 rb6_sz:16; 210 u64 rb5_sz:16; 211 u64 rb4_sz:16; 212 213 u64 rb11_sz:16; /* W5 */ 214 u64 rb10_sz:16; 215 u64 rb9_sz:16; 216 u64 rb8_sz:16; 217 #elif defined(__LITTLE_ENDIAN_BITFIELD) 218 u64 err_opcode:8; 219 u64 err_level:3; 220 u64 l2_present:1; 221 u64 l3_type:4; 222 u64 l4_type:4; 223 u64 vlan2_stripped:1; 224 u64 vlan2_found:1; 225 u64 vlan_stripped:1; 226 u64 vlan_found:1; 227 u64 rb_cnt:4; 228 u64 rsvd2:4; 229 u64 rss_alg:4; 230 u64 rsvd1:12; 231 u64 rq_idx:3; 232 u64 rq_qs:7; 233 u64 rsvd0:1; 234 u64 stdn_fault:1; 235 u64 cqe_type:4; /* W0 */ 236 u64 chan:12; 237 u64 rsvd3:1; 238 u64 align_pad:3; 239 u64 cq_pkt_len:8; 240 u64 l4_ptr:8; 241 u64 l3_ptr:8; 242 u64 l2_ptr:8; 243 u64 pkt_len:16; /* W1 */ 244 u64 vlan2_ptr:8; 245 u64 vlan_ptr:8; 246 u64 vlan_tci:16; 247 u64 rss_tag:32; /* W2 */ 248 u64 rb0_sz:16; 249 u64 rb1_sz:16; 250 u64 rb2_sz:16; 251 u64 rb3_sz:16; /* W3 */ 252 u64 rb4_sz:16; 253 u64 rb5_sz:16; 254 u64 rb6_sz:16; 255 u64 rb7_sz:16; /* W4 */ 256 u64 rb8_sz:16; 257 u64 rb9_sz:16; 258 u64 rb10_sz:16; 259 u64 rb11_sz:16; /* W5 */ 260 #endif 261 u64 rb0_ptr:64; 262 u64 rb1_ptr:64; 263 u64 rb2_ptr:64; 264 u64 rb3_ptr:64; 265 u64 rb4_ptr:64; 266 u64 rb5_ptr:64; 267 u64 rb6_ptr:64; 268 u64 rb7_ptr:64; 269 u64 rb8_ptr:64; 270 u64 rb9_ptr:64; 271 u64 rb10_ptr:64; 272 u64 rb11_ptr:64; 273 }; 274 275 struct cqe_rx_tcp_err_t { 276 #if defined(__BIG_ENDIAN_BITFIELD) 277 u64 cqe_type:4; /* W0 */ 278 u64 rsvd0:60; 279 280 u64 rsvd1:4; /* W1 */ 281 u64 partial_first:1; 282 u64 rsvd2:27; 283 u64 rbdr_bytes:8; 284 u64 rsvd3:24; 285 #elif defined(__LITTLE_ENDIAN_BITFIELD) 286 u64 rsvd0:60; 287 u64 cqe_type:4; 288 289 u64 rsvd3:24; 290 u64 rbdr_bytes:8; 291 u64 rsvd2:27; 292 u64 partial_first:1; 293 u64 rsvd1:4; 294 #endif 295 }; 296 297 struct cqe_rx_tcp_t { 298 #if defined(__BIG_ENDIAN_BITFIELD) 299 u64 cqe_type:4; /* W0 */ 300 u64 rsvd0:52; 301 u64 cq_tcp_status:8; 302 303 u64 rsvd1:32; /* W1 */ 304 u64 tcp_cntx_bytes:8; 305 u64 rsvd2:8; 306 u64 tcp_err_bytes:16; 307 #elif defined(__LITTLE_ENDIAN_BITFIELD) 308 u64 cq_tcp_status:8; 309 u64 rsvd0:52; 310 u64 cqe_type:4; /* W0 */ 311 312 u64 tcp_err_bytes:16; 313 u64 rsvd2:8; 314 u64 tcp_cntx_bytes:8; 315 u64 rsvd1:32; /* W1 */ 316 #endif 317 }; 318 319 struct cqe_send_t { 320 #if defined(__BIG_ENDIAN_BITFIELD) 321 u64 cqe_type:4; /* W0 */ 322 u64 rsvd0:4; 323 u64 sqe_ptr:16; 324 u64 rsvd1:4; 325 u64 rsvd2:10; 326 u64 sq_qs:7; 327 u64 sq_idx:3; 328 u64 rsvd3:8; 329 u64 send_status:8; 330 331 u64 ptp_timestamp:64; /* W1 */ 332 #elif defined(__LITTLE_ENDIAN_BITFIELD) 333 u64 send_status:8; 334 u64 rsvd3:8; 335 u64 sq_idx:3; 336 u64 sq_qs:7; 337 u64 rsvd2:10; 338 u64 rsvd1:4; 339 u64 sqe_ptr:16; 340 u64 rsvd0:4; 341 u64 cqe_type:4; /* W0 */ 342 343 u64 ptp_timestamp:64; /* W1 */ 344 #endif 345 }; 346 347 union cq_desc_t { 348 u64 u[64]; 349 struct cqe_send_t snd_hdr; 350 struct cqe_rx_t rx_hdr; 351 struct cqe_rx_tcp_t rx_tcp_hdr; 352 struct cqe_rx_tcp_err_t rx_tcp_err_hdr; 353 }; 354 355 struct rbdr_entry_t { 356 #if defined(__BIG_ENDIAN_BITFIELD) 357 u64 rsvd0:15; 358 u64 buf_addr:42; 359 u64 cache_align:7; 360 #elif defined(__LITTLE_ENDIAN_BITFIELD) 361 u64 cache_align:7; 362 u64 buf_addr:42; 363 u64 rsvd0:15; 364 #endif 365 }; 366 367 /* TCP reassembly context */ 368 struct rbe_tcp_cnxt_t { 369 #if defined(__BIG_ENDIAN_BITFIELD) 370 u64 tcp_pkt_cnt:12; 371 u64 rsvd1:4; 372 u64 align_hdr_bytes:4; 373 u64 align_ptr_bytes:4; 374 u64 ptr_bytes:16; 375 u64 rsvd2:24; 376 u64 cqe_type:4; 377 u64 rsvd0:54; 378 u64 tcp_end_reason:2; 379 u64 tcp_status:4; 380 #elif defined(__LITTLE_ENDIAN_BITFIELD) 381 u64 tcp_status:4; 382 u64 tcp_end_reason:2; 383 u64 rsvd0:54; 384 u64 cqe_type:4; 385 u64 rsvd2:24; 386 u64 ptr_bytes:16; 387 u64 align_ptr_bytes:4; 388 u64 align_hdr_bytes:4; 389 u64 rsvd1:4; 390 u64 tcp_pkt_cnt:12; 391 #endif 392 }; 393 394 /* Always Big endian */ 395 struct rx_hdr_t { 396 u64 opaque:32; 397 u64 rss_flow:8; 398 u64 skip_length:6; 399 u64 disable_rss:1; 400 u64 disable_tcp_reassembly:1; 401 u64 nodrop:1; 402 u64 dest_alg:2; 403 u64 rsvd0:2; 404 u64 dest_rq:11; 405 }; 406 407 enum send_l4_csum_type { 408 SEND_L4_CSUM_DISABLE = 0x00, 409 SEND_L4_CSUM_UDP = 0x01, 410 SEND_L4_CSUM_TCP = 0x02, 411 SEND_L4_CSUM_SCTP = 0x03, 412 }; 413 414 enum send_crc_alg { 415 SEND_CRCALG_CRC32 = 0x00, 416 SEND_CRCALG_CRC32C = 0x01, 417 SEND_CRCALG_ICRC = 0x02, 418 }; 419 420 enum send_load_type { 421 SEND_LD_TYPE_LDD = 0x00, 422 SEND_LD_TYPE_LDT = 0x01, 423 SEND_LD_TYPE_LDWB = 0x02, 424 }; 425 426 enum send_mem_alg_type { 427 SEND_MEMALG_SET = 0x00, 428 SEND_MEMALG_ADD = 0x08, 429 SEND_MEMALG_SUB = 0x09, 430 SEND_MEMALG_ADDLEN = 0x0A, 431 SEND_MEMALG_SUBLEN = 0x0B, 432 }; 433 434 enum send_mem_dsz_type { 435 SEND_MEMDSZ_B64 = 0x00, 436 SEND_MEMDSZ_B32 = 0x01, 437 SEND_MEMDSZ_B8 = 0x03, 438 }; 439 440 enum sq_subdesc_type { 441 SQ_DESC_TYPE_INVALID = 0x00, 442 SQ_DESC_TYPE_HEADER = 0x01, 443 SQ_DESC_TYPE_CRC = 0x02, 444 SQ_DESC_TYPE_IMMEDIATE = 0x03, 445 SQ_DESC_TYPE_GATHER = 0x04, 446 SQ_DESC_TYPE_MEMORY = 0x05, 447 }; 448 449 struct sq_crc_subdesc { 450 #if defined(__BIG_ENDIAN_BITFIELD) 451 u64 rsvd1:32; 452 u64 crc_ival:32; 453 u64 subdesc_type:4; 454 u64 crc_alg:2; 455 u64 rsvd0:10; 456 u64 crc_insert_pos:16; 457 u64 hdr_start:16; 458 u64 crc_len:16; 459 #elif defined(__LITTLE_ENDIAN_BITFIELD) 460 u64 crc_len:16; 461 u64 hdr_start:16; 462 u64 crc_insert_pos:16; 463 u64 rsvd0:10; 464 u64 crc_alg:2; 465 u64 subdesc_type:4; 466 u64 crc_ival:32; 467 u64 rsvd1:32; 468 #endif 469 }; 470 471 struct sq_gather_subdesc { 472 #if defined(__BIG_ENDIAN_BITFIELD) 473 u64 subdesc_type:4; /* W0 */ 474 u64 ld_type:2; 475 u64 rsvd0:42; 476 u64 size:16; 477 478 u64 rsvd1:15; /* W1 */ 479 u64 addr:49; 480 #elif defined(__LITTLE_ENDIAN_BITFIELD) 481 u64 size:16; 482 u64 rsvd0:42; 483 u64 ld_type:2; 484 u64 subdesc_type:4; /* W0 */ 485 486 u64 addr:49; 487 u64 rsvd1:15; /* W1 */ 488 #endif 489 }; 490 491 /* SQ immediate subdescriptor */ 492 struct sq_imm_subdesc { 493 #if defined(__BIG_ENDIAN_BITFIELD) 494 u64 subdesc_type:4; /* W0 */ 495 u64 rsvd0:46; 496 u64 len:14; 497 498 u64 data:64; /* W1 */ 499 #elif defined(__LITTLE_ENDIAN_BITFIELD) 500 u64 len:14; 501 u64 rsvd0:46; 502 u64 subdesc_type:4; /* W0 */ 503 504 u64 data:64; /* W1 */ 505 #endif 506 }; 507 508 struct sq_mem_subdesc { 509 #if defined(__BIG_ENDIAN_BITFIELD) 510 u64 subdesc_type:4; /* W0 */ 511 u64 mem_alg:4; 512 u64 mem_dsz:2; 513 u64 wmem:1; 514 u64 rsvd0:21; 515 u64 offset:32; 516 517 u64 rsvd1:15; /* W1 */ 518 u64 addr:49; 519 #elif defined(__LITTLE_ENDIAN_BITFIELD) 520 u64 offset:32; 521 u64 rsvd0:21; 522 u64 wmem:1; 523 u64 mem_dsz:2; 524 u64 mem_alg:4; 525 u64 subdesc_type:4; /* W0 */ 526 527 u64 addr:49; 528 u64 rsvd1:15; /* W1 */ 529 #endif 530 }; 531 532 struct sq_hdr_subdesc { 533 #if defined(__BIG_ENDIAN_BITFIELD) 534 u64 subdesc_type:4; 535 u64 tso:1; 536 u64 post_cqe:1; /* Post CQE on no error also */ 537 u64 dont_send:1; 538 u64 tstmp:1; 539 u64 subdesc_cnt:8; 540 u64 csum_l4:2; 541 u64 csum_l3:1; 542 u64 rsvd0:5; 543 u64 l4_offset:8; 544 u64 l3_offset:8; 545 u64 rsvd1:4; 546 u64 tot_len:20; /* W0 */ 547 548 u64 tso_sdc_cont:8; 549 u64 tso_sdc_first:8; 550 u64 tso_l4_offset:8; 551 u64 tso_flags_last:12; 552 u64 tso_flags_first:12; 553 u64 rsvd2:2; 554 u64 tso_max_paysize:14; /* W1 */ 555 #elif defined(__LITTLE_ENDIAN_BITFIELD) 556 u64 tot_len:20; 557 u64 rsvd1:4; 558 u64 l3_offset:8; 559 u64 l4_offset:8; 560 u64 rsvd0:5; 561 u64 csum_l3:1; 562 u64 csum_l4:2; 563 u64 subdesc_cnt:8; 564 u64 tstmp:1; 565 u64 dont_send:1; 566 u64 post_cqe:1; /* Post CQE on no error also */ 567 u64 tso:1; 568 u64 subdesc_type:4; /* W0 */ 569 570 u64 tso_max_paysize:14; 571 u64 rsvd2:2; 572 u64 tso_flags_first:12; 573 u64 tso_flags_last:12; 574 u64 tso_l4_offset:8; 575 u64 tso_sdc_first:8; 576 u64 tso_sdc_cont:8; /* W1 */ 577 #endif 578 }; 579 580 /* Queue config register formats */ 581 struct rq_cfg { 582 #if defined(__BIG_ENDIAN_BITFIELD) 583 u64 reserved_2_63:62; 584 u64 ena:1; 585 u64 tcp_ena:1; 586 #elif defined(__LITTLE_ENDIAN_BITFIELD) 587 u64 tcp_ena:1; 588 u64 ena:1; 589 u64 reserved_2_63:62; 590 #endif 591 }; 592 593 struct cq_cfg { 594 #if defined(__BIG_ENDIAN_BITFIELD) 595 u64 reserved_43_63:21; 596 u64 ena:1; 597 u64 reset:1; 598 u64 caching:1; 599 u64 reserved_35_39:5; 600 u64 qsize:3; 601 u64 reserved_25_31:7; 602 u64 avg_con:9; 603 u64 reserved_0_15:16; 604 #elif defined(__LITTLE_ENDIAN_BITFIELD) 605 u64 reserved_0_15:16; 606 u64 avg_con:9; 607 u64 reserved_25_31:7; 608 u64 qsize:3; 609 u64 reserved_35_39:5; 610 u64 caching:1; 611 u64 reset:1; 612 u64 ena:1; 613 u64 reserved_43_63:21; 614 #endif 615 }; 616 617 struct sq_cfg { 618 #if defined(__BIG_ENDIAN_BITFIELD) 619 u64 reserved_20_63:44; 620 u64 ena:1; 621 u64 reserved_18_18:1; 622 u64 reset:1; 623 u64 ldwb:1; 624 u64 reserved_11_15:5; 625 u64 qsize:3; 626 u64 reserved_3_7:5; 627 u64 tstmp_bgx_intf:3; 628 #elif defined(__LITTLE_ENDIAN_BITFIELD) 629 u64 tstmp_bgx_intf:3; 630 u64 reserved_3_7:5; 631 u64 qsize:3; 632 u64 reserved_11_15:5; 633 u64 ldwb:1; 634 u64 reset:1; 635 u64 reserved_18_18:1; 636 u64 ena:1; 637 u64 reserved_20_63:44; 638 #endif 639 }; 640 641 struct rbdr_cfg { 642 #if defined(__BIG_ENDIAN_BITFIELD) 643 u64 reserved_45_63:19; 644 u64 ena:1; 645 u64 reset:1; 646 u64 ldwb:1; 647 u64 reserved_36_41:6; 648 u64 qsize:4; 649 u64 reserved_25_31:7; 650 u64 avg_con:9; 651 u64 reserved_12_15:4; 652 u64 lines:12; 653 #elif defined(__LITTLE_ENDIAN_BITFIELD) 654 u64 lines:12; 655 u64 reserved_12_15:4; 656 u64 avg_con:9; 657 u64 reserved_25_31:7; 658 u64 qsize:4; 659 u64 reserved_36_41:6; 660 u64 ldwb:1; 661 u64 reset:1; 662 u64 ena: 1; 663 u64 reserved_45_63:19; 664 #endif 665 }; 666 667 struct qs_cfg { 668 #if defined(__BIG_ENDIAN_BITFIELD) 669 u64 reserved_32_63:32; 670 u64 ena:1; 671 u64 reserved_27_30:4; 672 u64 sq_ins_ena:1; 673 u64 sq_ins_pos:6; 674 u64 lock_ena:1; 675 u64 lock_viol_cqe_ena:1; 676 u64 send_tstmp_ena:1; 677 u64 be:1; 678 u64 reserved_7_15:9; 679 u64 vnic:7; 680 #elif defined(__LITTLE_ENDIAN_BITFIELD) 681 u64 vnic:7; 682 u64 reserved_7_15:9; 683 u64 be:1; 684 u64 send_tstmp_ena:1; 685 u64 lock_viol_cqe_ena:1; 686 u64 lock_ena:1; 687 u64 sq_ins_pos:6; 688 u64 sq_ins_ena:1; 689 u64 reserved_27_30:4; 690 u64 ena:1; 691 u64 reserved_32_63:32; 692 #endif 693 }; 694 695 #endif /* Q_STRUCT_H */ 696