1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * SuperH SCIF device driver.
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2007,2008,2010, 2014 Nobuhiro Iwamatsu
6 * Copyright (C) 2002 - 2008 Paul Mundt
7 */
8
9 #include <common.h>
10 #include <errno.h>
11 #include <clk.h>
12 #include <dm.h>
13 #include <asm/global_data.h>
14 #include <asm/io.h>
15 #include <asm/processor.h>
16 #include <serial.h>
17 #include <linux/compiler.h>
18 #include <dm/platform_data/serial_sh.h>
19 #include <linux/delay.h>
20 #include "serial_sh.h"
21
22 DECLARE_GLOBAL_DATA_PTR;
23
24 #if defined(CONFIG_CPU_SH7780)
scif_rxfill(struct uart_port * port)25 static int scif_rxfill(struct uart_port *port)
26 {
27 return sci_in(port, SCRFDR) & 0xff;
28 }
29 #elif defined(CONFIG_CPU_SH7763)
scif_rxfill(struct uart_port * port)30 static int scif_rxfill(struct uart_port *port)
31 {
32 if ((port->mapbase == 0xffe00000) ||
33 (port->mapbase == 0xffe08000)) {
34 /* SCIF0/1*/
35 return sci_in(port, SCRFDR) & 0xff;
36 } else {
37 /* SCIF2 */
38 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
39 }
40 }
41 #else
scif_rxfill(struct uart_port * port)42 static int scif_rxfill(struct uart_port *port)
43 {
44 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
45 }
46 #endif
47
sh_serial_init_generic(struct uart_port * port)48 static void sh_serial_init_generic(struct uart_port *port)
49 {
50 sci_out(port, SCSCR , SCSCR_INIT(port));
51 sci_out(port, SCSCR , SCSCR_INIT(port));
52 sci_out(port, SCSMR, 0);
53 sci_out(port, SCSMR, 0);
54 sci_out(port, SCFCR, SCFCR_RFRST|SCFCR_TFRST);
55 sci_in(port, SCFCR);
56 sci_out(port, SCFCR, 0);
57 #if defined(CONFIG_RZA1)
58 sci_out(port, SCSPTR, 0x0003);
59 #endif
60 }
61
62 static void
sh_serial_setbrg_generic(struct uart_port * port,int clk,int baudrate)63 sh_serial_setbrg_generic(struct uart_port *port, int clk, int baudrate)
64 {
65 if (port->clk_mode == EXT_CLK) {
66 unsigned short dl = DL_VALUE(baudrate, clk);
67 sci_out(port, DL, dl);
68 /* Need wait: Clock * 1/dl * 1/16 */
69 udelay((1000000 * dl * 16 / clk) * 1000 + 1);
70 } else {
71 sci_out(port, SCBRR, SCBRR_VALUE(baudrate, clk));
72 }
73 }
74
handle_error(struct uart_port * port)75 static void handle_error(struct uart_port *port)
76 {
77 sci_in(port, SCxSR);
78 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
79 sci_in(port, SCLSR);
80 sci_out(port, SCLSR, 0x00);
81 }
82
serial_raw_putc(struct uart_port * port,const char c)83 static int serial_raw_putc(struct uart_port *port, const char c)
84 {
85 /* Tx fifo is empty */
86 if (!(sci_in(port, SCxSR) & SCxSR_TEND(port)))
87 return -EAGAIN;
88
89 sci_out(port, SCxTDR, c);
90 sci_out(port, SCxSR, sci_in(port, SCxSR) & ~SCxSR_TEND(port));
91
92 return 0;
93 }
94
serial_rx_fifo_level(struct uart_port * port)95 static int serial_rx_fifo_level(struct uart_port *port)
96 {
97 return scif_rxfill(port);
98 }
99
sh_serial_tstc_generic(struct uart_port * port)100 static int sh_serial_tstc_generic(struct uart_port *port)
101 {
102 if (sci_in(port, SCxSR) & SCIF_ERRORS) {
103 handle_error(port);
104 return 0;
105 }
106
107 return serial_rx_fifo_level(port) ? 1 : 0;
108 }
109
serial_getc_check(struct uart_port * port)110 static int serial_getc_check(struct uart_port *port)
111 {
112 unsigned short status;
113
114 status = sci_in(port, SCxSR);
115
116 if (status & SCIF_ERRORS)
117 handle_error(port);
118 if (sci_in(port, SCLSR) & SCxSR_ORER(port))
119 handle_error(port);
120 status &= (SCIF_DR | SCxSR_RDxF(port));
121 if (status)
122 return status;
123 return scif_rxfill(port);
124 }
125
sh_serial_getc_generic(struct uart_port * port)126 static int sh_serial_getc_generic(struct uart_port *port)
127 {
128 unsigned short status;
129 char ch;
130
131 if (!serial_getc_check(port))
132 return -EAGAIN;
133
134 ch = sci_in(port, SCxRDR);
135 status = sci_in(port, SCxSR);
136
137 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
138
139 if (status & SCIF_ERRORS)
140 handle_error(port);
141
142 if (sci_in(port, SCLSR) & SCxSR_ORER(port))
143 handle_error(port);
144
145 return ch;
146 }
147
148 #if CONFIG_IS_ENABLED(DM_SERIAL)
149
sh_serial_pending(struct udevice * dev,bool input)150 static int sh_serial_pending(struct udevice *dev, bool input)
151 {
152 struct uart_port *priv = dev_get_priv(dev);
153
154 return sh_serial_tstc_generic(priv);
155 }
156
sh_serial_putc(struct udevice * dev,const char ch)157 static int sh_serial_putc(struct udevice *dev, const char ch)
158 {
159 struct uart_port *priv = dev_get_priv(dev);
160
161 return serial_raw_putc(priv, ch);
162 }
163
sh_serial_getc(struct udevice * dev)164 static int sh_serial_getc(struct udevice *dev)
165 {
166 struct uart_port *priv = dev_get_priv(dev);
167
168 return sh_serial_getc_generic(priv);
169 }
170
sh_serial_setbrg(struct udevice * dev,int baudrate)171 static int sh_serial_setbrg(struct udevice *dev, int baudrate)
172 {
173 struct sh_serial_plat *plat = dev_get_plat(dev);
174 struct uart_port *priv = dev_get_priv(dev);
175
176 sh_serial_setbrg_generic(priv, plat->clk, baudrate);
177
178 return 0;
179 }
180
sh_serial_probe(struct udevice * dev)181 static int sh_serial_probe(struct udevice *dev)
182 {
183 struct sh_serial_plat *plat = dev_get_plat(dev);
184 struct uart_port *priv = dev_get_priv(dev);
185
186 priv->membase = (unsigned char *)plat->base;
187 priv->mapbase = plat->base;
188 priv->type = plat->type;
189 priv->clk_mode = plat->clk_mode;
190
191 sh_serial_init_generic(priv);
192
193 return 0;
194 }
195
196 static const struct dm_serial_ops sh_serial_ops = {
197 .putc = sh_serial_putc,
198 .pending = sh_serial_pending,
199 .getc = sh_serial_getc,
200 .setbrg = sh_serial_setbrg,
201 };
202
203 #if CONFIG_IS_ENABLED(OF_CONTROL)
204 static const struct udevice_id sh_serial_id[] ={
205 {.compatible = "renesas,sci", .data = PORT_SCI},
206 {.compatible = "renesas,scif", .data = PORT_SCIF},
207 {.compatible = "renesas,scifa", .data = PORT_SCIFA},
208 {}
209 };
210
sh_serial_of_to_plat(struct udevice * dev)211 static int sh_serial_of_to_plat(struct udevice *dev)
212 {
213 struct sh_serial_plat *plat = dev_get_plat(dev);
214 struct clk sh_serial_clk;
215 fdt_addr_t addr;
216 int ret;
217
218 addr = dev_read_addr(dev);
219 if (!addr)
220 return -EINVAL;
221
222 plat->base = addr;
223
224 ret = clk_get_by_name(dev, "fck", &sh_serial_clk);
225 if (!ret) {
226 ret = clk_enable(&sh_serial_clk);
227 if (!ret)
228 plat->clk = clk_get_rate(&sh_serial_clk);
229 } else {
230 plat->clk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
231 "clock", 1);
232 }
233
234 plat->type = dev_get_driver_data(dev);
235 return 0;
236 }
237 #endif
238
239 U_BOOT_DRIVER(serial_sh) = {
240 .name = "serial_sh",
241 .id = UCLASS_SERIAL,
242 .of_match = of_match_ptr(sh_serial_id),
243 .of_to_plat = of_match_ptr(sh_serial_of_to_plat),
244 .plat_auto = sizeof(struct sh_serial_plat),
245 .probe = sh_serial_probe,
246 .ops = &sh_serial_ops,
247 #if !CONFIG_IS_ENABLED(OF_CONTROL)
248 .flags = DM_FLAG_PRE_RELOC,
249 #endif
250 .priv_auto = sizeof(struct uart_port),
251 };
252
253 #else /* CONFIG_DM_SERIAL */
254
255 #if defined(CONFIG_CONS_SCIF0)
256 # define SCIF_BASE SCIF0_BASE
257 #elif defined(CONFIG_CONS_SCIF1)
258 # define SCIF_BASE SCIF1_BASE
259 #elif defined(CONFIG_CONS_SCIF2)
260 # define SCIF_BASE SCIF2_BASE
261 #elif defined(CONFIG_CONS_SCIF3)
262 # define SCIF_BASE SCIF3_BASE
263 #elif defined(CONFIG_CONS_SCIF4)
264 # define SCIF_BASE SCIF4_BASE
265 #elif defined(CONFIG_CONS_SCIF5)
266 # define SCIF_BASE SCIF5_BASE
267 #elif defined(CONFIG_CONS_SCIF6)
268 # define SCIF_BASE SCIF6_BASE
269 #elif defined(CONFIG_CONS_SCIF7)
270 # define SCIF_BASE SCIF7_BASE
271 #elif defined(CONFIG_CONS_SCIFA0)
272 # define SCIF_BASE SCIFA0_BASE
273 #else
274 # error "Default SCIF doesn't set....."
275 #endif
276
277 #if defined(CONFIG_SCIF_A)
278 #define SCIF_BASE_PORT PORT_SCIFA
279 #elif defined(CONFIG_SCI)
280 #define SCIF_BASE_PORT PORT_SCI
281 #else
282 #define SCIF_BASE_PORT PORT_SCIF
283 #endif
284
285 static struct uart_port sh_sci = {
286 .membase = (unsigned char *)SCIF_BASE,
287 .mapbase = SCIF_BASE,
288 .type = SCIF_BASE_PORT,
289 #ifdef CONFIG_SCIF_USE_EXT_CLK
290 .clk_mode = EXT_CLK,
291 #endif
292 };
293
sh_serial_setbrg(void)294 static void sh_serial_setbrg(void)
295 {
296 DECLARE_GLOBAL_DATA_PTR;
297 struct uart_port *port = &sh_sci;
298
299 sh_serial_setbrg_generic(port, CONFIG_SH_SCIF_CLK_FREQ, gd->baudrate);
300 }
301
sh_serial_init(void)302 static int sh_serial_init(void)
303 {
304 struct uart_port *port = &sh_sci;
305
306 sh_serial_init_generic(port);
307 serial_setbrg();
308
309 return 0;
310 }
311
sh_serial_putc(const char c)312 static void sh_serial_putc(const char c)
313 {
314 struct uart_port *port = &sh_sci;
315
316 if (c == '\n') {
317 while (1) {
318 if (serial_raw_putc(port, '\r') != -EAGAIN)
319 break;
320 }
321 }
322 while (1) {
323 if (serial_raw_putc(port, c) != -EAGAIN)
324 break;
325 }
326 }
327
sh_serial_tstc(void)328 static int sh_serial_tstc(void)
329 {
330 struct uart_port *port = &sh_sci;
331
332 return sh_serial_tstc_generic(port);
333 }
334
sh_serial_getc(void)335 static int sh_serial_getc(void)
336 {
337 struct uart_port *port = &sh_sci;
338 int ch;
339
340 while (1) {
341 ch = sh_serial_getc_generic(port);
342 if (ch != -EAGAIN)
343 break;
344 }
345
346 return ch;
347 }
348
349 static struct serial_device sh_serial_drv = {
350 .name = "sh_serial",
351 .start = sh_serial_init,
352 .stop = NULL,
353 .setbrg = sh_serial_setbrg,
354 .putc = sh_serial_putc,
355 .puts = default_serial_puts,
356 .getc = sh_serial_getc,
357 .tstc = sh_serial_tstc,
358 };
359
sh_serial_initialize(void)360 void sh_serial_initialize(void)
361 {
362 serial_register(&sh_serial_drv);
363 }
364
default_serial_console(void)365 __weak struct serial_device *default_serial_console(void)
366 {
367 return &sh_serial_drv;
368 }
369 #endif /* CONFIG_DM_SERIAL */
370