1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2011-2012 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef _ASM_MPC85xx_CONFIG_H_ 7 #define _ASM_MPC85xx_CONFIG_H_ 8 9 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 10 11 /* 12 * This macro should be removed when we no longer care about backwards 13 * compatibility with older operating systems. 14 */ 15 #define CONFIG_PPC_SPINTABLE_COMPATIBLE 16 17 #include <fsl_ddrc_version.h> 18 19 /* IP endianness */ 20 #define CONFIG_SYS_FSL_IFC_BE 21 #define CONFIG_SYS_FSL_SFP_BE 22 #define CONFIG_SYS_FSL_SEC_MON_BE 23 24 #if defined(CONFIG_ARCH_MPC8548) 25 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 26 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 27 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 28 #define CONFIG_SYS_FSL_RMU 29 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 30 31 #elif defined(CONFIG_ARCH_MPC8568) 32 #define QE_MURAM_SIZE 0x10000UL 33 #define MAX_QE_RISC 2 34 #define QE_NUM_OF_SNUM 28 35 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 36 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 37 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 38 #define CONFIG_SYS_FSL_RMU 39 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 40 41 #elif defined(CONFIG_ARCH_P1010) 42 #define CONFIG_FSL_SDHC_V2_3 43 #define CONFIG_TSECV2 44 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 45 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 46 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 47 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 48 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 49 #define CONFIG_ESDHC_HC_BLK_ADDR 50 51 /* P1011 is single core version of P1020 */ 52 #elif defined(CONFIG_ARCH_P1011) 53 #define CONFIG_TSECV2 54 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 55 56 #elif defined(CONFIG_ARCH_P1020) 57 #define CONFIG_TSECV2 58 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT 59 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 60 #endif 61 62 #elif defined(CONFIG_ARCH_P1021) 63 #define CONFIG_TSECV2 64 #define QE_MURAM_SIZE 0x6000UL 65 #define MAX_QE_RISC 1 66 #define QE_NUM_OF_SNUM 28 67 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 68 69 #elif defined(CONFIG_ARCH_P1023) 70 #define CONFIG_SYS_NUM_FMAN 1 71 #define CONFIG_SYS_NUM_FM1_DTSEC 2 72 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 73 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 74 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 75 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 76 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 77 78 /* P1024 is lower end variant of P1020 */ 79 #elif defined(CONFIG_ARCH_P1024) 80 #define CONFIG_TSECV2 81 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 82 83 /* P1025 is lower end variant of P1021 */ 84 #elif defined(CONFIG_ARCH_P1025) 85 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 86 #define CONFIG_TSECV2 87 #define QE_MURAM_SIZE 0x6000UL 88 #define MAX_QE_RISC 1 89 #define QE_NUM_OF_SNUM 28 90 91 #elif defined(CONFIG_ARCH_P2020) 92 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 93 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 94 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 95 #define CONFIG_SYS_FSL_RMU 96 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 97 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 98 99 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */ 100 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 101 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 102 #define CONFIG_SYS_NUM_FMAN 1 103 #define CONFIG_SYS_NUM_FM1_DTSEC 5 104 #define CONFIG_SYS_NUM_FM1_10GEC 1 105 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT 106 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 107 #endif 108 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 109 #define CONFIG_SYS_FSL_TBCLK_DIV 32 110 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 111 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 112 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 113 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 114 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 115 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 116 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 117 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 118 119 #elif defined(CONFIG_ARCH_P3041) 120 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 121 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 122 #define CONFIG_SYS_NUM_FMAN 1 123 #define CONFIG_SYS_NUM_FM1_DTSEC 5 124 #define CONFIG_SYS_NUM_FM1_10GEC 1 125 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 126 #define CONFIG_SYS_FSL_TBCLK_DIV 32 127 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 128 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 129 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 130 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 131 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 132 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 133 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 134 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 135 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 136 137 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */ 138 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 139 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 140 #define CONFIG_SYS_NUM_FMAN 2 141 #define CONFIG_SYS_NUM_FM1_DTSEC 4 142 #define CONFIG_SYS_NUM_FM2_DTSEC 4 143 #define CONFIG_SYS_NUM_FM1_10GEC 1 144 #define CONFIG_SYS_NUM_FM2_10GEC 1 145 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 146 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 147 #define CONFIG_SYS_FSL_TBCLK_DIV 16 148 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 149 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 150 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 151 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 152 #define CONFIG_SYS_FSL_RMU 153 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 154 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 155 156 #elif defined(CONFIG_ARCH_P5040) 157 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 158 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 159 #define CONFIG_SYS_NUM_FMAN 2 160 #define CONFIG_SYS_NUM_FM1_DTSEC 5 161 #define CONFIG_SYS_NUM_FM1_10GEC 1 162 #define CONFIG_SYS_NUM_FM2_DTSEC 5 163 #define CONFIG_SYS_NUM_FM2_10GEC 1 164 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 165 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 166 #define CONFIG_SYS_FSL_TBCLK_DIV 16 167 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 168 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 169 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 170 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 171 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 172 173 #elif defined(CONFIG_ARCH_BSC9131) 174 #define CONFIG_FSL_SDHC_V2_3 175 #define CONFIG_TSECV2 176 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 177 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 178 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 179 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 180 #define CONFIG_NAND_FSL_IFC 181 #define CONFIG_ESDHC_HC_BLK_ADDR 182 183 #elif defined(CONFIG_ARCH_BSC9132) 184 #define CONFIG_FSL_SDHC_V2_3 185 #define CONFIG_TSECV2 186 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 187 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 188 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 189 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 190 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 191 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 192 #define CONFIG_NAND_FSL_IFC 193 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK 194 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 195 #define CONFIG_ESDHC_HC_BLK_ADDR 196 197 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) 198 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 199 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 200 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 201 #ifdef CONFIG_ARCH_T4240 202 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } 203 #define CONFIG_SYS_NUM_FM1_DTSEC 8 204 #define CONFIG_SYS_NUM_FM1_10GEC 2 205 #define CONFIG_SYS_NUM_FM2_DTSEC 8 206 #define CONFIG_SYS_NUM_FM2_10GEC 2 207 #else 208 #define CONFIG_SYS_NUM_FM1_DTSEC 6 209 #define CONFIG_SYS_NUM_FM1_10GEC 1 210 #define CONFIG_SYS_NUM_FM2_DTSEC 8 211 #define CONFIG_SYS_NUM_FM2_10GEC 1 212 #if defined(CONFIG_ARCH_T4160) 213 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 214 #endif 215 #endif 216 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 217 #define CONFIG_SYS_FSL_SRDS_1 218 #define CONFIG_SYS_FSL_SRDS_2 219 #define CONFIG_SYS_FSL_SRDS_3 220 #define CONFIG_SYS_FSL_SRDS_4 221 #define CONFIG_SYS_NUM_FMAN 2 222 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 223 #define CONFIG_SYS_PME_CLK 0 224 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 225 #define CONFIG_SYS_FMAN_V3 226 #define CONFIG_SYS_FM1_CLK 3 227 #define CONFIG_SYS_FM2_CLK 3 228 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 229 #define CONFIG_SYS_FSL_TBCLK_DIV 16 230 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 231 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 232 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 233 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 234 #define CONFIG_SYS_FSL_SRIO_LIODN 235 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 236 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 237 #define CONFIG_SYS_FSL_SFP_VER_3_0 238 #define CONFIG_SYS_FSL_PCI_VER_3_X 239 240 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) 241 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 242 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 243 #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */ 244 #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/ 245 #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/ 246 #define CONFIG_SYS_FSL_SRDS_1 247 #define CONFIG_SYS_FSL_SRDS_2 248 #define CONFIG_SYS_MAPLE 249 #define CONFIG_SYS_CPRI 250 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 251 #define CONFIG_SYS_NUM_FMAN 1 252 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 253 #define CONFIG_SYS_FM1_CLK 0 254 #define CONFIG_SYS_CPRI_CLK 3 255 #define CONFIG_SYS_ULB_CLK 4 256 #define CONFIG_SYS_ETVPE_CLK 1 257 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 258 #define CONFIG_SYS_FMAN_V3 259 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 260 #define CONFIG_SYS_FSL_TBCLK_DIV 16 261 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 262 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 263 #define CONFIG_SYS_FSL_SFP_VER_3_0 264 265 #ifdef CONFIG_ARCH_B4860 266 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 267 #define CONFIG_MAX_DSP_CPUS 12 268 #define CONFIG_NUM_DSP_CPUS 6 269 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2 270 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 271 #define CONFIG_SYS_NUM_FM1_DTSEC 6 272 #define CONFIG_SYS_NUM_FM1_10GEC 2 273 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 274 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 275 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 276 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 277 #define CONFIG_SYS_FSL_SRIO_LIODN 278 #else 279 #define CONFIG_MAX_DSP_CPUS 2 280 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1 281 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 282 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } 283 #define CONFIG_SYS_NUM_FM1_DTSEC 4 284 #define CONFIG_SYS_NUM_FM1_10GEC 0 285 #endif 286 287 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) 288 #define CONFIG_E5500 289 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 290 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 291 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 292 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 293 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 294 #define CONFIG_SYS_FSL_SRDS_1 295 #define CONFIG_SYS_NUM_FMAN 1 296 #define CONFIG_SYS_NUM_FM1_DTSEC 5 297 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 298 #define CONFIG_PME_PLAT_CLK_DIV 2 299 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 300 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 301 #define CONFIG_SYS_FMAN_V3 302 #define CONFIG_FM_PLAT_CLK_DIV 1 303 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV 304 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 305 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 306 #define CONFIG_SYS_FSL_TBCLK_DIV 16 307 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 308 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 309 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 310 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 311 #define QE_MURAM_SIZE 0x6000UL 312 #define MAX_QE_RISC 1 313 #define QE_NUM_OF_SNUM 28 314 #define CONFIG_SYS_FSL_SFP_VER_3_0 315 316 #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) 317 #define CONFIG_E5500 318 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 319 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 320 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 321 #define CONFIG_SYS_FMAN_V3 322 #define CONFIG_SYS_FSL_NUM_CC_PLL 2 323 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 324 #define CONFIG_SYS_FSL_SRDS_1 325 #define CONFIG_SYS_NUM_FMAN 1 326 #define CONFIG_SYS_NUM_FM1_DTSEC 4 327 #define CONFIG_SYS_NUM_FM1_10GEC 1 328 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION 329 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 330 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 331 #define CONFIG_SYS_FM1_CLK 0 332 #define CONFIG_QBMAN_CLK_DIV 1 333 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 334 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 335 #define CONFIG_SYS_FSL_TBCLK_DIV 16 336 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 337 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 338 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 339 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 340 #define QE_MURAM_SIZE 0x6000UL 341 #define MAX_QE_RISC 1 342 #define QE_NUM_OF_SNUM 28 343 #define CONFIG_SYS_FSL_SFP_VER_3_0 344 345 #elif defined(CONFIG_ARCH_T2080) 346 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 347 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 348 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 349 #define CONFIG_SYS_FSL_QMAN_V3 350 #define CONFIG_SYS_NUM_FMAN 1 351 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 352 #define CONFIG_SYS_FSL_SRDS_1 353 #define CONFIG_SYS_FSL_PCI_VER_3_X 354 #if defined(CONFIG_ARCH_T2080) 355 #define CONFIG_SYS_NUM_FM1_DTSEC 8 356 #define CONFIG_SYS_NUM_FM1_10GEC 4 357 #define CONFIG_SYS_FSL_SRDS_2 358 #define CONFIG_SYS_FSL_SRIO_LIODN 359 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 360 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 361 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 362 #endif 363 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 364 #define CONFIG_PME_PLAT_CLK_DIV 1 365 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 366 #define CONFIG_SYS_FM1_CLK 0 367 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 368 #define CONFIG_SYS_FMAN_V3 369 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 370 #define CONFIG_SYS_FSL_TBCLK_DIV 16 371 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 372 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 373 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 374 #define CONFIG_SYS_FSL_SFP_VER_3_0 375 #define CONFIG_SYS_FSL_ISBC_VER 2 376 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 377 #define CONFIG_SYS_FSL_SFP_VER_3_0 378 379 380 #elif defined(CONFIG_ARCH_C29X) 381 #define CONFIG_FSL_SDHC_V2_3 382 #define CONFIG_TSECV2_1 383 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 384 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3 385 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000 386 387 #endif 388 389 #if !defined(CONFIG_ARCH_C29X) 390 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 391 #endif 392 393 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 394