1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
4 *
5 * Author: Scott Wood <scottwood@freescale.com>
6 *
7 * (C) Copyright 2010
8 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
9 */
10
11 #include <common.h>
12 #include <fdt_support.h>
13 #include <init.h>
14 #include <asm/global_data.h>
15 #include <linux/delay.h>
16 #include <linux/libfdt.h>
17 #include <pci.h>
18 #include <mpc83xx.h>
19 #include <ns16550.h>
20 #include <nand.h>
21
22 #include <asm/bitops.h>
23 #include <asm/io.h>
24
25 DECLARE_GLOBAL_DATA_PTR;
26
27 extern void disable_addr_trans (void);
28 extern void enable_addr_trans (void);
29
checkboard(void)30 int checkboard(void)
31 {
32 puts("Board: ve8313\n");
33 return 0;
34 }
35
fixed_sdram(void)36 static long fixed_sdram(void)
37 {
38 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
39
40 #ifndef CONFIG_SYS_RAMBOOT
41 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
42 u32 msize_log2 = __ilog2(msize);
43
44 out_be32(&im->sysconf.ddrlaw[0].bar,
45 (CONFIG_SYS_SDRAM_BASE & 0xfffff000));
46 out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1)));
47 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
48
49 /*
50 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
51 * or the DDR2 controller may fail to initialize correctly.
52 */
53 __udelay(50000);
54
55 #if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
56 #warning Chip select bounds is only configurable in 16MB increments
57 #endif
58 out_be32(&im->ddr.csbnds[0].csbnds,
59 ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
60 (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
61 CSBNDS_EA));
62 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
63
64 /* Currently we use only one CS, so disable the other bank. */
65 out_be32(&im->ddr.cs_config[1], 0);
66
67 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
68 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
69 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
70 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
71 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
72
73 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
74
75 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
76 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
77 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
78
79 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
80 sync();
81
82 /* enable DDR controller */
83 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
84
85 /* now check the real size */
86 disable_addr_trans ();
87 msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
88 enable_addr_trans ();
89 #endif
90
91 return msize;
92 }
93
dram_init(void)94 int dram_init(void)
95 {
96 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
97 volatile fsl_lbc_t *lbc = &im->im_lbc;
98 u32 msize;
99
100 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
101 return -1;
102
103 /* DDR SDRAM - Main SODIMM */
104 msize = fixed_sdram();
105
106 /* Local Bus setup lbcr and mrtpr */
107 out_be32(&lbc->lbcr, 0x00040000);
108 out_be32(&lbc->mrtpr, 0x20000000);
109 sync();
110
111 /* return total bus SDRAM size(bytes) -- DDR */
112 gd->ram_size = msize;
113
114 return 0;
115 }
116
117 #define VE8313_WDT_EN 0x00020000
118 #define VE8313_WDT_TRIG 0x00040000
119
board_early_init_f(void)120 int board_early_init_f (void)
121 {
122 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
123 volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
124
125 #if defined(CONFIG_HW_WATCHDOG)
126 /* enable WDT */
127 clrbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
128 #else
129 /* disable WDT */
130 setbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
131 #endif
132 /* set WDT pins as output */
133 setbits_be32(&gpio->dir, VE8313_WDT_EN | VE8313_WDT_TRIG);
134
135 return 0;
136 }
137
138 #if defined(CONFIG_HW_WATCHDOG)
hw_watchdog_reset(void)139 void hw_watchdog_reset(void)
140 {
141 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
142 volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
143 unsigned long reg;
144
145 reg = in_be32(&gpio->dat);
146 if (reg & VE8313_WDT_TRIG)
147 clrbits_be32(&gpio->dat, VE8313_WDT_TRIG);
148 else
149 setbits_be32(&gpio->dat, VE8313_WDT_TRIG);
150 }
151 #endif
152
153
154 #if defined(CONFIG_PCI)
155 static struct pci_region pci_regions[] = {
156 {
157 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
158 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
159 size: CONFIG_SYS_PCI1_MEM_SIZE,
160 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
161 },
162 {
163 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
164 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
165 size: CONFIG_SYS_PCI1_MMIO_SIZE,
166 flags: PCI_REGION_MEM
167 },
168 {
169 bus_start: CONFIG_SYS_PCI1_IO_BASE,
170 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
171 size: CONFIG_SYS_PCI1_IO_SIZE,
172 flags: PCI_REGION_IO
173 }
174 };
175
pci_init_board(void)176 void pci_init_board(void)
177 {
178 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
179 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
180 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
181 struct pci_region *reg[] = { pci_regions };
182
183 /* Enable all 3 PCI_CLK_OUTPUTs. */
184 setbits_be32(&clk->occr, 0xe0000000);
185
186 /*
187 * Configure PCI Local Access Windows
188 */
189 out_be32(&pci_law[0].bar, CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR);
190 out_be32(&pci_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
191
192 out_be32(&pci_law[1].bar, CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR);
193 out_be32(&pci_law[1].ar, LBLAWAR_EN | LBLAWAR_1MB);
194
195 mpc83xx_pci_init(1, reg);
196 }
197 #endif
198
199 #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,struct bd_info * bd)200 int ft_board_setup(void *blob, struct bd_info *bd)
201 {
202 ft_cpu_setup(blob, bd);
203 #ifdef CONFIG_PCI
204 ft_pci_setup(blob, bd);
205 #endif
206
207 return 0;
208 }
209 #endif
210