1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Atmel QSPI Controller
4 *
5 * Copyright (C) 2015 Atmel Corporation
6 * Copyright (C) 2018 Cryptera A/S
7 *
8 * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
9 * Author: Piotr Bugalski <bugalski.piotr@gmail.com>
10 */
11
12 #include <malloc.h>
13 #include <asm/io.h>
14 #include <clk.h>
15 #include <common.h>
16 #include <dm.h>
17 #include <errno.h>
18 #include <fdtdec.h>
19 #include <dm/device_compat.h>
20 #include <linux/bitops.h>
21 #include <linux/err.h>
22 #include <linux/io.h>
23 #include <linux/iopoll.h>
24 #include <linux/ioport.h>
25 #include <mach/clk.h>
26 #include <spi.h>
27 #include <spi-mem.h>
28
29 /* QSPI register offsets */
30 #define QSPI_CR 0x0000 /* Control Register */
31 #define QSPI_MR 0x0004 /* Mode Register */
32 #define QSPI_RD 0x0008 /* Receive Data Register */
33 #define QSPI_TD 0x000c /* Transmit Data Register */
34 #define QSPI_SR 0x0010 /* Status Register */
35 #define QSPI_IER 0x0014 /* Interrupt Enable Register */
36 #define QSPI_IDR 0x0018 /* Interrupt Disable Register */
37 #define QSPI_IMR 0x001c /* Interrupt Mask Register */
38 #define QSPI_SCR 0x0020 /* Serial Clock Register */
39
40 #define QSPI_IAR 0x0030 /* Instruction Address Register */
41 #define QSPI_ICR 0x0034 /* Instruction Code Register */
42 #define QSPI_WICR 0x0034 /* Write Instruction Code Register */
43 #define QSPI_IFR 0x0038 /* Instruction Frame Register */
44 #define QSPI_RICR 0x003C /* Read Instruction Code Register */
45
46 #define QSPI_SMR 0x0040 /* Scrambling Mode Register */
47 #define QSPI_SKR 0x0044 /* Scrambling Key Register */
48
49 #define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */
50 #define QSPI_WPSR 0x00E8 /* Write Protection Status Register */
51
52 #define QSPI_VERSION 0x00FC /* Version Register */
53
54 /* Bitfields in QSPI_CR (Control Register) */
55 #define QSPI_CR_QSPIEN BIT(0)
56 #define QSPI_CR_QSPIDIS BIT(1)
57 #define QSPI_CR_SWRST BIT(7)
58 #define QSPI_CR_LASTXFER BIT(24)
59
60 /* Bitfields in QSPI_MR (Mode Register) */
61 #define QSPI_MR_SMM BIT(0)
62 #define QSPI_MR_LLB BIT(1)
63 #define QSPI_MR_WDRBT BIT(2)
64 #define QSPI_MR_SMRM BIT(3)
65 #define QSPI_MR_CSMODE_MASK GENMASK(5, 4)
66 #define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4)
67 #define QSPI_MR_CSMODE_LASTXFER (1 << 4)
68 #define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4)
69 #define QSPI_MR_NBBITS_MASK GENMASK(11, 8)
70 #define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
71 #define QSPI_MR_DLYBCT_MASK GENMASK(23, 16)
72 #define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK)
73 #define QSPI_MR_DLYCS_MASK GENMASK(31, 24)
74 #define QSPI_MR_DLYCS(n) (((n) << 24) & QSPI_MR_DLYCS_MASK)
75
76 /* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */
77 #define QSPI_SR_RDRF BIT(0)
78 #define QSPI_SR_TDRE BIT(1)
79 #define QSPI_SR_TXEMPTY BIT(2)
80 #define QSPI_SR_OVRES BIT(3)
81 #define QSPI_SR_CSR BIT(8)
82 #define QSPI_SR_CSS BIT(9)
83 #define QSPI_SR_INSTRE BIT(10)
84 #define QSPI_SR_QSPIENS BIT(24)
85
86 #define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE | QSPI_SR_CSR)
87
88 /* Bitfields in QSPI_SCR (Serial Clock Register) */
89 #define QSPI_SCR_CPOL BIT(0)
90 #define QSPI_SCR_CPHA BIT(1)
91 #define QSPI_SCR_SCBR_MASK GENMASK(15, 8)
92 #define QSPI_SCR_SCBR(n) (((n) << 8) & QSPI_SCR_SCBR_MASK)
93 #define QSPI_SCR_DLYBS_MASK GENMASK(23, 16)
94 #define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK)
95
96 /* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */
97 #define QSPI_ICR_INST_MASK GENMASK(7, 0)
98 #define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK)
99 #define QSPI_ICR_OPT_MASK GENMASK(23, 16)
100 #define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK)
101
102 /* Bitfields in QSPI_IFR (Instruction Frame Register) */
103 #define QSPI_IFR_WIDTH_MASK GENMASK(2, 0)
104 #define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0 << 0)
105 #define QSPI_IFR_WIDTH_DUAL_OUTPUT (1 << 0)
106 #define QSPI_IFR_WIDTH_QUAD_OUTPUT (2 << 0)
107 #define QSPI_IFR_WIDTH_DUAL_IO (3 << 0)
108 #define QSPI_IFR_WIDTH_QUAD_IO (4 << 0)
109 #define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0)
110 #define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0)
111 #define QSPI_IFR_INSTEN BIT(4)
112 #define QSPI_IFR_ADDREN BIT(5)
113 #define QSPI_IFR_OPTEN BIT(6)
114 #define QSPI_IFR_DATAEN BIT(7)
115 #define QSPI_IFR_OPTL_MASK GENMASK(9, 8)
116 #define QSPI_IFR_OPTL_1BIT (0 << 8)
117 #define QSPI_IFR_OPTL_2BIT (1 << 8)
118 #define QSPI_IFR_OPTL_4BIT (2 << 8)
119 #define QSPI_IFR_OPTL_8BIT (3 << 8)
120 #define QSPI_IFR_ADDRL BIT(10)
121 #define QSPI_IFR_TFRTYP_MEM BIT(12)
122 #define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13)
123 #define QSPI_IFR_CRM BIT(14)
124 #define QSPI_IFR_NBDUM_MASK GENMASK(20, 16)
125 #define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK)
126 #define QSPI_IFR_APBTFRTYP_READ BIT(24) /* Defined in SAM9X60 */
127
128 /* Bitfields in QSPI_SMR (Scrambling Mode Register) */
129 #define QSPI_SMR_SCREN BIT(0)
130 #define QSPI_SMR_RVDIS BIT(1)
131
132 /* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
133 #define QSPI_WPMR_WPEN BIT(0)
134 #define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8)
135 #define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
136
137 /* Bitfields in QSPI_WPSR (Write Protection Status Register) */
138 #define QSPI_WPSR_WPVS BIT(0)
139 #define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8)
140 #define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC)
141
142 struct atmel_qspi_caps {
143 bool has_qspick;
144 bool has_ricr;
145 };
146
147 struct atmel_qspi {
148 void __iomem *regs;
149 void __iomem *mem;
150 resource_size_t mmap_size;
151 const struct atmel_qspi_caps *caps;
152 struct udevice *dev;
153 ulong bus_clk_rate;
154 u32 mr;
155 };
156
157 struct atmel_qspi_mode {
158 u8 cmd_buswidth;
159 u8 addr_buswidth;
160 u8 data_buswidth;
161 u32 config;
162 };
163
164 static const struct atmel_qspi_mode atmel_qspi_modes[] = {
165 { 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
166 { 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
167 { 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
168 { 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
169 { 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
170 { 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
171 { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
172 };
173
174 #ifdef VERBOSE_DEBUG
atmel_qspi_reg_name(u32 offset,char * tmp,size_t sz)175 static const char *atmel_qspi_reg_name(u32 offset, char *tmp, size_t sz)
176 {
177 switch (offset) {
178 case QSPI_CR:
179 return "CR";
180 case QSPI_MR:
181 return "MR";
182 case QSPI_RD:
183 return "MR";
184 case QSPI_TD:
185 return "TD";
186 case QSPI_SR:
187 return "SR";
188 case QSPI_IER:
189 return "IER";
190 case QSPI_IDR:
191 return "IDR";
192 case QSPI_IMR:
193 return "IMR";
194 case QSPI_SCR:
195 return "SCR";
196 case QSPI_IAR:
197 return "IAR";
198 case QSPI_ICR:
199 return "ICR/WICR";
200 case QSPI_IFR:
201 return "IFR";
202 case QSPI_RICR:
203 return "RICR";
204 case QSPI_SMR:
205 return "SMR";
206 case QSPI_SKR:
207 return "SKR";
208 case QSPI_WPMR:
209 return "WPMR";
210 case QSPI_WPSR:
211 return "WPSR";
212 case QSPI_VERSION:
213 return "VERSION";
214 default:
215 snprintf(tmp, sz, "0x%02x", offset);
216 break;
217 }
218
219 return tmp;
220 }
221 #endif /* VERBOSE_DEBUG */
222
atmel_qspi_read(struct atmel_qspi * aq,u32 offset)223 static u32 atmel_qspi_read(struct atmel_qspi *aq, u32 offset)
224 {
225 u32 value = readl(aq->regs + offset);
226
227 #ifdef VERBOSE_DEBUG
228 char tmp[16];
229
230 dev_vdbg(aq->dev, "read 0x%08x from %s\n", value,
231 atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
232 #endif /* VERBOSE_DEBUG */
233
234 return value;
235 }
236
atmel_qspi_write(u32 value,struct atmel_qspi * aq,u32 offset)237 static void atmel_qspi_write(u32 value, struct atmel_qspi *aq, u32 offset)
238 {
239 #ifdef VERBOSE_DEBUG
240 char tmp[16];
241
242 dev_vdbg(aq->dev, "write 0x%08x into %s\n", value,
243 atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
244 #endif /* VERBOSE_DEBUG */
245
246 writel(value, aq->regs + offset);
247 }
248
atmel_qspi_is_compatible(const struct spi_mem_op * op,const struct atmel_qspi_mode * mode)249 static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
250 const struct atmel_qspi_mode *mode)
251 {
252 if (op->cmd.buswidth != mode->cmd_buswidth)
253 return false;
254
255 if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
256 return false;
257
258 if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
259 return false;
260
261 return true;
262 }
263
atmel_qspi_find_mode(const struct spi_mem_op * op)264 static int atmel_qspi_find_mode(const struct spi_mem_op *op)
265 {
266 u32 i;
267
268 for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++)
269 if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))
270 return i;
271
272 return -ENOTSUPP;
273 }
274
atmel_qspi_supports_op(struct spi_slave * slave,const struct spi_mem_op * op)275 static bool atmel_qspi_supports_op(struct spi_slave *slave,
276 const struct spi_mem_op *op)
277 {
278 if (atmel_qspi_find_mode(op) < 0)
279 return false;
280
281 /* special case not supported by hardware */
282 if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
283 op->dummy.nbytes == 0)
284 return false;
285
286 return true;
287 }
288
atmel_qspi_set_cfg(struct atmel_qspi * aq,const struct spi_mem_op * op,u32 * offset)289 static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
290 const struct spi_mem_op *op, u32 *offset)
291 {
292 u32 iar, icr, ifr;
293 u32 dummy_cycles = 0;
294 int mode;
295
296 iar = 0;
297 icr = QSPI_ICR_INST(op->cmd.opcode);
298 ifr = QSPI_IFR_INSTEN;
299
300 mode = atmel_qspi_find_mode(op);
301 if (mode < 0)
302 return mode;
303 ifr |= atmel_qspi_modes[mode].config;
304
305 if (op->dummy.buswidth && op->dummy.nbytes)
306 dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
307
308 /*
309 * The controller allows 24 and 32-bit addressing while NAND-flash
310 * requires 16-bit long. Handling 8-bit long addresses is done using
311 * the option field. For the 16-bit addresses, the workaround depends
312 * of the number of requested dummy bits. If there are 8 or more dummy
313 * cycles, the address is shifted and sent with the first dummy byte.
314 * Otherwise opcode is disabled and the first byte of the address
315 * contains the command opcode (works only if the opcode and address
316 * use the same buswidth). The limitation is when the 16-bit address is
317 * used without enough dummy cycles and the opcode is using a different
318 * buswidth than the address.
319 */
320 if (op->addr.buswidth) {
321 switch (op->addr.nbytes) {
322 case 0:
323 break;
324 case 1:
325 ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT;
326 icr |= QSPI_ICR_OPT(op->addr.val & 0xff);
327 break;
328 case 2:
329 if (dummy_cycles < 8 / op->addr.buswidth) {
330 ifr &= ~QSPI_IFR_INSTEN;
331 ifr |= QSPI_IFR_ADDREN;
332 iar = (op->cmd.opcode << 16) |
333 (op->addr.val & 0xffff);
334 } else {
335 ifr |= QSPI_IFR_ADDREN;
336 iar = (op->addr.val << 8) & 0xffffff;
337 dummy_cycles -= 8 / op->addr.buswidth;
338 }
339 break;
340 case 3:
341 ifr |= QSPI_IFR_ADDREN;
342 iar = op->addr.val & 0xffffff;
343 break;
344 case 4:
345 ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL;
346 iar = op->addr.val & 0x7ffffff;
347 break;
348 default:
349 return -ENOTSUPP;
350 }
351 }
352
353 /* offset of the data access in the QSPI memory space */
354 *offset = iar;
355
356 /* Set number of dummy cycles */
357 if (dummy_cycles)
358 ifr |= QSPI_IFR_NBDUM(dummy_cycles);
359
360 /* Set data enable */
361 if (op->data.nbytes)
362 ifr |= QSPI_IFR_DATAEN;
363
364 /*
365 * If the QSPI controller is set in regular SPI mode, set it in
366 * Serial Memory Mode (SMM).
367 */
368 if (aq->mr != QSPI_MR_SMM) {
369 atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
370 aq->mr = QSPI_MR_SMM;
371 }
372
373 /* Clear pending interrupts */
374 (void)atmel_qspi_read(aq, QSPI_SR);
375
376 if (aq->caps->has_ricr) {
377 if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
378 ifr |= QSPI_IFR_APBTFRTYP_READ;
379
380 /* Set QSPI Instruction Frame registers */
381 atmel_qspi_write(iar, aq, QSPI_IAR);
382 if (op->data.dir == SPI_MEM_DATA_IN)
383 atmel_qspi_write(icr, aq, QSPI_RICR);
384 else
385 atmel_qspi_write(icr, aq, QSPI_WICR);
386 atmel_qspi_write(ifr, aq, QSPI_IFR);
387 } else {
388 if (op->data.dir == SPI_MEM_DATA_OUT)
389 ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
390
391 /* Set QSPI Instruction Frame registers */
392 atmel_qspi_write(iar, aq, QSPI_IAR);
393 atmel_qspi_write(icr, aq, QSPI_ICR);
394 atmel_qspi_write(ifr, aq, QSPI_IFR);
395 }
396
397 return 0;
398 }
399
atmel_qspi_exec_op(struct spi_slave * slave,const struct spi_mem_op * op)400 static int atmel_qspi_exec_op(struct spi_slave *slave,
401 const struct spi_mem_op *op)
402 {
403 struct atmel_qspi *aq = dev_get_priv(slave->dev->parent);
404 u32 sr, imr, offset;
405 int err;
406
407 /*
408 * Check if the address exceeds the MMIO window size. An improvement
409 * would be to add support for regular SPI mode and fall back to it
410 * when the flash memories overrun the controller's memory space.
411 */
412 if (op->addr.val + op->data.nbytes > aq->mmap_size)
413 return -ENOTSUPP;
414
415 err = atmel_qspi_set_cfg(aq, op, &offset);
416 if (err)
417 return err;
418
419 /* Skip to the final steps if there is no data */
420 if (op->data.nbytes) {
421 /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
422 (void)atmel_qspi_read(aq, QSPI_IFR);
423
424 /* Send/Receive data */
425 if (op->data.dir == SPI_MEM_DATA_IN)
426 memcpy_fromio(op->data.buf.in, aq->mem + offset,
427 op->data.nbytes);
428 else
429 memcpy_toio(aq->mem + offset, op->data.buf.out,
430 op->data.nbytes);
431
432 /* Release the chip-select */
433 atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR);
434 }
435
436 /* Poll INSTruction End and Chip Select Rise flags. */
437 imr = QSPI_SR_INSTRE | QSPI_SR_CSR;
438 return readl_poll_timeout(aq->regs + QSPI_SR, sr, (sr & imr) == imr,
439 1000000);
440 }
441
atmel_qspi_set_speed(struct udevice * bus,uint hz)442 static int atmel_qspi_set_speed(struct udevice *bus, uint hz)
443 {
444 struct atmel_qspi *aq = dev_get_priv(bus);
445 u32 scr, scbr, mask, new_value;
446
447 /* Compute the QSPI baudrate */
448 scbr = DIV_ROUND_UP(aq->bus_clk_rate, hz);
449 if (scbr > 0)
450 scbr--;
451
452 new_value = QSPI_SCR_SCBR(scbr);
453 mask = QSPI_SCR_SCBR_MASK;
454
455 scr = atmel_qspi_read(aq, QSPI_SCR);
456 if ((scr & mask) == new_value)
457 return 0;
458
459 scr = (scr & ~mask) | new_value;
460 atmel_qspi_write(scr, aq, QSPI_SCR);
461
462 return 0;
463 }
464
atmel_qspi_set_mode(struct udevice * bus,uint mode)465 static int atmel_qspi_set_mode(struct udevice *bus, uint mode)
466 {
467 struct atmel_qspi *aq = dev_get_priv(bus);
468 u32 scr, mask, new_value = 0;
469
470 if (mode & SPI_CPOL)
471 new_value = QSPI_SCR_CPOL;
472 if (mode & SPI_CPHA)
473 new_value = QSPI_SCR_CPHA;
474
475 mask = QSPI_SCR_CPOL | QSPI_SCR_CPHA;
476
477 scr = atmel_qspi_read(aq, QSPI_SCR);
478 if ((scr & mask) == new_value)
479 return 0;
480
481 scr = (scr & ~mask) | new_value;
482 atmel_qspi_write(scr, aq, QSPI_SCR);
483
484 return 0;
485 }
486
atmel_qspi_enable_clk(struct udevice * dev)487 static int atmel_qspi_enable_clk(struct udevice *dev)
488 {
489 struct atmel_qspi *aq = dev_get_priv(dev);
490 struct clk pclk, qspick;
491 int ret;
492
493 ret = clk_get_by_name(dev, "pclk", &pclk);
494 if (ret)
495 ret = clk_get_by_index(dev, 0, &pclk);
496
497 if (ret) {
498 dev_err(dev, "Missing QSPI peripheral clock\n");
499 return ret;
500 }
501
502 ret = clk_enable(&pclk);
503 if (ret) {
504 dev_err(dev, "Failed to enable QSPI peripheral clock\n");
505 goto free_pclk;
506 }
507
508 if (aq->caps->has_qspick) {
509 /* Get the QSPI system clock */
510 ret = clk_get_by_name(dev, "qspick", &qspick);
511 if (ret) {
512 dev_err(dev, "Missing QSPI peripheral clock\n");
513 goto free_pclk;
514 }
515
516 ret = clk_enable(&qspick);
517 if (ret)
518 dev_err(dev, "Failed to enable QSPI system clock\n");
519 clk_free(&qspick);
520 }
521
522 aq->bus_clk_rate = clk_get_rate(&pclk);
523 if (!aq->bus_clk_rate)
524 ret = -EINVAL;
525
526 free_pclk:
527 clk_free(&pclk);
528
529 return ret;
530 }
531
atmel_qspi_init(struct atmel_qspi * aq)532 static void atmel_qspi_init(struct atmel_qspi *aq)
533 {
534 /* Reset the QSPI controller */
535 atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR);
536
537 /* Set the QSPI controller by default in Serial Memory Mode */
538 atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
539 aq->mr = QSPI_MR_SMM;
540
541 /* Enable the QSPI controller */
542 atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);
543 }
544
atmel_qspi_probe(struct udevice * dev)545 static int atmel_qspi_probe(struct udevice *dev)
546 {
547 struct atmel_qspi *aq = dev_get_priv(dev);
548 struct resource res;
549 int ret;
550
551 aq->caps = (struct atmel_qspi_caps *)dev_get_driver_data(dev);
552 if (!aq->caps) {
553 dev_err(dev, "Could not retrieve QSPI caps\n");
554 return -EINVAL;
555 };
556
557 /* Map the registers */
558 ret = dev_read_resource_byname(dev, "qspi_base", &res);
559 if (ret) {
560 dev_err(dev, "missing registers\n");
561 return ret;
562 }
563
564 aq->regs = devm_ioremap(dev, res.start, resource_size(&res));
565 if (IS_ERR(aq->regs))
566 return PTR_ERR(aq->regs);
567
568 /* Map the AHB memory */
569 ret = dev_read_resource_byname(dev, "qspi_mmap", &res);
570 if (ret) {
571 dev_err(dev, "missing AHB memory\n");
572 return ret;
573 }
574
575 aq->mem = devm_ioremap(dev, res.start, resource_size(&res));
576 if (IS_ERR(aq->mem))
577 return PTR_ERR(aq->mem);
578
579 aq->mmap_size = resource_size(&res);
580
581 ret = atmel_qspi_enable_clk(dev);
582 if (ret)
583 return ret;
584
585 aq->dev = dev;
586
587 atmel_qspi_init(aq);
588
589 return 0;
590 }
591
592 static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
593 .supports_op = atmel_qspi_supports_op,
594 .exec_op = atmel_qspi_exec_op,
595 };
596
597 static const struct dm_spi_ops atmel_qspi_ops = {
598 .set_speed = atmel_qspi_set_speed,
599 .set_mode = atmel_qspi_set_mode,
600 .mem_ops = &atmel_qspi_mem_ops,
601 };
602
603 static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
604
605 static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
606 .has_qspick = true,
607 .has_ricr = true,
608 };
609
610 static const struct udevice_id atmel_qspi_ids[] = {
611 {
612 .compatible = "atmel,sama5d2-qspi",
613 .data = (ulong)&atmel_sama5d2_qspi_caps,
614 },
615 {
616 .compatible = "microchip,sam9x60-qspi",
617 .data = (ulong)&atmel_sam9x60_qspi_caps,
618 },
619 { /* sentinel */ }
620 };
621
622 U_BOOT_DRIVER(atmel_qspi) = {
623 .name = "atmel_qspi",
624 .id = UCLASS_SPI,
625 .of_match = atmel_qspi_ids,
626 .ops = &atmel_qspi_ops,
627 .priv_auto = sizeof(struct atmel_qspi),
628 .probe = atmel_qspi_probe,
629 };
630