1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2016 Rockchip Electronics Co., Ltd
4 */
5
6 #include <common.h>
7 #include <fdt_support.h>
8 #include <init.h>
9 #include <log.h>
10 #include <spl.h>
11 #include <spl_gpio.h>
12 #include <syscon.h>
13 #include <asm/armv8/mmu.h>
14 #include <asm/global_data.h>
15 #include <asm/io.h>
16 #include <asm/arch-rockchip/bootrom.h>
17 #include <asm/arch-rockchip/clock.h>
18 #include <asm/arch-rockchip/gpio.h>
19 #include <asm/arch-rockchip/grf_rk3399.h>
20 #include <asm/arch-rockchip/hardware.h>
21 #include <linux/bitops.h>
22 #include <power/regulator.h>
23
24 DECLARE_GLOBAL_DATA_PTR;
25
26 #define GRF_EMMCCORE_CON11 0xff77f02c
27 #define GRF_BASE 0xff770000
28
29 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
30 [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000",
31 [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000",
32 [BROM_BOOTSOURCE_SD] = "/mmc@fe320000",
33 };
34
35 static struct mm_region rk3399_mem_map[] = {
36 {
37 .virt = 0x0UL,
38 .phys = 0x0UL,
39 .size = 0xf8000000UL,
40 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
41 PTE_BLOCK_INNER_SHARE
42 }, {
43 .virt = 0xf8000000UL,
44 .phys = 0xf8000000UL,
45 .size = 0x08000000UL,
46 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
47 PTE_BLOCK_NON_SHARE |
48 PTE_BLOCK_PXN | PTE_BLOCK_UXN
49 }, {
50 /* List terminator */
51 0,
52 }
53 };
54
55 struct mm_region *mem_map = rk3399_mem_map;
56
57 #ifdef CONFIG_SPL_BUILD
58
59 #define TIMER_END_COUNT_L 0x00
60 #define TIMER_END_COUNT_H 0x04
61 #define TIMER_INIT_COUNT_L 0x10
62 #define TIMER_INIT_COUNT_H 0x14
63 #define TIMER_CONTROL_REG 0x1c
64
65 #define TIMER_EN 0x1
66 #define TIMER_FMODE BIT(0)
67 #define TIMER_RMODE BIT(1)
68
rockchip_stimer_init(void)69 void rockchip_stimer_init(void)
70 {
71 /* If Timer already enabled, don't re-init it */
72 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
73
74 if (reg & TIMER_EN)
75 return;
76
77 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_L);
78 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_H);
79 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_L);
80 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_H);
81 writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + \
82 TIMER_CONTROL_REG);
83 }
84 #endif
85
arch_cpu_init(void)86 int arch_cpu_init(void)
87 {
88
89 #ifdef CONFIG_SPL_BUILD
90 struct rk3399_pmusgrf_regs *sgrf;
91 struct rk3399_grf_regs *grf;
92
93 /*
94 * Disable DDR and SRAM security regions.
95 *
96 * As we are entered from the BootROM, the region from
97 * 0x0 through 0xfffff (i.e. the first MB of memory) will
98 * be protected. This will cause issues with the DW_MMC
99 * driver, which tries to DMA from/to the stack (likely)
100 * located in this range.
101 */
102 sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
103 rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
104 rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
105
106 /* eMMC clock generator: disable the clock multipilier */
107 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
108 rk_clrreg(&grf->emmccore_con[11], 0x0ff);
109 #endif
110
111 return 0;
112 }
113
114 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
board_debug_uart_init(void)115 void board_debug_uart_init(void)
116 {
117 #define GRF_BASE 0xff770000
118 #define GPIO0_BASE 0xff720000
119 #define PMUGRF_BASE 0xff320000
120 struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
121 #ifdef CONFIG_TARGET_CHROMEBOOK_BOB
122 struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
123 struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
124 #endif
125
126 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
127 /* Enable early UART0 on the RK3399 */
128 rk_clrsetreg(&grf->gpio2c_iomux,
129 GRF_GPIO2C0_SEL_MASK,
130 GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
131 rk_clrsetreg(&grf->gpio2c_iomux,
132 GRF_GPIO2C1_SEL_MASK,
133 GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
134 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1B0000)
135 /* Enable early UART3 on the RK3399 */
136 rk_clrsetreg(&grf->gpio3b_iomux,
137 GRF_GPIO3B6_SEL_MASK,
138 GRF_UART3_SIN << GRF_GPIO3B6_SEL_SHIFT);
139 rk_clrsetreg(&grf->gpio3b_iomux,
140 GRF_GPIO3B7_SEL_MASK,
141 GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT);
142 #else
143 # ifdef CONFIG_TARGET_CHROMEBOOK_BOB
144 rk_setreg(&grf->io_vsel, 1 << 0);
145
146 /*
147 * Let's enable these power rails here, we are already running the SPI
148 * Flash based code.
149 */
150 spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */
151 spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
152
153 spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */
154 spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL);
155 #endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
156
157 /* Enable early UART2 channel C on the RK3399 */
158 rk_clrsetreg(&grf->gpio4c_iomux,
159 GRF_GPIO4C3_SEL_MASK,
160 GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
161 rk_clrsetreg(&grf->gpio4c_iomux,
162 GRF_GPIO4C4_SEL_MASK,
163 GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
164 /* Set channel C as UART2 input */
165 rk_clrsetreg(&grf->soc_con7,
166 GRF_UART_DBG_SEL_MASK,
167 GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
168 #endif
169 }
170 #endif
171
172 #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
spl_decode_boot_device(u32 boot_device)173 const char *spl_decode_boot_device(u32 boot_device)
174 {
175 int i;
176 static const struct {
177 u32 boot_device;
178 const char *ofpath;
179 } spl_boot_devices_tbl[] = {
180 { BOOT_DEVICE_MMC1, "/mmc@fe320000" },
181 { BOOT_DEVICE_MMC2, "/sdhci@fe330000" },
182 { BOOT_DEVICE_SPI, "/spi@ff1d0000" },
183 };
184
185 for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i)
186 if (spl_boot_devices_tbl[i].boot_device == boot_device)
187 return spl_boot_devices_tbl[i].ofpath;
188
189 return NULL;
190 }
191
spl_perform_fixups(struct spl_image_info * spl_image)192 void spl_perform_fixups(struct spl_image_info *spl_image)
193 {
194 void *blob = spl_image->fdt_addr;
195 const char *boot_ofpath;
196 int chosen;
197
198 /*
199 * Inject the ofpath of the device the full U-Boot (or Linux in
200 * Falcon-mode) was booted from into the FDT, if a FDT has been
201 * loaded at the same time.
202 */
203 if (!blob)
204 return;
205
206 boot_ofpath = spl_decode_boot_device(spl_image->boot_device);
207 if (!boot_ofpath) {
208 pr_err("%s: could not map boot_device to ofpath\n", __func__);
209 return;
210 }
211
212 chosen = fdt_find_or_add_subnode(blob, 0, "chosen");
213 if (chosen < 0) {
214 pr_err("%s: could not find/create '/chosen'\n", __func__);
215 return;
216 }
217 fdt_setprop_string(blob, chosen,
218 "u-boot,spl-boot-device", boot_ofpath);
219 }
220
221 #if defined(SPL_GPIO_SUPPORT)
rk3399_force_power_on_reset(void)222 static void rk3399_force_power_on_reset(void)
223 {
224 ofnode node;
225 struct gpio_desc sysreset_gpio;
226
227 debug("%s: trying to force a power-on reset\n", __func__);
228
229 node = ofnode_path("/config");
230 if (!ofnode_valid(node)) {
231 debug("%s: no /config node?\n", __func__);
232 return;
233 }
234
235 if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0,
236 &sysreset_gpio, GPIOD_IS_OUT)) {
237 debug("%s: could not find a /config/sysreset-gpio\n", __func__);
238 return;
239 }
240
241 dm_gpio_set_value(&sysreset_gpio, 1);
242 }
243 #endif
244
led_setup(void)245 void __weak led_setup(void)
246 {
247 }
248
spl_board_init(void)249 void spl_board_init(void)
250 {
251 led_setup();
252
253 #if defined(SPL_GPIO_SUPPORT)
254 struct rockchip_cru *cru = rockchip_get_cru();
255
256 /*
257 * The RK3399 resets only 'almost all logic' (see also in the TRM
258 * "3.9.4 Global software reset"), when issuing a software reset.
259 * This may cause issues during boot-up for some configurations of
260 * the application software stack.
261 *
262 * To work around this, we test whether the last reset reason was
263 * a power-on reset and (if not) issue an overtemp-reset to reset
264 * the entire module.
265 *
266 * While this was previously fixed by modifying the various places
267 * that could generate a software reset (e.g. U-Boot's sysreset
268 * driver, the ATF or Linux), we now have it here to ensure that
269 * we no longer have to track this through the various components.
270 */
271 if (cru->glb_rst_st != 0)
272 rk3399_force_power_on_reset();
273 #endif
274
275 #if defined(SPL_DM_REGULATOR)
276 /*
277 * Turning the eMMC and SPI back on (if disabled via the Qseven
278 * BIOS_ENABLE) signal is done through a always-on regulator).
279 */
280 if (regulators_enable_boot_on(false))
281 debug("%s: Cannot enable boot on regulator\n", __func__);
282 #endif
283 }
284 #endif
285