1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2011, Marvell Semiconductor Inc.
4 * Lei Wen <leiwen@marvell.com>
5 *
6 * Back ported to the 8xx platform (from the 8260 platform) by
7 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
8 */
9
10 #include <common.h>
11 #include <command.h>
12 #include <config.h>
13 #include <cpu_func.h>
14 #include <net.h>
15 #include <malloc.h>
16 #include <asm/byteorder.h>
17 #include <asm/cache.h>
18 #include <linux/delay.h>
19 #include <linux/errno.h>
20 #include <asm/io.h>
21 #include <asm/unaligned.h>
22 #include <linux/types.h>
23 #include <linux/usb/ch9.h>
24 #include <linux/usb/gadget.h>
25 #include <usb/ci_udc.h>
26 #include "../host/ehci.h"
27 #include "ci_udc.h"
28
29 /*
30 * Check if the system has too long cachelines. If the cachelines are
31 * longer then 128b, the driver will not be able flush/invalidate data
32 * cache over separate QH entries. We use 128b because one QH entry is
33 * 64b long and there are always two QH list entries for each endpoint.
34 */
35 #if ARCH_DMA_MINALIGN > 128
36 #error This driver can not work on systems with caches longer than 128b
37 #endif
38
39 /*
40 * Every QTD must be individually aligned, since we can program any
41 * QTD's address into HW. Cache flushing requires ARCH_DMA_MINALIGN,
42 * and the USB HW requires 32-byte alignment. Align to both:
43 */
44 #define ILIST_ALIGN roundup(ARCH_DMA_MINALIGN, 32)
45 /* Each QTD is this size */
46 #define ILIST_ENT_RAW_SZ sizeof(struct ept_queue_item)
47 /*
48 * Align the size of the QTD too, so we can add this value to each
49 * QTD's address to get another aligned address.
50 */
51 #define ILIST_ENT_SZ roundup(ILIST_ENT_RAW_SZ, ILIST_ALIGN)
52 /* For each endpoint, we need 2 QTDs, one for each of IN and OUT */
53 #define ILIST_SZ (NUM_ENDPOINTS * 2 * ILIST_ENT_SZ)
54
55 #define EP_MAX_LENGTH_TRANSFER 0x4000
56
57 #ifndef DEBUG
58 #define DBG(x...) do {} while (0)
59 #else
60 #define DBG(x...) printf(x)
reqname(unsigned r)61 static const char *reqname(unsigned r)
62 {
63 switch (r) {
64 case USB_REQ_GET_STATUS: return "GET_STATUS";
65 case USB_REQ_CLEAR_FEATURE: return "CLEAR_FEATURE";
66 case USB_REQ_SET_FEATURE: return "SET_FEATURE";
67 case USB_REQ_SET_ADDRESS: return "SET_ADDRESS";
68 case USB_REQ_GET_DESCRIPTOR: return "GET_DESCRIPTOR";
69 case USB_REQ_SET_DESCRIPTOR: return "SET_DESCRIPTOR";
70 case USB_REQ_GET_CONFIGURATION: return "GET_CONFIGURATION";
71 case USB_REQ_SET_CONFIGURATION: return "SET_CONFIGURATION";
72 case USB_REQ_GET_INTERFACE: return "GET_INTERFACE";
73 case USB_REQ_SET_INTERFACE: return "SET_INTERFACE";
74 default: return "*UNKNOWN*";
75 }
76 }
77 #endif
78
79 static struct usb_endpoint_descriptor ep0_desc = {
80 .bLength = sizeof(struct usb_endpoint_descriptor),
81 .bDescriptorType = USB_DT_ENDPOINT,
82 .bEndpointAddress = USB_DIR_IN,
83 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
84 };
85
86 static int ci_pullup(struct usb_gadget *gadget, int is_on);
87 static int ci_ep_enable(struct usb_ep *ep,
88 const struct usb_endpoint_descriptor *desc);
89 static int ci_ep_disable(struct usb_ep *ep);
90 static int ci_ep_queue(struct usb_ep *ep,
91 struct usb_request *req, gfp_t gfp_flags);
92 static int ci_ep_dequeue(struct usb_ep *ep, struct usb_request *req);
93 static struct usb_request *
94 ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags);
95 static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *_req);
96
97 static struct usb_gadget_ops ci_udc_ops = {
98 .pullup = ci_pullup,
99 };
100
101 static struct usb_ep_ops ci_ep_ops = {
102 .enable = ci_ep_enable,
103 .disable = ci_ep_disable,
104 .queue = ci_ep_queue,
105 .dequeue = ci_ep_dequeue,
106 .alloc_request = ci_ep_alloc_request,
107 .free_request = ci_ep_free_request,
108 };
109
ci_init_after_reset(struct ehci_ctrl * ctrl)110 __weak void ci_init_after_reset(struct ehci_ctrl *ctrl)
111 {
112 }
113
114 /* Init values for USB endpoints. */
115 static const struct usb_ep ci_ep_init[5] = {
116 [0] = { /* EP 0 */
117 .maxpacket = 64,
118 .name = "ep0",
119 .ops = &ci_ep_ops,
120 },
121 [1] = {
122 .maxpacket = 512,
123 .name = "ep1in-bulk",
124 .ops = &ci_ep_ops,
125 },
126 [2] = {
127 .maxpacket = 512,
128 .name = "ep2out-bulk",
129 .ops = &ci_ep_ops,
130 },
131 [3] = {
132 .maxpacket = 512,
133 .name = "ep3in-int",
134 .ops = &ci_ep_ops,
135 },
136 [4] = {
137 .maxpacket = 512,
138 .name = "ep-",
139 .ops = &ci_ep_ops,
140 },
141 };
142
143 static struct ci_drv controller = {
144 .gadget = {
145 .name = "ci_udc",
146 .ops = &ci_udc_ops,
147 .is_dualspeed = 1,
148 .max_speed = USB_SPEED_HIGH,
149 },
150 };
151
152 /**
153 * ci_get_qh() - return queue head for endpoint
154 * @ep_num: Endpoint number
155 * @dir_in: Direction of the endpoint (IN = 1, OUT = 0)
156 *
157 * This function returns the QH associated with particular endpoint
158 * and it's direction.
159 */
ci_get_qh(int ep_num,int dir_in)160 static struct ept_queue_head *ci_get_qh(int ep_num, int dir_in)
161 {
162 return &controller.epts[(ep_num * 2) + dir_in];
163 }
164
165 /**
166 * ci_get_qtd() - return queue item for endpoint
167 * @ep_num: Endpoint number
168 * @dir_in: Direction of the endpoint (IN = 1, OUT = 0)
169 *
170 * This function returns the QH associated with particular endpoint
171 * and it's direction.
172 */
ci_get_qtd(int ep_num,int dir_in)173 static struct ept_queue_item *ci_get_qtd(int ep_num, int dir_in)
174 {
175 int index = (ep_num * 2) + dir_in;
176 uint8_t *imem = controller.items_mem + (index * ILIST_ENT_SZ);
177 return (struct ept_queue_item *)imem;
178 }
179
180 /**
181 * ci_flush_qh - flush cache over queue head
182 * @ep_num: Endpoint number
183 *
184 * This function flushes cache over QH for particular endpoint.
185 */
ci_flush_qh(int ep_num)186 static void ci_flush_qh(int ep_num)
187 {
188 struct ept_queue_head *head = ci_get_qh(ep_num, 0);
189 const unsigned long start = (unsigned long)head;
190 const unsigned long end = start + 2 * sizeof(*head);
191
192 flush_dcache_range(start, end);
193 }
194
195 /**
196 * ci_invalidate_qh - invalidate cache over queue head
197 * @ep_num: Endpoint number
198 *
199 * This function invalidates cache over QH for particular endpoint.
200 */
ci_invalidate_qh(int ep_num)201 static void ci_invalidate_qh(int ep_num)
202 {
203 struct ept_queue_head *head = ci_get_qh(ep_num, 0);
204 unsigned long start = (unsigned long)head;
205 unsigned long end = start + 2 * sizeof(*head);
206
207 invalidate_dcache_range(start, end);
208 }
209
210 /**
211 * ci_flush_qtd - flush cache over queue item
212 * @ep_num: Endpoint number
213 *
214 * This function flushes cache over qTD pair for particular endpoint.
215 */
ci_flush_qtd(int ep_num)216 static void ci_flush_qtd(int ep_num)
217 {
218 struct ept_queue_item *item = ci_get_qtd(ep_num, 0);
219 const unsigned long start = (unsigned long)item;
220 const unsigned long end = start + 2 * ILIST_ENT_SZ;
221
222 flush_dcache_range(start, end);
223 }
224
225 /**
226 * ci_flush_td - flush cache over queue item
227 * @td: td pointer
228 *
229 * This function flushes cache for particular transfer descriptor.
230 */
ci_flush_td(struct ept_queue_item * td)231 static void ci_flush_td(struct ept_queue_item *td)
232 {
233 const unsigned long start = (unsigned long)td;
234 const unsigned long end = (unsigned long)td + ILIST_ENT_SZ;
235 flush_dcache_range(start, end);
236 }
237
238 /**
239 * ci_invalidate_qtd - invalidate cache over queue item
240 * @ep_num: Endpoint number
241 *
242 * This function invalidates cache over qTD pair for particular endpoint.
243 */
ci_invalidate_qtd(int ep_num)244 static void ci_invalidate_qtd(int ep_num)
245 {
246 struct ept_queue_item *item = ci_get_qtd(ep_num, 0);
247 const unsigned long start = (unsigned long)item;
248 const unsigned long end = start + 2 * ILIST_ENT_SZ;
249
250 invalidate_dcache_range(start, end);
251 }
252
253 /**
254 * ci_invalidate_td - invalidate cache over queue item
255 * @td: td pointer
256 *
257 * This function invalidates cache for particular transfer descriptor.
258 */
ci_invalidate_td(struct ept_queue_item * td)259 static void ci_invalidate_td(struct ept_queue_item *td)
260 {
261 const unsigned long start = (unsigned long)td;
262 const unsigned long end = start + ILIST_ENT_SZ;
263 invalidate_dcache_range(start, end);
264 }
265
266 static struct usb_request *
ci_ep_alloc_request(struct usb_ep * ep,unsigned int gfp_flags)267 ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags)
268 {
269 struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
270 int num = -1;
271 struct ci_req *ci_req;
272
273 if (ci_ep->desc)
274 num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
275
276 if (num == 0 && controller.ep0_req)
277 return &controller.ep0_req->req;
278
279 ci_req = calloc(1, sizeof(*ci_req));
280 if (!ci_req)
281 return NULL;
282
283 INIT_LIST_HEAD(&ci_req->queue);
284
285 if (num == 0)
286 controller.ep0_req = ci_req;
287
288 return &ci_req->req;
289 }
290
ci_ep_free_request(struct usb_ep * ep,struct usb_request * req)291 static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *req)
292 {
293 struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
294 struct ci_req *ci_req = container_of(req, struct ci_req, req);
295 int num = -1;
296
297 if (ci_ep->desc)
298 num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
299
300 if (num == 0) {
301 if (!controller.ep0_req)
302 return;
303 controller.ep0_req = 0;
304 }
305
306 if (ci_req->b_buf)
307 free(ci_req->b_buf);
308 free(ci_req);
309 }
310
ep_enable(int num,int in,int maxpacket)311 static void ep_enable(int num, int in, int maxpacket)
312 {
313 struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
314 unsigned n;
315
316 n = readl(&udc->epctrl[num]);
317 if (in)
318 n |= (CTRL_TXE | CTRL_TXR | CTRL_TXT_BULK);
319 else
320 n |= (CTRL_RXE | CTRL_RXR | CTRL_RXT_BULK);
321
322 if (num != 0) {
323 struct ept_queue_head *head = ci_get_qh(num, in);
324
325 head->config = CONFIG_MAX_PKT(maxpacket) | CONFIG_ZLT;
326 ci_flush_qh(num);
327 }
328 writel(n, &udc->epctrl[num]);
329 }
330
ci_ep_enable(struct usb_ep * ep,const struct usb_endpoint_descriptor * desc)331 static int ci_ep_enable(struct usb_ep *ep,
332 const struct usb_endpoint_descriptor *desc)
333 {
334 struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
335 int num, in;
336 num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
337 in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
338 ci_ep->desc = desc;
339 ep->desc = desc;
340
341 if (num) {
342 int max = get_unaligned_le16(&desc->wMaxPacketSize);
343
344 if ((max > 64) && (controller.gadget.speed == USB_SPEED_FULL))
345 max = 64;
346 if (ep->maxpacket != max) {
347 DBG("%s: from %d to %d\n", __func__,
348 ep->maxpacket, max);
349 ep->maxpacket = max;
350 }
351 }
352 ep_enable(num, in, ep->maxpacket);
353 DBG("%s: num=%d maxpacket=%d\n", __func__, num, ep->maxpacket);
354 return 0;
355 }
356
ci_ep_disable(struct usb_ep * ep)357 static int ci_ep_disable(struct usb_ep *ep)
358 {
359 struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
360
361 ci_ep->desc = NULL;
362 ep->desc = NULL;
363 return 0;
364 }
365
ci_bounce(struct ci_req * ci_req,int in)366 static int ci_bounce(struct ci_req *ci_req, int in)
367 {
368 struct usb_request *req = &ci_req->req;
369 unsigned long addr = (unsigned long)req->buf;
370 unsigned long hwaddr;
371 uint32_t aligned_used_len;
372
373 /* Input buffer address is not aligned. */
374 if (addr & (ARCH_DMA_MINALIGN - 1))
375 goto align;
376
377 /* Input buffer length is not aligned. */
378 if (req->length & (ARCH_DMA_MINALIGN - 1))
379 goto align;
380
381 /* The buffer is well aligned, only flush cache. */
382 ci_req->hw_len = req->length;
383 ci_req->hw_buf = req->buf;
384 goto flush;
385
386 align:
387 if (ci_req->b_buf && req->length > ci_req->b_len) {
388 free(ci_req->b_buf);
389 ci_req->b_buf = 0;
390 }
391 if (!ci_req->b_buf) {
392 ci_req->b_len = roundup(req->length, ARCH_DMA_MINALIGN);
393 ci_req->b_buf = memalign(ARCH_DMA_MINALIGN, ci_req->b_len);
394 if (!ci_req->b_buf)
395 return -ENOMEM;
396 }
397 ci_req->hw_len = ci_req->b_len;
398 ci_req->hw_buf = ci_req->b_buf;
399
400 if (in)
401 memcpy(ci_req->hw_buf, req->buf, req->length);
402
403 flush:
404 hwaddr = (unsigned long)ci_req->hw_buf;
405 aligned_used_len = roundup(req->length, ARCH_DMA_MINALIGN);
406 flush_dcache_range(hwaddr, hwaddr + aligned_used_len);
407
408 return 0;
409 }
410
ci_debounce(struct ci_req * ci_req,int in)411 static void ci_debounce(struct ci_req *ci_req, int in)
412 {
413 struct usb_request *req = &ci_req->req;
414 unsigned long addr = (unsigned long)req->buf;
415 unsigned long hwaddr = (unsigned long)ci_req->hw_buf;
416 uint32_t aligned_used_len;
417
418 if (in)
419 return;
420
421 aligned_used_len = roundup(req->actual, ARCH_DMA_MINALIGN);
422 invalidate_dcache_range(hwaddr, hwaddr + aligned_used_len);
423
424 if (addr == hwaddr)
425 return; /* not a bounce */
426
427 memcpy(req->buf, ci_req->hw_buf, req->actual);
428 }
429
ci_ep_submit_next_request(struct ci_ep * ci_ep)430 static void ci_ep_submit_next_request(struct ci_ep *ci_ep)
431 {
432 struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
433 struct ept_queue_item *item;
434 struct ept_queue_head *head;
435 int bit, num, len, in;
436 struct ci_req *ci_req;
437 u8 *buf;
438 uint32_t len_left, len_this_dtd;
439 struct ept_queue_item *dtd, *qtd;
440
441 ci_ep->req_primed = true;
442
443 num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
444 in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
445 item = ci_get_qtd(num, in);
446 head = ci_get_qh(num, in);
447
448 ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue);
449 len = ci_req->req.length;
450
451 head->next = (unsigned long)item;
452 head->info = 0;
453
454 ci_req->dtd_count = 0;
455 buf = ci_req->hw_buf;
456 len_left = len;
457 dtd = item;
458
459 do {
460 len_this_dtd = min(len_left, (unsigned)EP_MAX_LENGTH_TRANSFER);
461
462 dtd->info = INFO_BYTES(len_this_dtd) | INFO_ACTIVE;
463 dtd->page0 = (unsigned long)buf;
464 dtd->page1 = ((unsigned long)buf & 0xfffff000) + 0x1000;
465 dtd->page2 = ((unsigned long)buf & 0xfffff000) + 0x2000;
466 dtd->page3 = ((unsigned long)buf & 0xfffff000) + 0x3000;
467 dtd->page4 = ((unsigned long)buf & 0xfffff000) + 0x4000;
468
469 len_left -= len_this_dtd;
470 buf += len_this_dtd;
471
472 if (len_left) {
473 qtd = (struct ept_queue_item *)
474 memalign(ILIST_ALIGN, ILIST_ENT_SZ);
475 dtd->next = (unsigned long)qtd;
476 dtd = qtd;
477 memset(dtd, 0, ILIST_ENT_SZ);
478 }
479
480 ci_req->dtd_count++;
481 } while (len_left);
482
483 item = dtd;
484 /*
485 * When sending the data for an IN transaction, the attached host
486 * knows that all data for the IN is sent when one of the following
487 * occurs:
488 * a) A zero-length packet is transmitted.
489 * b) A packet with length that isn't an exact multiple of the ep's
490 * maxpacket is transmitted.
491 * c) Enough data is sent to exactly fill the host's maximum expected
492 * IN transaction size.
493 *
494 * One of these conditions MUST apply at the end of an IN transaction,
495 * or the transaction will not be considered complete by the host. If
496 * none of (a)..(c) already applies, then we must force (a) to apply
497 * by explicitly sending an extra zero-length packet.
498 */
499 /* IN !a !b !c */
500 if (in && len && !(len % ci_ep->ep.maxpacket) && ci_req->req.zero) {
501 /*
502 * Each endpoint has 2 items allocated, even though typically
503 * only 1 is used at a time since either an IN or an OUT but
504 * not both is queued. For an IN transaction, item currently
505 * points at the second of these items, so we know that we
506 * can use the other to transmit the extra zero-length packet.
507 */
508 struct ept_queue_item *other_item = ci_get_qtd(num, 0);
509 item->next = (unsigned long)other_item;
510 item = other_item;
511 item->info = INFO_ACTIVE;
512 }
513
514 item->next = TERMINATE;
515 item->info |= INFO_IOC;
516
517 ci_flush_qtd(num);
518
519 item = (struct ept_queue_item *)(unsigned long)head->next;
520 while (item->next != TERMINATE) {
521 ci_flush_td((struct ept_queue_item *)(unsigned long)item->next);
522 item = (struct ept_queue_item *)(unsigned long)item->next;
523 }
524
525 DBG("ept%d %s queue len %x, req %p, buffer %p\n",
526 num, in ? "in" : "out", len, ci_req, ci_req->hw_buf);
527 ci_flush_qh(num);
528
529 if (in)
530 bit = EPT_TX(num);
531 else
532 bit = EPT_RX(num);
533
534 writel(bit, &udc->epprime);
535 }
536
ci_ep_dequeue(struct usb_ep * _ep,struct usb_request * _req)537 static int ci_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
538 {
539 struct ci_ep *ci_ep = container_of(_ep, struct ci_ep, ep);
540 struct ci_req *ci_req;
541
542 list_for_each_entry(ci_req, &ci_ep->queue, queue) {
543 if (&ci_req->req == _req)
544 break;
545 }
546
547 if (&ci_req->req != _req)
548 return -EINVAL;
549
550 list_del_init(&ci_req->queue);
551
552 if (ci_req->req.status == -EINPROGRESS) {
553 ci_req->req.status = -ECONNRESET;
554 if (ci_req->req.complete)
555 ci_req->req.complete(_ep, _req);
556 }
557
558 return 0;
559 }
560
ci_ep_queue(struct usb_ep * ep,struct usb_request * req,gfp_t gfp_flags)561 static int ci_ep_queue(struct usb_ep *ep,
562 struct usb_request *req, gfp_t gfp_flags)
563 {
564 struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
565 struct ci_req *ci_req = container_of(req, struct ci_req, req);
566 int in, ret;
567 int __maybe_unused num;
568
569 num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
570 in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
571
572 if (!num && ci_ep->req_primed) {
573 /*
574 * The flipping of ep0 between IN and OUT relies on
575 * ci_ep_queue consuming the current IN/OUT setting
576 * immediately. If this is deferred to a later point when the
577 * req is pulled out of ci_req->queue, then the IN/OUT setting
578 * may have been changed since the req was queued, and state
579 * will get out of sync. This condition doesn't occur today,
580 * but could if bugs were introduced later, and this error
581 * check will save a lot of debugging time.
582 */
583 printf("%s: ep0 transaction already in progress\n", __func__);
584 return -EPROTO;
585 }
586
587 ret = ci_bounce(ci_req, in);
588 if (ret)
589 return ret;
590
591 DBG("ept%d %s pre-queue req %p, buffer %p\n",
592 num, in ? "in" : "out", ci_req, ci_req->hw_buf);
593 list_add_tail(&ci_req->queue, &ci_ep->queue);
594
595 if (!ci_ep->req_primed)
596 ci_ep_submit_next_request(ci_ep);
597
598 return 0;
599 }
600
flip_ep0_direction(void)601 static void flip_ep0_direction(void)
602 {
603 if (ep0_desc.bEndpointAddress == USB_DIR_IN) {
604 DBG("%s: Flipping ep0 to OUT\n", __func__);
605 ep0_desc.bEndpointAddress = 0;
606 } else {
607 DBG("%s: Flipping ep0 to IN\n", __func__);
608 ep0_desc.bEndpointAddress = USB_DIR_IN;
609 }
610 }
611
handle_ep_complete(struct ci_ep * ci_ep)612 static void handle_ep_complete(struct ci_ep *ci_ep)
613 {
614 struct ept_queue_item *item, *next_td;
615 int num, in, len, j;
616 struct ci_req *ci_req;
617
618 num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
619 in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
620 item = ci_get_qtd(num, in);
621 ci_invalidate_qtd(num);
622 ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue);
623
624 next_td = item;
625 len = 0;
626 for (j = 0; j < ci_req->dtd_count; j++) {
627 ci_invalidate_td(next_td);
628 item = next_td;
629 len += (item->info >> 16) & 0x7fff;
630 if (item->info & 0xff)
631 printf("EP%d/%s FAIL info=%x pg0=%x\n",
632 num, in ? "in" : "out", item->info, item->page0);
633 if (j != ci_req->dtd_count - 1)
634 next_td = (struct ept_queue_item *)(unsigned long)
635 item->next;
636 if (j != 0)
637 free(item);
638 }
639
640 list_del_init(&ci_req->queue);
641 ci_ep->req_primed = false;
642
643 if (!list_empty(&ci_ep->queue))
644 ci_ep_submit_next_request(ci_ep);
645
646 ci_req->req.actual = ci_req->req.length - len;
647 ci_debounce(ci_req, in);
648
649 DBG("ept%d %s req %p, complete %x\n",
650 num, in ? "in" : "out", ci_req, len);
651 if (num != 0 || controller.ep0_data_phase)
652 ci_req->req.complete(&ci_ep->ep, &ci_req->req);
653 if (num == 0 && controller.ep0_data_phase) {
654 /*
655 * Data Stage is complete, so flip ep0 dir for Status Stage,
656 * which always transfers a packet in the opposite direction.
657 */
658 DBG("%s: flip ep0 dir for Status Stage\n", __func__);
659 flip_ep0_direction();
660 controller.ep0_data_phase = false;
661 ci_req->req.length = 0;
662 usb_ep_queue(&ci_ep->ep, &ci_req->req, 0);
663 }
664 }
665
666 #define SETUP(type, request) (((type) << 8) | (request))
667
handle_setup(void)668 static void handle_setup(void)
669 {
670 struct ci_ep *ci_ep = &controller.ep[0];
671 struct ci_req *ci_req;
672 struct usb_request *req;
673 struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
674 struct ept_queue_head *head;
675 struct usb_ctrlrequest r;
676 int status = 0;
677 int num, in, _num, _in, i;
678 char *buf;
679
680 ci_req = controller.ep0_req;
681 req = &ci_req->req;
682 head = ci_get_qh(0, 0); /* EP0 OUT */
683
684 ci_invalidate_qh(0);
685 memcpy(&r, head->setup_data, sizeof(struct usb_ctrlrequest));
686 #ifdef CONFIG_CI_UDC_HAS_HOSTPC
687 writel(EPT_RX(0), &udc->epsetupstat);
688 #else
689 writel(EPT_RX(0), &udc->epstat);
690 #endif
691 DBG("handle setup %s, %x, %x index %x value %x length %x\n",
692 reqname(r.bRequest), r.bRequestType, r.bRequest, r.wIndex,
693 r.wValue, r.wLength);
694
695 /* Set EP0 dir for Data Stage based on Setup Stage data */
696 if (r.bRequestType & USB_DIR_IN) {
697 DBG("%s: Set ep0 to IN for Data Stage\n", __func__);
698 ep0_desc.bEndpointAddress = USB_DIR_IN;
699 } else {
700 DBG("%s: Set ep0 to OUT for Data Stage\n", __func__);
701 ep0_desc.bEndpointAddress = 0;
702 }
703 if (r.wLength) {
704 controller.ep0_data_phase = true;
705 } else {
706 /* 0 length -> no Data Stage. Flip dir for Status Stage */
707 DBG("%s: 0 length: flip ep0 dir for Status Stage\n", __func__);
708 flip_ep0_direction();
709 controller.ep0_data_phase = false;
710 }
711
712 list_del_init(&ci_req->queue);
713 ci_ep->req_primed = false;
714
715 switch (SETUP(r.bRequestType, r.bRequest)) {
716 case SETUP(USB_RECIP_ENDPOINT, USB_REQ_CLEAR_FEATURE):
717 _num = r.wIndex & 15;
718 _in = !!(r.wIndex & 0x80);
719
720 if ((r.wValue == 0) && (r.wLength == 0)) {
721 req->length = 0;
722 for (i = 0; i < NUM_ENDPOINTS; i++) {
723 struct ci_ep *ep = &controller.ep[i];
724
725 if (!ep->desc)
726 continue;
727 num = ep->desc->bEndpointAddress
728 & USB_ENDPOINT_NUMBER_MASK;
729 in = (ep->desc->bEndpointAddress
730 & USB_DIR_IN) != 0;
731 if ((num == _num) && (in == _in)) {
732 ep_enable(num, in, ep->ep.maxpacket);
733 usb_ep_queue(controller.gadget.ep0,
734 req, 0);
735 break;
736 }
737 }
738 }
739 return;
740
741 case SETUP(USB_RECIP_DEVICE, USB_REQ_SET_ADDRESS):
742 /*
743 * write address delayed (will take effect
744 * after the next IN txn)
745 */
746 writel((r.wValue << 25) | (1 << 24), &udc->devaddr);
747 req->length = 0;
748 usb_ep_queue(controller.gadget.ep0, req, 0);
749 return;
750
751 case SETUP(USB_DIR_IN | USB_RECIP_DEVICE, USB_REQ_GET_STATUS):
752 req->length = 2;
753 buf = (char *)req->buf;
754 buf[0] = 1 << USB_DEVICE_SELF_POWERED;
755 buf[1] = 0;
756 usb_ep_queue(controller.gadget.ep0, req, 0);
757 return;
758 }
759 /* pass request up to the gadget driver */
760 if (controller.driver)
761 status = controller.driver->setup(&controller.gadget, &r);
762 else
763 status = -ENODEV;
764
765 if (!status)
766 return;
767 DBG("STALL reqname %s type %x value %x, index %x\n",
768 reqname(r.bRequest), r.bRequestType, r.wValue, r.wIndex);
769 writel((1<<16) | (1 << 0), &udc->epctrl[0]);
770 }
771
stop_activity(void)772 static void stop_activity(void)
773 {
774 int i, num, in;
775 struct ept_queue_head *head;
776 struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
777 writel(readl(&udc->epcomp), &udc->epcomp);
778 #ifdef CONFIG_CI_UDC_HAS_HOSTPC
779 writel(readl(&udc->epsetupstat), &udc->epsetupstat);
780 #endif
781 writel(readl(&udc->epstat), &udc->epstat);
782 writel(0xffffffff, &udc->epflush);
783
784 /* error out any pending reqs */
785 for (i = 0; i < NUM_ENDPOINTS; i++) {
786 if (i != 0)
787 writel(0, &udc->epctrl[i]);
788 if (controller.ep[i].desc) {
789 num = controller.ep[i].desc->bEndpointAddress
790 & USB_ENDPOINT_NUMBER_MASK;
791 in = (controller.ep[i].desc->bEndpointAddress
792 & USB_DIR_IN) != 0;
793 head = ci_get_qh(num, in);
794 head->info = INFO_ACTIVE;
795 ci_flush_qh(num);
796 }
797 }
798 }
799
udc_irq(void)800 void udc_irq(void)
801 {
802 struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
803 unsigned n = readl(&udc->usbsts);
804 writel(n, &udc->usbsts);
805 int bit, i, num, in;
806
807 n &= (STS_SLI | STS_URI | STS_PCI | STS_UI | STS_UEI);
808 if (n == 0)
809 return;
810
811 if (n & STS_URI) {
812 DBG("-- reset --\n");
813 stop_activity();
814 }
815 if (n & STS_SLI)
816 DBG("-- suspend --\n");
817
818 if (n & STS_PCI) {
819 int max = 64;
820 int speed = USB_SPEED_FULL;
821
822 #ifdef CONFIG_CI_UDC_HAS_HOSTPC
823 bit = (readl(&udc->hostpc1_devlc) >> 25) & 3;
824 #else
825 bit = (readl(&udc->portsc) >> 26) & 3;
826 #endif
827 DBG("-- portchange %x %s\n", bit, (bit == 2) ? "High" : "Full");
828 if (bit == 2) {
829 speed = USB_SPEED_HIGH;
830 max = 512;
831 }
832 controller.gadget.speed = speed;
833 for (i = 1; i < NUM_ENDPOINTS; i++) {
834 if (controller.ep[i].ep.maxpacket > max)
835 controller.ep[i].ep.maxpacket = max;
836 }
837 }
838
839 if (n & STS_UEI)
840 printf("<UEI %x>\n", readl(&udc->epcomp));
841
842 if ((n & STS_UI) || (n & STS_UEI)) {
843 #ifdef CONFIG_CI_UDC_HAS_HOSTPC
844 n = readl(&udc->epsetupstat);
845 #else
846 n = readl(&udc->epstat);
847 #endif
848 if (n & EPT_RX(0))
849 handle_setup();
850
851 n = readl(&udc->epcomp);
852 if (n != 0)
853 writel(n, &udc->epcomp);
854
855 for (i = 0; i < NUM_ENDPOINTS && n; i++) {
856 if (controller.ep[i].desc) {
857 num = controller.ep[i].desc->bEndpointAddress
858 & USB_ENDPOINT_NUMBER_MASK;
859 in = (controller.ep[i].desc->bEndpointAddress
860 & USB_DIR_IN) != 0;
861 bit = (in) ? EPT_TX(num) : EPT_RX(num);
862 if (n & bit)
863 handle_ep_complete(&controller.ep[i]);
864 }
865 }
866 }
867 }
868
usb_gadget_handle_interrupts(int index)869 int usb_gadget_handle_interrupts(int index)
870 {
871 u32 value;
872 struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
873
874 value = readl(&udc->usbsts);
875 if (value)
876 udc_irq();
877
878 return value;
879 }
880
udc_disconnect(void)881 void udc_disconnect(void)
882 {
883 struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
884 /* disable pullup */
885 stop_activity();
886 writel(USBCMD_FS2, &udc->usbcmd);
887 udelay(800);
888 if (controller.driver)
889 controller.driver->disconnect(&controller.gadget);
890 }
891
ci_pullup(struct usb_gadget * gadget,int is_on)892 static int ci_pullup(struct usb_gadget *gadget, int is_on)
893 {
894 struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
895 if (is_on) {
896 /* RESET */
897 writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RST, &udc->usbcmd);
898 udelay(200);
899
900 ci_init_after_reset(controller.ctrl);
901
902 writel((unsigned long)controller.epts, &udc->epinitaddr);
903
904 /* select DEVICE mode */
905 writel(USBMODE_DEVICE, &udc->usbmode);
906
907 #if !defined(CONFIG_USB_GADGET_DUALSPEED)
908 /* Port force Full-Speed Connect */
909 setbits_le32(&udc->portsc, PFSC);
910 #endif
911
912 writel(0xffffffff, &udc->epflush);
913
914 /* Turn on the USB connection by enabling the pullup resistor */
915 setbits_le32(&udc->usbcmd, USBCMD_ITC(MICRO_8FRAME) |
916 USBCMD_RUN);
917 } else {
918 udc_disconnect();
919 }
920
921 return 0;
922 }
923
ci_udc_probe(void)924 static int ci_udc_probe(void)
925 {
926 struct ept_queue_head *head;
927 int i;
928
929 const int num = 2 * NUM_ENDPOINTS;
930
931 const int eplist_min_align = 4096;
932 const int eplist_align = roundup(eplist_min_align, ARCH_DMA_MINALIGN);
933 const int eplist_raw_sz = num * sizeof(struct ept_queue_head);
934 const int eplist_sz = roundup(eplist_raw_sz, ARCH_DMA_MINALIGN);
935
936 /* The QH list must be aligned to 4096 bytes. */
937 controller.epts = memalign(eplist_align, eplist_sz);
938 if (!controller.epts)
939 return -ENOMEM;
940 memset(controller.epts, 0, eplist_sz);
941
942 controller.items_mem = memalign(ILIST_ALIGN, ILIST_SZ);
943 if (!controller.items_mem) {
944 free(controller.epts);
945 return -ENOMEM;
946 }
947 memset(controller.items_mem, 0, ILIST_SZ);
948
949 for (i = 0; i < 2 * NUM_ENDPOINTS; i++) {
950 /*
951 * Configure QH for each endpoint. The structure of the QH list
952 * is such that each two subsequent fields, N and N+1 where N is
953 * even, in the QH list represent QH for one endpoint. The Nth
954 * entry represents OUT configuration and the N+1th entry does
955 * represent IN configuration of the endpoint.
956 */
957 head = controller.epts + i;
958 if (i < 2)
959 head->config = CONFIG_MAX_PKT(EP0_MAX_PACKET_SIZE)
960 | CONFIG_ZLT | CONFIG_IOS;
961 else
962 head->config = CONFIG_MAX_PKT(EP_MAX_PACKET_SIZE)
963 | CONFIG_ZLT;
964 head->next = TERMINATE;
965 head->info = 0;
966
967 if (i & 1) {
968 ci_flush_qh(i / 2);
969 ci_flush_qtd(i / 2);
970 }
971 }
972
973 INIT_LIST_HEAD(&controller.gadget.ep_list);
974
975 /* Init EP 0 */
976 memcpy(&controller.ep[0].ep, &ci_ep_init[0], sizeof(*ci_ep_init));
977 controller.ep[0].desc = &ep0_desc;
978 INIT_LIST_HEAD(&controller.ep[0].queue);
979 controller.ep[0].req_primed = false;
980 controller.gadget.ep0 = &controller.ep[0].ep;
981 INIT_LIST_HEAD(&controller.gadget.ep0->ep_list);
982
983 /* Init EP 1..3 */
984 for (i = 1; i < 4; i++) {
985 memcpy(&controller.ep[i].ep, &ci_ep_init[i],
986 sizeof(*ci_ep_init));
987 INIT_LIST_HEAD(&controller.ep[i].queue);
988 controller.ep[i].req_primed = false;
989 list_add_tail(&controller.ep[i].ep.ep_list,
990 &controller.gadget.ep_list);
991 }
992
993 /* Init EP 4..n */
994 for (i = 4; i < NUM_ENDPOINTS; i++) {
995 memcpy(&controller.ep[i].ep, &ci_ep_init[4],
996 sizeof(*ci_ep_init));
997 INIT_LIST_HEAD(&controller.ep[i].queue);
998 controller.ep[i].req_primed = false;
999 list_add_tail(&controller.ep[i].ep.ep_list,
1000 &controller.gadget.ep_list);
1001 }
1002
1003 ci_ep_alloc_request(&controller.ep[0].ep, 0);
1004 if (!controller.ep0_req) {
1005 free(controller.items_mem);
1006 free(controller.epts);
1007 return -ENOMEM;
1008 }
1009
1010 return 0;
1011 }
1012
usb_gadget_register_driver(struct usb_gadget_driver * driver)1013 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1014 {
1015 int ret;
1016
1017 if (!driver)
1018 return -EINVAL;
1019 if (!driver->bind || !driver->setup || !driver->disconnect)
1020 return -EINVAL;
1021
1022 #if CONFIG_IS_ENABLED(DM_USB)
1023 ret = usb_setup_ehci_gadget(&controller.ctrl);
1024 #else
1025 ret = usb_lowlevel_init(0, USB_INIT_DEVICE, (void **)&controller.ctrl);
1026 #endif
1027 if (ret)
1028 return ret;
1029
1030 ret = ci_udc_probe();
1031 if (ret) {
1032 DBG("udc probe failed, returned %d\n", ret);
1033 return ret;
1034 }
1035
1036 ret = driver->bind(&controller.gadget);
1037 if (ret) {
1038 DBG("driver->bind() returned %d\n", ret);
1039 return ret;
1040 }
1041 controller.driver = driver;
1042
1043 return 0;
1044 }
1045
usb_gadget_unregister_driver(struct usb_gadget_driver * driver)1046 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1047 {
1048 udc_disconnect();
1049
1050 driver->unbind(&controller.gadget);
1051 controller.driver = NULL;
1052
1053 ci_ep_free_request(&controller.ep[0].ep, &controller.ep0_req->req);
1054 free(controller.items_mem);
1055 free(controller.epts);
1056
1057 #if CONFIG_IS_ENABLED(DM_USB)
1058 usb_remove_ehci_gadget(&controller.ctrl);
1059 #else
1060 usb_lowlevel_stop(0);
1061 controller.ctrl = NULL;
1062 #endif
1063
1064 return 0;
1065 }
1066
dfu_usb_get_reset(void)1067 bool dfu_usb_get_reset(void)
1068 {
1069 struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
1070
1071 return !!(readl(&udc->usbsts) & STS_URI);
1072 }
1073