1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* linux/arch/arm/plat-s3c/include/plat/regs-otg.h
3  *
4  * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
5  *
6  * Registers remapping:
7  * Lukasz Majewski <l.majewski@samsumg.com>
8  */
9 
10 #ifndef __ASM_ARCH_REGS_USB_OTG_HS_H
11 #define __ASM_ARCH_REGS_USB_OTG_HS_H
12 
13 /* USB2.0 OTG Controller register */
14 #include <linux/bitops.h>
15 struct dwc2_usbotg_phy {
16 	u32 phypwr;
17 	u32 phyclk;
18 	u32 rstcon;
19 };
20 
21 /* Device Logical IN Endpoint-Specific Registers */
22 struct dwc2_dev_in_endp {
23 	u32 diepctl;
24 	u8  res1[4];
25 	u32 diepint;
26 	u8  res2[4];
27 	u32 dieptsiz;
28 	u32 diepdma;
29 	u8  res3[4];
30 	u32 diepdmab;
31 };
32 
33 /* Device Logical OUT Endpoint-Specific Registers */
34 struct dwc2_dev_out_endp {
35 	u32 doepctl;
36 	u8  res1[4];
37 	u32 doepint;
38 	u8  res2[4];
39 	u32 doeptsiz;
40 	u32 doepdma;
41 	u8  res3[4];
42 	u32 doepdmab;
43 };
44 
45 struct ep_fifo {
46 	u32 fifo;
47 	u8  res[4092];
48 };
49 
50 /* USB2.0 OTG Controller register */
51 struct dwc2_usbotg_reg {
52 	/* Core Global Registers */
53 	u32 gotgctl; /* OTG Control & Status */
54 	u32 gotgint; /* OTG Interrupt */
55 	u32 gahbcfg; /* Core AHB Configuration */
56 	u32 gusbcfg; /* Core USB Configuration */
57 	u32 grstctl; /* Core Reset */
58 	u32 gintsts; /* Core Interrupt */
59 	u32 gintmsk; /* Core Interrupt Mask */
60 	u32 grxstsr; /* Receive Status Debug Read/Status Read */
61 	u32 grxstsp; /* Receive Status Debug Pop/Status Pop */
62 	u32 grxfsiz; /* Receive FIFO Size */
63 	u32 gnptxfsiz; /* Non-Periodic Transmit FIFO Size */
64 	u8  res0[12];
65 	u32 ggpio;     /* 0x038 */
66 	u8  res1[20];
67 	u32 ghwcfg4; /* User HW Config4 */
68 	u8  res2[176];
69 	u32 dieptxf[15]; /* Device Periodic Transmit FIFO size register */
70 	u8  res3[1728];
71 	/* Device Configuration */
72 	u32 dcfg; /* Device Configuration Register */
73 	u32 dctl; /* Device Control */
74 	u32 dsts; /* Device Status */
75 	u8  res4[4];
76 	u32 diepmsk; /* Device IN Endpoint Common Interrupt Mask */
77 	u32 doepmsk; /* Device OUT Endpoint Common Interrupt Mask */
78 	u32 daint; /* Device All Endpoints Interrupt */
79 	u32 daintmsk; /* Device All Endpoints Interrupt Mask */
80 	u8  res5[224];
81 	struct dwc2_dev_in_endp in_endp[16];
82 	struct dwc2_dev_out_endp out_endp[16];
83 	u8  res6[768];
84 	struct ep_fifo ep[16];
85 };
86 
87 /*===================================================================== */
88 /*definitions related to CSR setting */
89 
90 /* DWC2_UDC_OTG_GOTGCTL */
91 #define B_SESSION_VALID			BIT(19)
92 #define A_SESSION_VALID			BIT(18)
93 #define B_VALOVAL			BIT(7)
94 #define B_VALOEN			BIT(6)
95 #define A_VALOVAL			BIT(5)
96 #define A_VALOEN			BIT(4)
97 #define VB_VALOVAL			BIT(3)
98 #define VB_VALOEN			BIT(2)
99 
100 /* DWC2_UDC_OTG_GOTINT */
101 #define GOTGINT_SES_END_DET		(1<<2)
102 
103 /* DWC2_UDC_OTG_GAHBCFG */
104 #define PTXFE_HALF			(0<<8)
105 #define PTXFE_ZERO			(1<<8)
106 #define NPTXFE_HALF			(0<<7)
107 #define NPTXFE_ZERO			(1<<7)
108 #define MODE_SLAVE			(0<<5)
109 #define MODE_DMA			(1<<5)
110 #define BURST_SINGLE			(0<<1)
111 #define BURST_INCR			(1<<1)
112 #define BURST_INCR4			(3<<1)
113 #define BURST_INCR8			(5<<1)
114 #define BURST_INCR16			(7<<1)
115 #define GBL_INT_UNMASK			(1<<0)
116 #define GBL_INT_MASK			(0<<0)
117 
118 /* DWC2_UDC_OTG_GRSTCTL */
119 #define AHB_MASTER_IDLE		(1u<<31)
120 #define CORE_SOFT_RESET		(0x1<<0)
121 
122 /* DWC2_UDC_OTG_GINTSTS/DWC2_UDC_OTG_GINTMSK core interrupt register */
123 #define INT_RESUME			(1u<<31)
124 #define INT_DISCONN			(0x1<<29)
125 #define INT_CONN_ID_STS_CNG		(0x1<<28)
126 #define INT_OUT_EP			(0x1<<19)
127 #define INT_IN_EP			(0x1<<18)
128 #define INT_ENUMDONE			(0x1<<13)
129 #define INT_RESET			(0x1<<12)
130 #define INT_SUSPEND			(0x1<<11)
131 #define INT_EARLY_SUSPEND		(0x1<<10)
132 #define INT_NP_TX_FIFO_EMPTY		(0x1<<5)
133 #define INT_RX_FIFO_NOT_EMPTY		(0x1<<4)
134 #define INT_SOF			(0x1<<3)
135 #define INT_OTG			(0x1<<2)
136 #define INT_DEV_MODE			(0x0<<0)
137 #define INT_HOST_MODE			(0x1<<1)
138 #define INT_GOUTNakEff			(0x01<<7)
139 #define INT_GINNakEff			(0x01<<6)
140 
141 #define FULL_SPEED_CONTROL_PKT_SIZE	8
142 #define FULL_SPEED_BULK_PKT_SIZE	64
143 
144 #define HIGH_SPEED_CONTROL_PKT_SIZE	64
145 #define HIGH_SPEED_BULK_PKT_SIZE	512
146 
147 #define RX_FIFO_SIZE			(1024)
148 #define NPTX_FIFO_SIZE			(1024)
149 #define PTX_FIFO_SIZE			(384)
150 
151 #define DEPCTL_TXFNUM_0		(0x0<<22)
152 #define DEPCTL_TXFNUM_1		(0x1<<22)
153 #define DEPCTL_TXFNUM_2		(0x2<<22)
154 #define DEPCTL_TXFNUM_3		(0x3<<22)
155 #define DEPCTL_TXFNUM_4		(0x4<<22)
156 
157 /* Enumeration speed */
158 #define USB_HIGH_30_60MHZ		(0x0<<1)
159 #define USB_FULL_30_60MHZ		(0x1<<1)
160 #define USB_LOW_6MHZ			(0x2<<1)
161 #define USB_FULL_48MHZ			(0x3<<1)
162 
163 /* DWC2_UDC_OTG_GRXSTSP STATUS */
164 #define OUT_PKT_RECEIVED		(0x2<<17)
165 #define OUT_TRANSFER_COMPLELTED	(0x3<<17)
166 #define SETUP_TRANSACTION_COMPLETED	(0x4<<17)
167 #define SETUP_PKT_RECEIVED		(0x6<<17)
168 #define GLOBAL_OUT_NAK			(0x1<<17)
169 
170 /* DWC2_UDC_OTG_DCTL device control register */
171 #define NORMAL_OPERATION		(0x1<<0)
172 #define SOFT_DISCONNECT		(0x1<<1)
173 
174 /* DWC2_UDC_OTG_DAINT device all endpoint interrupt register */
175 #define DAINT_OUT_BIT			(16)
176 #define DAINT_MASK			(0xFFFF)
177 
178 /* DWC2_UDC_OTG_DIEPCTL0/DOEPCTL0 device
179    control IN/OUT endpoint 0 control register */
180 #define DEPCTL_EPENA			(0x1<<31)
181 #define DEPCTL_EPDIS			(0x1<<30)
182 #define DEPCTL_SETD1PID		(0x1<<29)
183 #define DEPCTL_SETD0PID		(0x1<<28)
184 #define DEPCTL_SNAK			(0x1<<27)
185 #define DEPCTL_CNAK			(0x1<<26)
186 #define DEPCTL_STALL			(0x1<<21)
187 #define DEPCTL_TYPE_BIT		(18)
188 #define DEPCTL_TYPE_MASK		(0x3<<18)
189 #define DEPCTL_CTRL_TYPE		(0x0<<18)
190 #define DEPCTL_ISO_TYPE		(0x1<<18)
191 #define DEPCTL_BULK_TYPE		(0x2<<18)
192 #define DEPCTL_INTR_TYPE		(0x3<<18)
193 #define DEPCTL_USBACTEP		(0x1<<15)
194 #define DEPCTL_NEXT_EP_BIT		(11)
195 #define DEPCTL_MPS_BIT			(0)
196 #define DEPCTL_MPS_MASK		(0x7FF)
197 
198 #define DEPCTL0_MPS_64			(0x0<<0)
199 #define DEPCTL0_MPS_32			(0x1<<0)
200 #define DEPCTL0_MPS_16			(0x2<<0)
201 #define DEPCTL0_MPS_8			(0x3<<0)
202 #define DEPCTL_MPS_BULK_512		(512<<0)
203 #define DEPCTL_MPS_INT_MPS_16		(16<<0)
204 
205 #define DIEPCTL0_NEXT_EP_BIT		(11)
206 
207 
208 /* DWC2_UDC_OTG_DIEPMSK/DOEPMSK device IN/OUT endpoint
209    common interrupt mask register */
210 /* DWC2_UDC_OTG_DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register */
211 #define BACK2BACK_SETUP_RECEIVED	(0x1<<6)
212 #define INTKNEPMIS			(0x1<<5)
213 #define INTKN_TXFEMP			(0x1<<4)
214 #define NON_ISO_IN_EP_TIMEOUT		(0x1<<3)
215 #define CTRL_OUT_EP_SETUP_PHASE_DONE	(0x1<<3)
216 #define AHB_ERROR			(0x1<<2)
217 #define EPDISBLD			(0x1<<1)
218 #define TRANSFER_DONE			(0x1<<0)
219 
220 #define USB_PHY_CTRL_EN0                (0x1 << 0)
221 
222 /* OPHYPWR */
223 #define PHY_0_SLEEP                     (0x1 << 5)
224 #define OTG_DISABLE_0                   (0x1 << 4)
225 #define ANALOG_PWRDOWN                  (0x1 << 3)
226 #define FORCE_SUSPEND_0                 (0x1 << 0)
227 
228 /* URSTCON */
229 #define HOST_SW_RST                     (0x1 << 4)
230 #define PHY_SW_RST1                     (0x1 << 3)
231 #define PHYLNK_SW_RST                   (0x1 << 2)
232 #define LINK_SW_RST                     (0x1 << 1)
233 #define PHY_SW_RST0                     (0x1 << 0)
234 
235 /* OPHYCLK */
236 #define COMMON_ON_N1                    (0x1 << 7)
237 #define COMMON_ON_N0                    (0x1 << 4)
238 #define ID_PULLUP0                      (0x1 << 2)
239 #define CLK_SEL_24MHZ                   (0x3 << 0)
240 #define CLK_SEL_12MHZ                   (0x2 << 0)
241 #define CLK_SEL_48MHZ                   (0x0 << 0)
242 
243 #define EXYNOS4X12_ID_PULLUP0		(0x01 << 3)
244 #define EXYNOS4X12_COMMON_ON_N0	(0x01 << 4)
245 #define EXYNOS4X12_CLK_SEL_12MHZ	(0x02 << 0)
246 #define EXYNOS4X12_CLK_SEL_24MHZ	(0x05 << 0)
247 
248 /* Device Configuration Register DCFG */
249 #define DEV_SPEED_HIGH_SPEED_20         (0x0 << 0)
250 #define DEV_SPEED_FULL_SPEED_20         (0x1 << 0)
251 #define DEV_SPEED_LOW_SPEED_11          (0x2 << 0)
252 #define DEV_SPEED_FULL_SPEED_11         (0x3 << 0)
253 #define EP_MISS_CNT(x)                  (x << 18)
254 #define DEVICE_ADDRESS(x)               (x << 4)
255 
256 /* Core Reset Register (GRSTCTL) */
257 #define TX_FIFO_FLUSH                   (0x1 << 5)
258 #define RX_FIFO_FLUSH                   (0x1 << 4)
259 #define TX_FIFO_NUMBER(x)               (x << 6)
260 #define TX_FIFO_FLUSH_ALL               TX_FIFO_NUMBER(0x10)
261 
262 /* Masks definitions */
263 #define GINTMSK_INIT	(INT_OUT_EP | INT_IN_EP | INT_RESUME | INT_ENUMDONE\
264 			| INT_RESET | INT_SUSPEND | INT_OTG)
265 #define DOEPMSK_INIT	(CTRL_OUT_EP_SETUP_PHASE_DONE | AHB_ERROR|TRANSFER_DONE)
266 #define DIEPMSK_INIT	(NON_ISO_IN_EP_TIMEOUT|AHB_ERROR|TRANSFER_DONE)
267 #define GAHBCFG_INIT	(PTXFE_HALF | NPTXFE_HALF | MODE_DMA | BURST_INCR4\
268 			| GBL_INT_UNMASK)
269 
270 /* Device Endpoint X Transfer Size Register (DIEPTSIZX) */
271 #define DIEPT_SIZ_PKT_CNT(x)                      (x << 19)
272 #define DIEPT_SIZ_XFER_SIZE(x)                    (x << 0)
273 
274 /* Device OUT Endpoint X Transfer Size Register (DOEPTSIZX) */
275 #define DOEPT_SIZ_PKT_CNT(x)                      (x << 19)
276 #define DOEPT_SIZ_XFER_SIZE(x)                    (x << 0)
277 #define DOEPT_SIZ_XFER_SIZE_MAX_EP0               (0x7F << 0)
278 #define DOEPT_SIZ_XFER_SIZE_MAX_EP                (0x7FFF << 0)
279 
280 /* Device Endpoint-N Control Register (DIEPCTLn/DOEPCTLn) */
281 #define DIEPCTL_TX_FIFO_NUM(x)                    (x << 22)
282 #define DIEPCTL_TX_FIFO_NUM_MASK                  (~DIEPCTL_TX_FIFO_NUM(0xF))
283 
284 /* Device ALL Endpoints Interrupt Register (DAINT) */
285 #define DAINT_IN_EP_INT(x)                        (x << 0)
286 #define DAINT_OUT_EP_INT(x)                       (x << 16)
287 
288 /* User HW Config4 */
289 #define GHWCFG4_NUM_IN_EPS_MASK		(0xf << 26)
290 #define GHWCFG4_NUM_IN_EPS_SHIFT	26
291 
292 /* OTG general core configuration register (OTG_GCCFG:0x38) for STM32MP1 */
293 #define GGPIO_STM32_OTG_GCCFG_VBDEN               BIT(21)
294 #define GGPIO_STM32_OTG_GCCFG_IDEN                BIT(22)
295 
296 #endif
297