1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (C) Marvell International Ltd. and its affiliates
4 */
5
6 #ifndef _DDR_ML_WRAPPER_H
7 #define _DDR_ML_WRAPPER_H
8
9 #include <common.h>
10 #include <i2c.h>
11 #include <spl.h>
12 #include <asm/io.h>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/soc.h>
15
16 #define INTER_REGS_BASE SOC_REGS_PHY_BASE
17
18 /*
19 * MV_DEBUG_INIT need to be defines, otherwise the output of the
20 * DDR2 training code is not complete and misleading
21 */
22 #define MV_DEBUG_INIT
23
24 #ifdef MV_DEBUG_INIT
25 #define DEBUG_INIT_S(s) puts(s)
26 #define DEBUG_INIT_D(d, l) printf("%x", d)
27 #define DEBUG_INIT_D_10(d, l) printf("%d", d)
28 #else
29 #define DEBUG_INIT_S(s)
30 #define DEBUG_INIT_D(d, l)
31 #define DEBUG_INIT_D_10(d, l)
32 #endif
33
34 #ifdef MV_DEBUG_INIT_FULL
35 #define DEBUG_INIT_FULL_S(s) puts(s)
36 #define DEBUG_INIT_FULL_D(d, l) printf("%x", d)
37 #define DEBUG_INIT_FULL_D_10(d, l) printf("%d", d)
38 #define DEBUG_WR_REG(reg, val) \
39 { DEBUG_INIT_S("Write Reg: 0x"); DEBUG_INIT_D((reg), 8); \
40 DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
41 #define DEBUG_RD_REG(reg, val) \
42 { DEBUG_INIT_S("Read Reg: 0x"); DEBUG_INIT_D((reg), 8); \
43 DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
44 #else
45 #define DEBUG_INIT_FULL_S(s)
46 #define DEBUG_INIT_FULL_D(d, l)
47 #define DEBUG_INIT_FULL_D_10(d, l)
48 #define DEBUG_WR_REG(reg, val)
49 #define DEBUG_RD_REG(reg, val)
50 #endif
51
52 #define DEBUG_INIT_FULL_C(s, d, l) \
53 { DEBUG_INIT_FULL_S(s); \
54 DEBUG_INIT_FULL_D(d, l); \
55 DEBUG_INIT_FULL_S("\n"); }
56 #define DEBUG_INIT_C(s, d, l) \
57 { DEBUG_INIT_S(s); DEBUG_INIT_D(d, l); DEBUG_INIT_S("\n"); }
58
59 /*
60 * Debug (Enable/Disable modules) and Error report
61 */
62
63 #ifdef BASIC_DEBUG
64 #define MV_DEBUG_WL
65 #define MV_DEBUG_RL
66 #define MV_DEBUG_DQS_RESULTS
67 #endif
68
69 #ifdef FULL_DEBUG
70 #define MV_DEBUG_WL
71 #define MV_DEBUG_RL
72 #define MV_DEBUG_DQS
73
74 #define MV_DEBUG_PBS
75 #define MV_DEBUG_DFS
76 #define MV_DEBUG_MAIN_FULL
77 #define MV_DEBUG_DFS_FULL
78 #define MV_DEBUG_DQS_FULL
79 #define MV_DEBUG_RL_FULL
80 #define MV_DEBUG_WL_FULL
81 #endif
82
83
84 /* The following is a list of Marvell status */
85 #define MV_ERROR (-1)
86 #define MV_OK (0x00) /* Operation succeeded */
87 #define MV_FAIL (0x01) /* Operation failed */
88 #define MV_BAD_VALUE (0x02) /* Illegal value (general) */
89 #define MV_OUT_OF_RANGE (0x03) /* The value is out of range */
90 #define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */
91 #define MV_BAD_PTR (0x05) /* Illegal pointer value */
92 #define MV_BAD_SIZE (0x06) /* Illegal size */
93 #define MV_BAD_STATE (0x07) /* Illegal state of state machine */
94 #define MV_SET_ERROR (0x08) /* Set operation failed */
95 #define MV_GET_ERROR (0x09) /* Get operation failed */
96 #define MV_CREATE_ERROR (0x0a) /* Fail while creating an item */
97 #define MV_NOT_FOUND (0x0b) /* Item not found */
98 #define MV_NO_MORE (0x0c) /* No more items found */
99 #define MV_NO_SUCH (0x0d) /* No such item */
100 #define MV_TIMEOUT (0x0e) /* Time Out */
101 #define MV_NO_CHANGE (0x0f) /* Parameter(s) is already in this value */
102 #define MV_NOT_SUPPORTED (0x10) /* This request is not support */
103 #define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented*/
104 #define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */
105 #define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */
106 #define MV_FULL (0x14) /* Item is full (Queue or table etc...) */
107 #define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */
108 #define MV_INIT_ERROR (0x16) /* Error occurred while INIT process */
109 #define MV_HW_ERROR (0x17) /* Hardware error */
110 #define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */
111 #define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */
112 #define MV_NOT_READY (0x1a) /* The other side is not ready yet */
113 #define MV_ALREADY_EXIST (0x1b) /* Tried to create existing item */
114 #define MV_OUT_OF_CPU_MEM (0x1c) /* Cpu memory allocation failed. */
115 #define MV_NOT_STARTED (0x1d) /* Not started yet */
116 #define MV_BUSY (0x1e) /* Item is busy. */
117 #define MV_TERMINATE (0x1f) /* Item terminates it's work. */
118 #define MV_NOT_ALIGNED (0x20) /* Wrong alignment */
119 #define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */
120 #define MV_WRITE_PROTECT (0x22) /* Write protected */
121 #define MV_INVALID (int)(-1)
122
123 /*
124 * Accessor functions for the registers
125 */
reg_write(u32 addr,u32 val)126 static inline void reg_write(u32 addr, u32 val)
127 {
128 writel(val, INTER_REGS_BASE + addr);
129 }
130
reg_read(u32 addr)131 static inline u32 reg_read(u32 addr)
132 {
133 return readl(INTER_REGS_BASE + addr);
134 }
135
reg_bit_set(u32 addr,u32 mask)136 static inline void reg_bit_set(u32 addr, u32 mask)
137 {
138 setbits_le32(INTER_REGS_BASE + addr, mask);
139 }
140
reg_bit_clr(u32 addr,u32 mask)141 static inline void reg_bit_clr(u32 addr, u32 mask)
142 {
143 clrbits_le32(INTER_REGS_BASE + addr, mask);
144 }
145
146 #endif /* _DDR_ML_WRAPPER_H */
147