1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <init.h>
8 #include <mpc83xx.h>
9 #include <pci.h>
10 #include <asm/io.h>
11 #include <linux/delay.h>
12
13 static struct pci_region pci_regions[] = {
14 {
15 bus_start: CONFIG_SYS_PCI_MEM_BASE,
16 phys_start: CONFIG_SYS_PCI_MEM_PHYS,
17 size: CONFIG_SYS_PCI_MEM_SIZE,
18 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
19 },
20 {
21 bus_start: CONFIG_SYS_PCI_MMIO_BASE,
22 phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
23 size: CONFIG_SYS_PCI_MMIO_SIZE,
24 flags: PCI_REGION_MEM
25 },
26 {
27 bus_start: CONFIG_SYS_PCI_IO_BASE,
28 phys_start: CONFIG_SYS_PCI_IO_PHYS,
29 size: CONFIG_SYS_PCI_IO_SIZE,
30 flags: PCI_REGION_IO
31 }
32 };
33
34 static struct pci_region pcie_regions_0[] = {
35 {
36 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
37 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
38 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
39 .flags = PCI_REGION_MEM,
40 },
41 {
42 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
43 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
44 .size = CONFIG_SYS_PCIE1_IO_SIZE,
45 .flags = PCI_REGION_IO,
46 },
47 };
48
49 static struct pci_region pcie_regions_1[] = {
50 {
51 .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
52 .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
53 .size = CONFIG_SYS_PCIE2_MEM_SIZE,
54 .flags = PCI_REGION_MEM,
55 },
56 {
57 .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
58 .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
59 .size = CONFIG_SYS_PCIE2_IO_SIZE,
60 .flags = PCI_REGION_IO,
61 },
62 };
63
pci_init_board(void)64 void pci_init_board(void)
65 {
66 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
67 volatile sysconf83xx_t *sysconf = &immr->sysconf;
68 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
69 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
70 volatile law83xx_t *pcie_law = sysconf->pcielaw;
71 struct pci_region *reg[] = { pci_regions };
72 struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
73 u32 spridr = in_be32(&immr->sysconf.spridr);
74
75 /* Enable all 5 PCI_CLK_OUTPUTS */
76 clk->occr |= 0xf8000000;
77 udelay(2000);
78
79 /* Configure PCI Local Access Windows */
80 pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
81 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
82
83 pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
84 pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
85
86 mpc83xx_pci_init(1, reg);
87
88 /* There is no PEX in MPC8379 parts. */
89 if (PARTID_NO_E(spridr) == SPR_8379)
90 return;
91
92 /* Configure the clock for PCIE controller */
93 clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
94 SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
95
96 /* Deassert the resets in the control register */
97 out_be32(&sysconf->pecr1, 0xE0008000);
98 out_be32(&sysconf->pecr2, 0xE0008000);
99 udelay(2000);
100
101 /* Configure PCI Express Local Access Windows */
102 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
103 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
104
105 out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
106 out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
107
108 mpc83xx_pcie_init(2, pcie_reg);
109 }
110