1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Board functions for TI AM335X based draco board
4 * (C) Copyright 2013 Siemens Schweiz AG
5 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
6 *
7 * Based on:
8 *
9 * Board functions for TI AM335X based boards
10 * u-boot:/board/ti/am335x/board.c
11 *
12 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
13 */
14
15 #include <common.h>
16 #include <command.h>
17 #include <env.h>
18 #include <errno.h>
19 #include <init.h>
20 #include <net.h>
21 #include <spl.h>
22 #include <asm/arch/cpu.h>
23 #include <asm/arch/hardware.h>
24 #include <asm/arch/omap.h>
25 #include <asm/arch/ddr_defs.h>
26 #include <asm/arch/clock.h>
27 #include <asm/arch/gpio.h>
28 #include <asm/arch/mmc_host_def.h>
29 #include <asm/arch/sys_proto.h>
30 #include <asm/arch/mem.h>
31 #include <asm/io.h>
32 #include <asm/emif.h>
33 #include <asm/gpio.h>
34 #include <i2c.h>
35 #include <miiphy.h>
36 #include <cpsw.h>
37 #include <watchdog.h>
38 #include <linux/delay.h>
39 #include "board.h"
40 #include "../common/factoryset.h"
41 #include <nand.h>
42
43 #ifdef CONFIG_SPL_BUILD
44 static struct draco_baseboard_id __section(".data") settings;
45
46 #if DDR_PLL_FREQ == 303
47 #if !defined(CONFIG_TARGET_ETAMIN)
48 /* Default@303MHz-i0 */
49 const struct ddr3_data ddr3_default = {
50 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
51 0x0079, 0x0888A39B, 0x26517FDA, 0x501F84EF, 0x00100206, 0x61A44A32,
52 0x0000093B, 0x0000014A,
53 "default name @303MHz \0",
54 "default marking \0",
55 };
56 #else
57 /* etamin board */
58 const struct ddr3_data ddr3_default = {
59 0x33524444, 0x56312e36, 0x0080, 0x0000, 0x003A, 0x0010, 0x009F,
60 0x0050, 0x0888A39B, 0x266D7FDA, 0x501F86AF, 0x00100206, 0x61A44BB2,
61 0x0000093B, 0x0000018A,
62 "test-etamin \0",
63 "generic-8Gbit \0",
64 };
65 #endif
66 #elif DDR_PLL_FREQ == 400
67 /* Default@400MHz-i0 */
68 const struct ddr3_data ddr3_default = {
69 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab,
70 0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232,
71 0x00000618, 0x0000014A,
72 "default name @400MHz \0",
73 "default marking \0",
74 };
75 #endif
76
set_default_ddr3_timings(void)77 static void set_default_ddr3_timings(void)
78 {
79 printf("Set default DDR3 settings\n");
80 settings.ddr3 = ddr3_default;
81 }
82
print_ddr3_timings(void)83 static void print_ddr3_timings(void)
84 {
85 printf("\nDDR3\n");
86 printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ);
87 printf("device:\t\t%s\n", settings.ddr3.manu_name);
88 printf("marking:\t%s\n", settings.ddr3.manu_marking);
89 printf("%-20s, %-8s, %-8s, %-4s\n", "timing parameters", "eeprom",
90 "default", "diff");
91 PRINTARGS(magic);
92 PRINTARGS(version);
93 PRINTARGS(ddr3_sratio);
94 PRINTARGS(iclkout);
95
96 PRINTARGS(dt0rdsratio0);
97 PRINTARGS(dt0wdsratio0);
98 PRINTARGS(dt0fwsratio0);
99 PRINTARGS(dt0wrsratio0);
100
101 PRINTARGS(sdram_tim1);
102 PRINTARGS(sdram_tim2);
103 PRINTARGS(sdram_tim3);
104
105 PRINTARGS(emif_ddr_phy_ctlr_1);
106
107 PRINTARGS(sdram_config);
108 PRINTARGS(ref_ctrl);
109 PRINTARGS(ioctr_val);
110 }
111
print_chip_data(void)112 static void print_chip_data(void)
113 {
114 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
115 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
116 printf("\nCPU BOARD\n");
117 printf("device: \t'%s'\n", settings.chip.sdevname);
118 printf("hw version: \t'%s'\n", settings.chip.shwver);
119 printf("max freq: \t%d MHz\n", dpll_mpu_opp100.m);
120 }
121 #endif /* CONFIG_SPL_BUILD */
122
123 #define AM335X_NAND_ECC_MASK 0x0f
124 #define AM335X_NAND_ECC_TYPE_16 0x02
125
126 static int ecc_type;
127
128 struct am335x_nand_geometry {
129 u32 magic;
130 u8 nand_geo_addr;
131 u8 nand_geo_page;
132 u8 nand_bus;
133 };
134
draco_read_nand_geometry(void)135 static int draco_read_nand_geometry(void)
136 {
137 struct am335x_nand_geometry geo;
138
139 /* Read NAND geometry */
140 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x80, 2,
141 (uchar *)&geo, sizeof(struct am335x_nand_geometry))) {
142 printf("Could not read the NAND geomtery; something fundamentally wrong on the I2C bus.\n");
143 return -EIO;
144 }
145 if (geo.magic != 0xa657b310) {
146 printf("%s: bad magic: %x\n", __func__, geo.magic);
147 return -EFAULT;
148 }
149 if ((geo.nand_bus & AM335X_NAND_ECC_MASK) == AM335X_NAND_ECC_TYPE_16)
150 ecc_type = 16;
151 else
152 ecc_type = 8;
153
154 return 0;
155 }
156
157 /*
158 * Read header information from EEPROM into global structure.
159 */
read_eeprom(void)160 static int read_eeprom(void)
161 {
162 /* Check if baseboard eeprom is available */
163 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
164 printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
165 return 1;
166 }
167
168 #ifdef CONFIG_SPL_BUILD
169 /* Read Siemens eeprom data (DDR3) */
170 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2,
171 (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) {
172 printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n");
173 set_default_ddr3_timings();
174 }
175 /* Read Siemens eeprom data (CHIP) */
176 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2,
177 (uchar *)&settings.chip, sizeof(settings.chip)))
178 printf("Could not read chip settings\n");
179
180 if (ddr3_default.magic == settings.ddr3.magic &&
181 ddr3_default.version == settings.ddr3.version) {
182 printf("Using DDR3 settings from EEPROM\n");
183 } else {
184 if (ddr3_default.magic != settings.ddr3.magic)
185 printf("Warning: No valid DDR3 data in eeprom.\n");
186 if (ddr3_default.version != settings.ddr3.version)
187 printf("Warning: DDR3 data version does not match.\n");
188
189 printf("Using default settings\n");
190 set_default_ddr3_timings();
191 }
192
193 if (MAGIC_CHIP == settings.chip.magic)
194 print_chip_data();
195 else
196 printf("Warning: No chip data in eeprom\n");
197
198 print_ddr3_timings();
199
200 return draco_read_nand_geometry();
201 #endif
202 return 0;
203 }
204
205 #ifdef CONFIG_SPL_BUILD
board_init_ddr(void)206 static void board_init_ddr(void)
207 {
208 struct emif_regs draco_ddr3_emif_reg_data = {
209 .zq_config = 0x50074BE4,
210 };
211
212 struct ddr_data draco_ddr3_data = {
213 };
214
215 struct cmd_control draco_ddr3_cmd_ctrl_data = {
216 };
217
218 struct ctrl_ioregs draco_ddr3_ioregs = {
219 };
220
221 /* pass values from eeprom */
222 draco_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
223 draco_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
224 draco_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
225 draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
226 settings.ddr3.emif_ddr_phy_ctlr_1;
227 draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
228 draco_ddr3_emif_reg_data.sdram_config2 = 0x08000000;
229 draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
230
231 draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
232 draco_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
233 draco_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
234 draco_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
235
236 draco_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
237 draco_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
238 draco_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
239 draco_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
240 draco_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
241 draco_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
242
243 draco_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
244 draco_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
245 draco_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
246 draco_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
247 draco_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
248
249 config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data,
250 &draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0);
251 }
252
spl_siemens_board_init(void)253 static void spl_siemens_board_init(void)
254 {
255 return;
256 }
257 #endif /* if def CONFIG_SPL_BUILD */
258
259 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)260 int board_late_init(void)
261 {
262 int ret;
263
264 ret = draco_read_nand_geometry();
265 if (ret != 0)
266 return ret;
267
268 nand_curr_device = 0;
269 omap_nand_switch_ecc(1, ecc_type);
270 #ifdef CONFIG_TARGET_ETAMIN
271 nand_curr_device = 1;
272 omap_nand_switch_ecc(1, ecc_type);
273 #endif
274 #ifdef CONFIG_FACTORYSET
275 /* Set ASN in environment*/
276 if (factory_dat.asn[0] != 0) {
277 env_set("dtb_name", (char *)factory_dat.asn);
278 } else {
279 /* dtb suffix gets added in load script */
280 env_set("dtb_name", "am335x-draco");
281 }
282 #else
283 env_set("dtb_name", "am335x-draco");
284 #endif
285
286 return 0;
287 }
288 #endif
289
290 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
291 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
cpsw_control(int enabled)292 static void cpsw_control(int enabled)
293 {
294 /* VTP can be added here */
295
296 return;
297 }
298
299 static struct cpsw_slave_data cpsw_slaves[] = {
300 {
301 .slave_reg_ofs = 0x208,
302 .sliver_reg_ofs = 0xd80,
303 .phy_addr = 0,
304 .phy_if = PHY_INTERFACE_MODE_MII,
305 },
306 };
307
308 static struct cpsw_platform_data cpsw_data = {
309 .mdio_base = CPSW_MDIO_BASE,
310 .cpsw_base = CPSW_BASE,
311 .mdio_div = 0xff,
312 .channels = 4,
313 .cpdma_reg_ofs = 0x800,
314 .slaves = 1,
315 .slave_data = cpsw_slaves,
316 .ale_reg_ofs = 0xd00,
317 .ale_entries = 1024,
318 .host_port_reg_ofs = 0x108,
319 .hw_stats_reg_ofs = 0x900,
320 .bd_ram_ofs = 0x2000,
321 .mac_control = (1 << 5),
322 .control = cpsw_control,
323 .host_port_num = 0,
324 .version = CPSW_CTRL_VERSION_2,
325 };
326
327 #if defined(CONFIG_DRIVER_TI_CPSW) || \
328 (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
board_eth_init(struct bd_info * bis)329 int board_eth_init(struct bd_info *bis)
330 {
331 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
332 int n = 0;
333 int rv;
334
335 factoryset_env_set();
336
337 /* Set rgmii mode and enable rmii clock to be sourced from chip */
338 writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
339
340 rv = cpsw_register(&cpsw_data);
341 if (rv < 0)
342 printf("Error %d registering CPSW switch\n", rv);
343 else
344 n += rv;
345 return n;
346 }
347
do_switch_reset(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])348 static int do_switch_reset(struct cmd_tbl *cmdtp, int flag, int argc,
349 char *const argv[])
350 {
351 /* Reset SMSC LAN9303 switch for default configuration */
352 gpio_request(GPIO_LAN9303_NRST, "nRST");
353 gpio_direction_output(GPIO_LAN9303_NRST, 0);
354 /* assert active low reset for 200us */
355 udelay(200);
356 gpio_set_value(GPIO_LAN9303_NRST, 1);
357
358 return 0;
359 };
360
361 U_BOOT_CMD(
362 switch_rst, CONFIG_SYS_MAXARGS, 1, do_switch_reset,
363 "Reset LAN9303 switch via its reset pin",
364 ""
365 );
366 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
367 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
368
369 #ifdef CONFIG_NAND_CS_INIT
370 /* GPMC definitions for second nand cs1 */
371 static const u32 gpmc_nand_config[] = {
372 ETAMIN_NAND_GPMC_CONFIG1,
373 ETAMIN_NAND_GPMC_CONFIG2,
374 ETAMIN_NAND_GPMC_CONFIG3,
375 ETAMIN_NAND_GPMC_CONFIG4,
376 ETAMIN_NAND_GPMC_CONFIG5,
377 ETAMIN_NAND_GPMC_CONFIG6,
378 /*CONFIG7- computed as params */
379 };
380
board_nand_cs_init(void)381 static void board_nand_cs_init(void)
382 {
383 enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[1],
384 0x18000000, GPMC_SIZE_16M);
385 }
386 #endif
387
388 #include "../common/board.c"
389