1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2016 Atmel Corporation 4 * Wenyou.Yang <wenyou.yang@atmel.com> 5 */ 6 7 #ifndef __AT91_PMC_H__ 8 #define __AT91_PMC_H__ 9 10 #include <linux/bitops.h> 11 #include <linux/io.h> 12 13 /* Keep a range of 256 available clocks for every clock type. */ 14 #define AT91_TO_CLK_ID(_t, _i) (((_t) << 8) | ((_i) & 0xff)) 15 #define AT91_CLK_ID_TO_DID(_i) ((_i) & 0xff) 16 17 struct clk_range { 18 unsigned long min; 19 unsigned long max; 20 }; 21 22 struct clk_master_layout { 23 u32 offset; 24 u32 mask; 25 u8 pres_shift; 26 }; 27 28 extern const struct clk_master_layout at91rm9200_master_layout; 29 extern const struct clk_master_layout at91sam9x5_master_layout; 30 31 struct clk_master_characteristics { 32 struct clk_range output; 33 u32 divisors[5]; 34 u8 have_div3_pres; 35 }; 36 37 struct clk_pll_characteristics { 38 struct clk_range input; 39 int num_output; 40 const struct clk_range *output; 41 u16 *icpll; 42 u8 *out; 43 u8 upll : 1; 44 }; 45 46 struct clk_pll_layout { 47 u32 pllr_mask; 48 u32 mul_mask; 49 u32 frac_mask; 50 u32 div_mask; 51 u32 endiv_mask; 52 u8 mul_shift; 53 u8 frac_shift; 54 u8 div_shift; 55 u8 endiv_shift; 56 }; 57 58 struct clk_programmable_layout { 59 u8 pres_mask; 60 u8 pres_shift; 61 u8 css_mask; 62 u8 have_slck_mck; 63 u8 is_pres_direct; 64 }; 65 66 struct clk_pcr_layout { 67 u32 offset; 68 u32 cmd; 69 u32 div_mask; 70 u32 gckcss_mask; 71 u32 pid_mask; 72 }; 73 74 extern const struct clk_programmable_layout at91rm9200_programmable_layout; 75 extern const struct clk_programmable_layout at91sam9g45_programmable_layout; 76 extern const struct clk_programmable_layout at91sam9x5_programmable_layout; 77 78 extern const struct clk_ops at91_clk_ops; 79 80 struct clk *at91_clk_main_rc(void __iomem *reg, const char *name, 81 const char *parent_name); 82 struct clk *at91_clk_main_osc(void __iomem *reg, const char *name, 83 const char *parent_name, bool bypass); 84 struct clk *at91_clk_rm9200_main(void __iomem *reg, const char *name, 85 const char *parent_name); 86 struct clk *at91_clk_sam9x5_main(void __iomem *reg, const char *name, 87 const char * const *parent_names, int num_parents, 88 const u32 *mux_table, int type); 89 struct clk * 90 sam9x60_clk_register_div_pll(void __iomem *base, const char *name, 91 const char *parent_name, u8 id, 92 const struct clk_pll_characteristics *characteristics, 93 const struct clk_pll_layout *layout, bool critical); 94 struct clk * 95 sam9x60_clk_register_frac_pll(void __iomem *base, const char *name, 96 const char *parent_name, u8 id, 97 const struct clk_pll_characteristics *characteristics, 98 const struct clk_pll_layout *layout, bool critical); 99 struct clk * 100 at91_clk_register_master(void __iomem *base, const char *name, 101 const char * const *parent_names, int num_parents, 102 const struct clk_master_layout *layout, 103 const struct clk_master_characteristics *characteristics, 104 const u32 *mux_table); 105 struct clk * 106 at91_clk_sama7g5_register_master(void __iomem *base, const char *name, 107 const char * const *parent_names, int num_parents, 108 const u32 *mux_table, const u32 *clk_mux_table, 109 bool critical, u8 id); 110 struct clk * 111 at91_clk_register_utmi(void __iomem *base, struct udevice *dev, 112 const char *name, const char *parent_name); 113 struct clk * 114 at91_clk_sama7g5_register_utmi(void __iomem *base, const char *name, 115 const char *parent_name); 116 struct clk * 117 at91_clk_register_programmable(void __iomem *base, const char *name, 118 const char * const *parent_names, u8 num_parents, u8 id, 119 const struct clk_programmable_layout *layout, 120 const u32 *clk_mux_table, const u32 *mux_table); 121 struct clk * 122 at91_clk_register_system(void __iomem *base, const char *name, 123 const char *parent_name, u8 id); 124 struct clk * 125 at91_clk_register_peripheral(void __iomem *base, const char *name, 126 const char *parent_name, u32 id); 127 struct clk * 128 at91_clk_register_sam9x5_peripheral(void __iomem *base, 129 const struct clk_pcr_layout *layout, 130 const char *name, const char *parent_name, 131 u32 id, const struct clk_range *range); 132 struct clk * 133 at91_clk_register_generic(void __iomem *base, 134 const struct clk_pcr_layout *layout, const char *name, 135 const char * const *parent_names, 136 const u32 *clk_mux_table, const u32 *mux_table, 137 u8 num_parents, u8 id, const struct clk_range *range); 138 139 int at91_clk_mux_val_to_index(const u32 *table, u32 num_parents, u32 val); 140 int at91_clk_mux_index_to_val(const u32 *table, u32 num_parents, u32 index); 141 142 void pmc_read(void __iomem *base, unsigned int off, unsigned int *val); 143 void pmc_write(void __iomem *base, unsigned int off, unsigned int val); 144 void pmc_update_bits(void __iomem *base, unsigned int off, unsigned int mask, 145 unsigned int bits); 146 147 #endif 148