1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2007-2008
4  * Stelian Pop <stelian@popies.net>
5  * Lead Tech Design <www.leadtechdesign.com>
6  * Ilko Iliev <www.ronetix.at>
7  *
8  * Configuation settings for the RONETIX PM9263 board.
9  */
10 
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13 
14 /*
15  * SoC must be defined first, before hardware.h is included.
16  * In this case SoC is defined in boards.cfg.
17  */
18 #include <asm/hardware.h>
19 
20 /* ARM asynchronous clock */
21 
22 #define MASTER_PLL_DIV		6
23 #define MASTER_PLL_MUL		65
24 #define MAIN_PLL_DIV		2	/* 2 or 4 */
25 #define CONFIG_SYS_AT91_MAIN_CLOCK	18432000
26 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
27 
28 #define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9263"
29 
30 #define CONFIG_MACH_TYPE	MACH_TYPE_PM9263
31 
32 /* clocks */
33 #define CONFIG_SYS_MOR_VAL						\
34 		(AT91_PMC_MOR_MOSCEN |					\
35 		 (255 << 8))		/* Main Oscillator Start-up Time */
36 #define CONFIG_SYS_PLLAR_VAL						\
37 		(AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
38 		 AT91_PMC_PLLXR_OUT(3) |				\
39 		 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |	/* PLL Counter */\
40 		 (2 << 28) |		/* PLL Clock Frequency Range */	\
41 		 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
42 
43 #if (MAIN_PLL_DIV == 2)
44 /* PCK/2 = MCK Master Clock from PLLA */
45 #define	CONFIG_SYS_MCKR1_VAL		\
46 		(AT91_PMC_MCKR_CSS_SLOW |	\
47 		 AT91_PMC_MCKR_PRES_1 |	\
48 		 AT91_PMC_MCKR_MDIV_2)
49 /* PCK/2 = MCK Master Clock from PLLA */
50 #define	CONFIG_SYS_MCKR2_VAL		\
51 		(AT91_PMC_MCKR_CSS_PLLA |	\
52 		 AT91_PMC_MCKR_PRES_1 |	\
53 		 AT91_PMC_MCKR_MDIV_2)
54 #else
55 /* PCK/4 = MCK Master Clock from PLLA */
56 #define	CONFIG_SYS_MCKR1_VAL			\
57 		(AT91_PMC_MCKR_CSS_SLOW |		\
58 		 AT91_PMC_MCKR_PRES_1 |		\
59 		 AT91_PMC_MCKR_MDIV_4)
60 /* PCK/4 = MCK Master Clock from PLLA */
61 #define	CONFIG_SYS_MCKR2_VAL			\
62 		(AT91_PMC_MCKR_CSS_PLLA |		\
63 		 AT91_PMC_MCKR_PRES_1 |		\
64 		 AT91_PMC_MCKR_MDIV_4)
65 #endif
66 /* define PDC[31:16] as DATA[31:16] */
67 #define CONFIG_SYS_PIOD_PDR_VAL1	0xFFFF0000
68 /* no pull-up for D[31:16] */
69 #define CONFIG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
70 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
71 #define CONFIG_SYS_MATRIX_EBI0CSA_VAL					\
72 	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |	\
73 	 AT91_MATRIX_CSA_EBI_CS1A)
74 
75 /* SDRAM */
76 /* SDRAMC_MR Mode register */
77 #define CONFIG_SYS_SDRC_MR_VAL1		0
78 /* SDRAMC_TR - Refresh Timer register */
79 #define CONFIG_SYS_SDRC_TR_VAL1		0x3AA
80 /* SDRAMC_CR - Configuration register*/
81 #define CONFIG_SYS_SDRC_CR_VAL							\
82 		(AT91_SDRAMC_NC_9 |						\
83 		 AT91_SDRAMC_NR_13 |						\
84 		 AT91_SDRAMC_NB_4 |						\
85 		 AT91_SDRAMC_CAS_2 |						\
86 		 AT91_SDRAMC_DBW_32 |						\
87 		 (2 <<  8) |	/* tWR -  Write Recovery Delay */		\
88 		 (7 << 12) |	/* tRC -  Row Cycle Delay */			\
89 		 (2 << 16) |	/* tRP -  Row Precharge Delay */		\
90 		 (2 << 20) |	/* tRCD - Row to Column Delay */		\
91 		 (5 << 24) |	/* tRAS - Active to Precharge Delay */		\
92 		 (8 << 28))	/* tXSR - Exit Self Refresh to Active Delay */
93 
94 /* Memory Device Register -> SDRAM */
95 #define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
96 #define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
97 #define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
98 #define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
99 #define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
100 #define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
101 #define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
102 #define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
103 #define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
104 #define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
105 #define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
106 #define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
107 #define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
108 #define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
109 #define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
110 #define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
111 #define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
112 #define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */
113 
114 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
115 #define CONFIG_SYS_SMC0_SETUP0_VAL					\
116 		(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
117 		 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
118 #define CONFIG_SYS_SMC0_PULSE0_VAL					\
119 		(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
120 		 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
121 #define CONFIG_SYS_SMC0_CYCLE0_VAL	\
122 		(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
123 #define CONFIG_SYS_SMC0_MODE0_VAL				\
124 		(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |	\
125 		 AT91_SMC_MODE_DBW_16 |				\
126 		 AT91_SMC_MODE_TDF |				\
127 		 AT91_SMC_MODE_TDF_CYCLE(6))
128 
129 /* user reset enable */
130 #define CONFIG_SYS_RSTC_RMR_VAL			\
131 		(AT91_RSTC_KEY |		\
132 		AT91_RSTC_CR_PROCRST |		\
133 		AT91_RSTC_MR_ERSTL(1) |	\
134 		AT91_RSTC_MR_ERSTL(2))
135 
136 /* Disable Watchdog */
137 #define CONFIG_SYS_WDTC_WDMR_VAL				\
138 		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
139 		 AT91_WDT_MR_WDV(0xfff) |					\
140 		 AT91_WDT_MR_WDDIS |				\
141 		 AT91_WDT_MR_WDD(0xfff))
142 
143 #define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs */
144 #define CONFIG_SETUP_MEMORY_TAGS 1
145 #define CONFIG_INITRD_TAG	1
146 
147 #undef CONFIG_SKIP_LOWLEVEL_INIT
148 #define CONFIG_USER_LOWLEVEL_INIT	1
149 
150 /*
151  * Hardware drivers
152  */
153 /* LCD */
154 #define LCD_BPP				LCD_COLOR8
155 #define CONFIG_LCD_LOGO			1
156 #undef LCD_TEST_PATTERN
157 #define CONFIG_LCD_INFO			1
158 #define CONFIG_LCD_INFO_BELOW_LOGO	1
159 #define CONFIG_ATMEL_LCD		1
160 #define CONFIG_ATMEL_LCD_BGR555		1
161 
162 #define CONFIG_LCD_IN_PSRAM		1
163 
164 /*
165  * BOOTP options
166  */
167 #define CONFIG_BOOTP_BOOTFILESIZE	1
168 
169 /* SDRAM */
170 #define PHYS_SDRAM		0x20000000
171 #define PHYS_SDRAM_SIZE		0x04000000	/* 64 megs */
172 
173 /* NOR flash, if populated */
174 #define PHYS_FLASH_1			0x10000000
175 #define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
176 #define CONFIG_SYS_MAX_FLASH_SECT	256
177 #define CONFIG_SYS_MAX_FLASH_BANKS	1
178 
179 /* NAND flash */
180 #ifdef CONFIG_CMD_NAND
181 #define CONFIG_SYS_MAX_NAND_DEVICE	1
182 #define CONFIG_SYS_NAND_BASE		0x40000000
183 #define CONFIG_SYS_NAND_DBW_8		1
184 /* our ALE is AD21 */
185 #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
186 /* our CLE is AD22 */
187 #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
188 #define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PD(15)
189 #define CONFIG_SYS_NAND_READY_PIN	GPIO_PIN_PB(30)
190 
191 #endif
192 
193 #define CONFIG_JFFS2_NAND		1
194 #define CONFIG_JFFS2_DEV		"nand0" /* NAND device jffs2 lives on */
195 #define CONFIG_JFFS2_PART_OFFSET	0	/* start of jffs2 partition */
196 #define CONFIG_JFFS2_PART_SIZE		(256 * 1024 * 1024) /* partition size*/
197 
198 /* PSRAM */
199 #define	PHYS_PSRAM			0x70000000
200 #define	PHYS_PSRAM_SIZE			0x00400000	/* 4MB */
201 /* Slave EBI1, PSRAM connected */
202 #define CONFIG_PSRAM_SCFG		(AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY	| \
203 					 AT91_MATRIX_SCFG_FIXED_DEFMSTR(5)	| \
204 					 AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED	| \
205 					 AT91_MATRIX_SCFG_SLOT_CYCLE(255))
206 
207 /* Ethernet */
208 #define CONFIG_MACB			1
209 #define CONFIG_RMII			1
210 #define CONFIG_NET_RETRY_COUNT		20
211 #define CONFIG_RESET_PHY_R		1
212 
213 /* USB */
214 #define CONFIG_USB_ATMEL
215 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
216 #define CONFIG_USB_OHCI_NEW			1
217 #define CONFIG_SYS_USB_OHCI_CPU_INIT		1
218 #define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000	/* AT91SAM9263_UHP_BASE */
219 #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
220 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
221 
222 #define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
223 
224 #define CONFIG_SYS_USE_FLASH	1
225 #undef CONFIG_SYS_USE_DATAFLASH
226 #undef CONFIG_SYS_USE_NANDFLASH
227 
228 #ifdef CONFIG_SYS_USE_DATAFLASH
229 
230 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
231 #define CONFIG_BOOTCOMMAND	"sf probe 0; " \
232 				"sf read 0x22000000 0x84000 0x294000; " \
233 				"bootm 0x22000000"
234 
235 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */
236 
237 /* bootstrap + u-boot + env + linux in nandflash */
238 #define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0xA0000 0x200000; bootm"
239 
240 #elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */
241 /* JFFS Partition offset set */
242 #define CONFIG_SYS_JFFS2_FIRST_BANK	0
243 #define CONFIG_SYS_JFFS2_NUM_BANKS	1
244 
245 /* 512k reserved for u-boot */
246 #define CONFIG_SYS_JFFS2_FIRST_SECTOR	11
247 
248 #define CONFIG_BOOTCOMMAND		"run flashboot"
249 #define CONFIG_ROOTPATH			"/ronetix/rootfs"
250 
251 #define CONFIG_CON_ROT			"fbcon=rotate:3 "
252 
253 #define CONFIG_EXTRA_ENV_SETTINGS				\
254 	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0"				\
255 	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"			\
256 	"partition=nand0,0\0"					\
257 	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"	\
258 	"nfsargs=setenv bootargs root=/dev/nfs rw "		\
259 		CONFIG_CON_ROT					\
260 		"nfsroot=$(serverip):$(rootpath) $(mtdparts)\0"	\
261 	"addip=setenv bootargs $(bootargs) "			\
262 		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
263 		":$(hostname):eth0:off\0"			\
264 	"ramboot=tftpboot 0x22000000 vmImage;"			\
265 		"run ramargs;run addip;bootm 22000000\0"	\
266 	"nfsboot=tftpboot 0x22000000 vmImage;"			\
267 		"run nfsargs;run addip;bootm 22000000\0"	\
268 	"flashboot=run ramargs;run addip;bootm 0x10050000\0"	\
269 	""
270 
271 #else
272 #error "Undefined memory device"
273 #endif
274 
275 /*
276  * Size of malloc() pool
277  */
278 #define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
279 
280 #define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM
281 #define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \
282 				GENERATED_GBL_DATA_SIZE)
283 
284 #endif
285