1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
4 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
5 */
6
7 /*
8 * PCI Configuration space access support
9 */
10 #include <common.h>
11 #include <pci.h>
12 #include <asm/io.h>
13 #include <asm/immap.h>
14 #include <linux/delay.h>
15
16 #if defined(CONFIG_PCI)
17 /* System RAM mapped over PCI */
18 #define CONFIG_SYS_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
19 #define CONFIG_SYS_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
20 #define CONFIG_SYS_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
21
22 #define cfg_read(val, addr, type, op) *val = op((type)(addr));
23 #define cfg_write(val, addr, type, op) op((type *)(addr), (val));
24
25 #define PCI_OP(rw, size, type, op, mask) \
26 int pci_##rw##_cfg_##size(struct pci_controller *hose, \
27 pci_dev_t dev, int offset, type val) \
28 { \
29 u32 addr = 0; \
30 u16 cfg_type = 0; \
31 addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \
32 out_be32(hose->cfg_addr, addr); \
33 cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
34 out_be32(hose->cfg_addr, addr & 0x7fffffff); \
35 return 0; \
36 }
37
38 PCI_OP(read, byte, u8 *, in_8, 3)
39 PCI_OP(read, word, u16 *, in_le16, 2)
40 PCI_OP(read, dword, u32 *, in_le32, 0)
41 PCI_OP(write, byte, u8, out_8, 3)
42 PCI_OP(write, word, u16, out_le16, 2)
43 PCI_OP(write, dword, u32, out_le32, 0)
44
pci_mcf5445x_init(struct pci_controller * hose)45 void pci_mcf5445x_init(struct pci_controller *hose)
46 {
47 pci_t *pci = (pci_t *)MMAP_PCI;
48 pciarb_t *pciarb = (pciarb_t *)MMAP_PCIARB;
49 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
50 u32 barEn = 0;
51
52 out_be32(&pciarb->acr, 0x001f001f);
53
54 /* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
55 PCIREQ2, PCIGNT2 */
56 out_be16(&gpio->par_pci,
57 GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 |
58 GPIO_PAR_PCI_GNT1 | GPIO_PAR_PCI_GNT0 |
59 GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 |
60 GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0);
61
62 /* Assert reset bit */
63 setbits_be32(&pci->gscr, PCI_GSCR_PR);
64
65 setbits_be32(&pci->tcr1, PCI_TCR1_P);
66
67 /* Initiator windows */
68 out_be32(&pci->iw0btar,
69 CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16));
70 out_be32(&pci->iw1btar,
71 CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16));
72 out_be32(&pci->iw2btar,
73 CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16));
74
75 out_be32(&pci->iwcr,
76 PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
77 PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO);
78
79 out_be32(&pci->icr, 0);
80
81 /* Enable bus master and mem access */
82 out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M);
83
84 /* Cache line size and master latency */
85 out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8));
86 out_be32(&pci->cr2, 0);
87
88 #ifdef CONFIG_SYS_PCI_BAR0
89 out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0));
90 out_be32(&pci->tbatr0, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN);
91 barEn |= PCI_TCR2_B0E;
92 #endif
93 #ifdef CONFIG_SYS_PCI_BAR1
94 out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1));
95 out_be32(&pci->tbatr1, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN);
96 barEn |= PCI_TCR2_B1E;
97 #endif
98 #ifdef CONFIG_SYS_PCI_BAR2
99 out_be32(&pci->bar2, PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2));
100 out_be32(&pci->tbatr2, CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN);
101 barEn |= PCI_TCR2_B2E;
102 #endif
103 #ifdef CONFIG_SYS_PCI_BAR3
104 out_be32(&pci->bar3, PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3));
105 out_be32(&pci->tbatr3, CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN);
106 barEn |= PCI_TCR2_B3E;
107 #endif
108 #ifdef CONFIG_SYS_PCI_BAR4
109 out_be32(&pci->bar4, PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4));
110 out_be32(&pci->tbatr4, CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN);
111 barEn |= PCI_TCR2_B4E;
112 #endif
113 #ifdef CONFIG_SYS_PCI_BAR5
114 out_be32(&pci->bar5, PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5));
115 out_be32(&pci->tbatr5, CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN);
116 barEn |= PCI_TCR2_B5E;
117 #endif
118
119 out_be32(&pci->tcr2, barEn);
120
121 /* Deassert reset bit */
122 clrbits_be32(&pci->gscr, PCI_GSCR_PR);
123 udelay(1000);
124
125 /* Enable PCI bus master support */
126 hose->first_busno = 0;
127 hose->last_busno = 0xff;
128
129 pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS,
130 CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
131
132 pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS,
133 CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
134
135 pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS,
136 CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE,
137 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
138
139 hose->region_count = 3;
140
141 hose->cfg_addr = &(pci->car);
142 hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS;
143
144 pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
145 pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
146 pci_write_cfg_dword);
147
148 /* Hose scan */
149 pci_register_hose(hose);
150 hose->last_busno = pci_hose_scan(hose);
151 }
152 #endif /* CONFIG_PCI */
153