1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2014 - 2015 Xilinx, Inc. 4 * Michal Simek <michal.simek@xilinx.com> 5 */ 6 7 #ifndef _ASM_ARCH_HARDWARE_H 8 #define _ASM_ARCH_HARDWARE_H 9 10 #ifndef __ASSEMBLY__ 11 #include <linux/bitops.h> 12 #endif 13 14 #define ZYNQMP_TCM_BASE_ADDR 0xFFE00000 15 #define ZYNQMP_TCM_SIZE 0x40000 16 17 #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000 18 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000 19 #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0 20 #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8 21 22 #define ZYNQMP_AMS_PS_SYSMON_BASEADDR 0XFFA50800 23 #define ZYNQMP_AMS_PS_SYSMON_ANALOG_BUS ((ZYNQMP_AMS_PS_SYSMON_BASEADDR) \ 24 + 0x00000114) 25 #define ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL 0x00003210 26 27 #define PS_MODE0 BIT(0) 28 #define PS_MODE1 BIT(1) 29 #define PS_MODE2 BIT(2) 30 #define PS_MODE3 BIT(3) 31 32 #define RESET_REASON_DEBUG_SYS BIT(6) 33 #define RESET_REASON_SOFT BIT(5) 34 #define RESET_REASON_SRST BIT(4) 35 #define RESET_REASON_PSONLY BIT(3) 36 #define RESET_REASON_PMU BIT(2) 37 #define RESET_REASON_INTERNAL BIT(1) 38 #define RESET_REASON_EXTERNAL BIT(0) 39 40 struct crlapb_regs { 41 u32 reserved0[36]; 42 u32 cpu_r5_ctrl; /* 0x90 */ 43 u32 reserved1[37]; 44 u32 timestamp_ref_ctrl; /* 0x128 */ 45 u32 reserved2[53]; 46 u32 boot_mode; /* 0x200 */ 47 u32 reserved3_0[7]; 48 u32 reset_reason; /* 0x220 */ 49 u32 reserved3_1[6]; 50 u32 rst_lpd_top; /* 0x23C */ 51 u32 reserved4[4]; 52 u32 boot_pin_ctrl; /* 0x250 */ 53 u32 reserved5[21]; 54 }; 55 56 #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) 57 58 #define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000 59 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1 60 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2 61 62 struct iou_scntr_secure { 63 u32 counter_control_register; 64 u32 reserved0[7]; 65 u32 base_frequency_id_register; 66 }; 67 68 #define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE) 69 70 /* Bootmode setting values */ 71 #define BOOT_MODES_MASK 0x0000000F 72 #define QSPI_MODE_24BIT 0x00000001 73 #define QSPI_MODE_32BIT 0x00000002 74 #define SD_MODE 0x00000003 /* sd 0 */ 75 #define SD_MODE1 0x00000005 /* sd 1 */ 76 #define NAND_MODE 0x00000004 77 #define EMMC_MODE 0x00000006 78 #define USB_MODE 0x00000007 79 #define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */ 80 #define JTAG_MODE 0x00000000 81 #define BOOT_MODE_USE_ALT 0x100 82 #define BOOT_MODE_ALT_SHIFT 12 83 /* SW secondary boot modes 0xa - 0xd */ 84 #define SW_USBHOST_MODE 0x0000000A 85 #define SW_SATA_MODE 0x0000000B 86 87 #define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000 88 89 struct iou_slcr_regs { 90 u32 mio_pin[78]; 91 u32 reserved[442]; 92 }; 93 94 #define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR) 95 96 #define ZYNQMP_RPU_BASEADDR 0xFF9A0000 97 98 struct rpu_regs { 99 u32 rpu_glbl_ctrl; 100 u32 reserved0[63]; 101 u32 rpu0_cfg; /* 0x100 */ 102 u32 reserved1[63]; 103 u32 rpu1_cfg; /* 0x200 */ 104 }; 105 106 #define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR) 107 108 #define ZYNQMP_CRF_APB_BASEADDR 0xFD1A0000 109 110 struct crfapb_regs { 111 u32 reserved0[65]; 112 u32 rst_fpd_apu; /* 0x104 */ 113 u32 reserved1; 114 }; 115 116 #define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR) 117 118 #define ZYNQMP_APU_BASEADDR 0xFD5C0000 119 120 struct apu_regs { 121 u32 reserved0[16]; 122 u32 rvbar_addr0_l; /* 0x40 */ 123 u32 rvbar_addr0_h; /* 0x44 */ 124 u32 reserved1[20]; 125 }; 126 127 #define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR) 128 129 /* Board version value */ 130 #define ZYNQMP_CSU_BASEADDR 0xFFCA0000 131 #define ZYNQMP_CSU_VERSION_SILICON 0x0 132 #define ZYNQMP_CSU_VERSION_QEMU 0x3 133 134 #define ZYNQMP_CSU_VERSION_EMPTY_SHIFT 20 135 136 #define ZYNQMP_SILICON_VER_MASK 0xF 137 #define ZYNQMP_SILICON_VER_SHIFT 0 138 139 struct csu_regs { 140 u32 reserved0[4]; 141 u32 multi_boot; 142 u32 reserved1[11]; 143 u32 idcode; 144 u32 version; 145 }; 146 147 #define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR) 148 149 #define ZYNQMP_PMU_BASEADDR 0xFFD80000 150 151 struct pmu_regs { 152 u32 reserved[18]; 153 u32 gen_storage6; /* 0x48 */ 154 }; 155 156 #define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR) 157 158 #endif /* _ASM_ARCH_HARDWARE_H */ 159