1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * T4240 Silicon/SoC Device Tree Source (pre include)
4 *
5 * Copyright 2013 Freescale Semiconductor Inc.
6 * Copyright 2019-2020 NXP
7 */
8
9/dts-v1/;
10
11/include/ "e6500_power_isa.dtsi"
12
13/ {
14	#address-cells = <2>;
15	#size-cells = <2>;
16	interrupt-parent = <&mpic>;
17
18	cpus {
19		#address-cells = <1>;
20		#size-cells = <0>;
21
22		cpu0: PowerPC,e6500@0 {
23			device_type = "cpu";
24			reg = <0 1>;
25			fsl,portid-mapping = <0x80000000>;
26		};
27		cpu1: PowerPC,e6500@2 {
28			device_type = "cpu";
29			reg = <2 3>;
30			fsl,portid-mapping = <0x80000000>;
31		};
32		cpu2: PowerPC,e6500@4 {
33			device_type = "cpu";
34			reg = <4 5>;
35			fsl,portid-mapping = <0x80000000>;
36		};
37		cpu3: PowerPC,e6500@6 {
38			device_type = "cpu";
39			reg = <6 7>;
40			fsl,portid-mapping = <0x80000000>;
41		};
42		cpu4: PowerPC,e6500@8 {
43			device_type = "cpu";
44			reg = <8 9>;
45			fsl,portid-mapping = <0x80000000>;
46		};
47		cpu5: PowerPC,e6500@10 {
48			device_type = "cpu";
49			reg = <10 11>;
50			fsl,portid-mapping = <0x80000000>;
51		};
52		cpu6: PowerPC,e6500@12 {
53			device_type = "cpu";
54			reg = <12 13>;
55			fsl,portid-mapping = <0x80000000>;
56		};
57		cpu7: PowerPC,e6500@14 {
58			device_type = "cpu";
59			reg = <14 15>;
60			fsl,portid-mapping = <0x80000000>;
61		};
62		cpu8: PowerPC,e6500@16 {
63			device_type = "cpu";
64			reg = <16 17>;
65			fsl,portid-mapping = <0x80000000>;
66		};
67		cpu9: PowerPC,e6500@18 {
68			device_type = "cpu";
69			reg = <18 19>;
70			fsl,portid-mapping = <0x80000000>;
71		};
72		cpu10: PowerPC,e6500@20 {
73			device_type = "cpu";
74			reg = <20 21>;
75			fsl,portid-mapping = <0x80000000>;
76		};
77		cpu11: PowerPC,e6500@22 {
78			device_type = "cpu";
79			reg = <22 23>;
80			fsl,portid-mapping = <0x80000000>;
81		};
82	};
83
84	soc: soc@ffe000000 {
85		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
86		reg = <0xf 0xfe000000 0 0x00001000>;
87		#address-cells = <1>;
88		#size-cells = <1>;
89		device_type = "soc";
90		compatible = "simple-bus";
91
92		mpic: pic@40000 {
93			interrupt-controller;
94			#address-cells = <0>;
95			#interrupt-cells = <4>;
96			reg = <0x40000 0x40000>;
97			compatible = "fsl,mpic";
98			device_type = "open-pic";
99			clock-frequency = <0x0>;
100		};
101
102		espi0: spi@110000 {
103			compatible = "fsl,mpc8536-espi";
104			#address-cells = <1>;
105			#size-cells = <0>;
106			reg = <0x110000 0x1000>;
107			fsl,espi-num-chipselects = <4>;
108			status = "disabled";
109		};
110
111		usb@210000 {
112			compatible = "fsl-usb2-mph";
113			reg = <0x210000 0x1000>;
114			phy_type = "utmi";
115		};
116
117		usb@211000 {
118			compatible = "fsl-usb2-dr";
119			reg = <0x211000 0x1000>;
120			phy_type = "utmi";
121		};
122
123		sata: sata@220000 {
124			compatible = "fsl,pq-sata-v2";
125			reg = <0x220000 0x1000>;
126			interrupts = <68 0x2 0 0>;
127			sata-offset = <0x1000>;
128			sata-number = <2>;
129			sata-fpdma = <0>;
130		};
131
132		esdhc: esdhc@114000 {
133			compatible = "fsl,esdhc";
134			reg = <0x114000 0x1000>;
135			clock-frequency = <0>;
136		};
137
138		/include/ "qoriq-i2c-0.dtsi"
139		/include/ "qoriq-i2c-1.dtsi"
140	};
141
142	pcie@ffe240000 {
143		compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
144		reg = <0xf 0xfe240000 0x0 0x4000>;   /* registers */
145		law_trgt_if = <0>;
146		#address-cells = <3>;
147		#size-cells = <2>;
148		device_type = "pci";
149		bus-range = <0x0 0xff>;
150		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
151			  0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
152	};
153
154	pcie@ffe250000 {
155		compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
156		reg = <0xf 0xfe250000 0x0 0x4000>;   /* registers */
157		law_trgt_if = <1>;
158		#address-cells = <3>;
159		#size-cells = <2>;
160		device_type = "pci";
161		bus-range = <0x0 0xff>;
162		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
163			  0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
164	};
165
166	pcie@ffe260000 {
167		compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
168		reg = <0xf 0xfe260000 0x0 0x4000>;   /* registers */
169		law_trgt_if = <2>;
170		#address-cells = <3>;
171		#size-cells = <2>;
172		device_type = "pci";
173		bus-range = <0x0 0xff>;
174		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
175			  0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
176	};
177
178	pcie@ffe270000 {
179		compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
180		reg = <0xf 0xfe270000 0x0 0x4000>;   /* registers */
181		law_trgt_if = <3>;
182		#address-cells = <3>;
183		#size-cells = <2>;
184		device_type = "pci";
185		bus-range = <0x0 0xff>;
186		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000   /* downstream I/O */
187			  0x02000000 0x0 0xe0000000 0xc 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */
188	};
189};
190