1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2007 Freescale Semiconductor, Inc.
4 * Kevin Lam <kevin.lam@freescale.com>
5 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
6 */
7
8 #include <common.h>
9 #include <env.h>
10 #include <hwconfig.h>
11 #include <i2c.h>
12 #include <init.h>
13 #include <asm/bitops.h>
14 #include <asm/global_data.h>
15 #include <asm/io.h>
16 #include <asm/fsl_mpc83xx_serdes.h>
17 #include <fdt_support.h>
18 #include <spd_sdram.h>
19 #include <vsc7385.h>
20 #include <fsl_esdhc.h>
21 #include <linux/delay.h>
22
23 DECLARE_GLOBAL_DATA_PTR;
24
25 #if defined(CONFIG_SYS_DRAM_TEST)
26 int
testdram(void)27 testdram(void)
28 {
29 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
30 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
31 uint *p;
32
33 printf("Testing DRAM from 0x%08x to 0x%08x\n",
34 CONFIG_SYS_MEMTEST_START,
35 CONFIG_SYS_MEMTEST_END);
36
37 printf("DRAM test phase 1:\n");
38 for (p = pstart; p < pend; p++)
39 *p = 0xaaaaaaaa;
40
41 for (p = pstart; p < pend; p++) {
42 if (*p != 0xaaaaaaaa) {
43 printf("DRAM test fails at: %08x\n", (uint) p);
44 return 1;
45 }
46 }
47
48 printf("DRAM test phase 2:\n");
49 for (p = pstart; p < pend; p++)
50 *p = 0x55555555;
51
52 for (p = pstart; p < pend; p++) {
53 if (*p != 0x55555555) {
54 printf("DRAM test fails at: %08x\n", (uint) p);
55 return 1;
56 }
57 }
58
59 printf("DRAM test passed.\n");
60 return 0;
61 }
62 #endif
63
64 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
65 void ddr_enable_ecc(unsigned int dram_size);
66 #endif
67 int fixed_sdram(void);
68
dram_init(void)69 int dram_init(void)
70 {
71 immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
72 u32 msize = 0;
73
74 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
75 return -ENXIO;
76
77 #if defined(CONFIG_SPD_EEPROM)
78 msize = spd_sdram();
79 #else
80 msize = fixed_sdram();
81 #endif
82
83 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
84 /* Initialize DDR ECC byte */
85 ddr_enable_ecc(msize * 1024 * 1024);
86 #endif
87 /* return total bus DDR size(bytes) */
88 gd->ram_size = msize * 1024 * 1024;
89
90 return 0;
91 }
92
93 #if !defined(CONFIG_SPD_EEPROM)
94 /*************************************************************************
95 * fixed sdram init -- doesn't use serial presence detect.
96 ************************************************************************/
fixed_sdram(void)97 int fixed_sdram(void)
98 {
99 immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
100 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
101 u32 msize_log2 = __ilog2(msize);
102
103 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
104 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
105
106 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
107 udelay(50000);
108
109 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
110 udelay(1000);
111
112 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
113 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
114 udelay(1000);
115
116 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
117 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
118 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
119 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
120 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
121 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
122 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
123 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
124 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
125 sync();
126 udelay(1000);
127
128 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
129 udelay(2000);
130 return CONFIG_SYS_DDR_SIZE;
131 }
132 #endif /*!CONFIG_SYS_SPD_EEPROM */
133
checkboard(void)134 int checkboard(void)
135 {
136 puts("Board: Freescale MPC837xERDB\n");
137 return 0;
138 }
139
board_early_init_f(void)140 int board_early_init_f(void)
141 {
142 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
143 #ifdef CONFIG_FSL_SERDES
144 u32 spridr = in_be32(&immr->sysconf.spridr);
145
146 /* we check only part num, and don't look for CPU revisions */
147 switch (PARTID_NO_E(spridr)) {
148 case SPR_8377:
149 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
150 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
151 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
152 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
153 break;
154 case SPR_8378:
155 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
156 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
157 break;
158 case SPR_8379:
159 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
160 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
161 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
162 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
163 break;
164 default:
165 printf("serdes not configured: unknown CPU part number: "
166 "%04x\n", spridr >> 16);
167 break;
168 }
169 #endif /* CONFIG_FSL_SERDES */
170
171 #ifdef CONFIG_FSL_ESDHC
172 clrsetbits_be32(&immr->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
173 clrsetbits_be32(&immr->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
174 #endif
175 return 0;
176 }
177
178 #ifdef CONFIG_FSL_ESDHC
179 #if !(CONFIG_IS_ENABLED(DM_MMC))
board_mmc_init(struct bd_info * bd)180 int board_mmc_init(struct bd_info *bd)
181 {
182 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
183 char buffer[HWCONFIG_BUFFER_SIZE] = {0};
184 int esdhc_hwconfig_enabled = 0;
185
186 if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
187 esdhc_hwconfig_enabled = hwconfig_f("esdhc", buffer);
188
189 if (esdhc_hwconfig_enabled == 0)
190 return 0;
191
192 clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
193 clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
194
195 return fsl_esdhc_mmc_init(bd);
196 }
197 #endif
198 #endif
199
200 /*
201 * Miscellaneous late-boot configurations
202 *
203 * If a VSC7385 microcode image is present, then upload it.
204 */
misc_init_r(void)205 int misc_init_r(void)
206 {
207 int rc = 0;
208
209 #ifdef CONFIG_VSC7385_IMAGE
210 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
211 CONFIG_VSC7385_IMAGE_SIZE)) {
212 puts("Failure uploading VSC7385 microcode.\n");
213 rc = 1;
214 }
215 #endif
216
217 return rc;
218 }
219
220 #if defined(CONFIG_OF_BOARD_SETUP)
221
ft_board_setup(void * blob,struct bd_info * bd)222 int ft_board_setup(void *blob, struct bd_info *bd)
223 {
224 #ifdef CONFIG_PCI
225 ft_pci_setup(blob, bd);
226 #endif
227 ft_cpu_setup(blob, bd);
228 fsl_fdt_fixup_dr_usb(blob, bd);
229 fdt_fixup_esdhc(blob, bd);
230
231 return 0;
232 }
233 #endif /* CONFIG_OF_BOARD_SETUP */
234