1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2010-2011 Calxeda, Inc.
4 */
5
6 #include <common.h>
7 #include <malloc.h>
8 #include <net.h>
9 #include <linux/compiler.h>
10 #include <linux/delay.h>
11 #include <linux/err.h>
12 #include <asm/io.h>
13 #include <dm.h>
14 #include <dm/device-internal.h> /* for dev_set_priv() */
15
16 #define TX_NUM_DESC 1
17 #define RX_NUM_DESC 32
18
19 #define MAC_TIMEOUT (5*CONFIG_SYS_HZ)
20
21 #define ETH_BUF_SZ 2048
22 #define TX_BUF_SZ (ETH_BUF_SZ * TX_NUM_DESC)
23 #define RX_BUF_SZ (ETH_BUF_SZ * RX_NUM_DESC)
24
25 #define RXSTART 0x00000002
26 #define TXSTART 0x00002000
27
28 #define RXENABLE 0x00000004
29 #define TXENABLE 0x00000008
30
31 #define XGMAC_CONTROL_SPD 0x40000000
32 #define XGMAC_CONTROL_SPD_MASK 0x60000000
33 #define XGMAC_CONTROL_SARC 0x10000000
34 #define XGMAC_CONTROL_SARK_MASK 0x18000000
35 #define XGMAC_CONTROL_CAR 0x04000000
36 #define XGMAC_CONTROL_CAR_MASK 0x06000000
37 #define XGMAC_CONTROL_CAR_SHIFT 25
38 #define XGMAC_CONTROL_DP 0x01000000
39 #define XGMAC_CONTROL_WD 0x00800000
40 #define XGMAC_CONTROL_JD 0x00400000
41 #define XGMAC_CONTROL_JE 0x00100000
42 #define XGMAC_CONTROL_LM 0x00001000
43 #define XGMAC_CONTROL_IPC 0x00000400
44 #define XGMAC_CONTROL_ACS 0x00000080
45 #define XGMAC_CONTROL_DDIC 0x00000010
46 #define XGMAC_CONTROL_TE 0x00000008
47 #define XGMAC_CONTROL_RE 0x00000004
48
49 #define XGMAC_DMA_BUSMODE_RESET 0x00000001
50 #define XGMAC_DMA_BUSMODE_DSL 0x00000004
51 #define XGMAC_DMA_BUSMODE_DSL_MASK 0x0000007c
52 #define XGMAC_DMA_BUSMODE_DSL_SHIFT 2
53 #define XGMAC_DMA_BUSMODE_ATDS 0x00000080
54 #define XGMAC_DMA_BUSMODE_PBL_MASK 0x00003f00
55 #define XGMAC_DMA_BUSMODE_PBL_SHIFT 8
56 #define XGMAC_DMA_BUSMODE_FB 0x00010000
57 #define XGMAC_DMA_BUSMODE_USP 0x00800000
58 #define XGMAC_DMA_BUSMODE_8PBL 0x01000000
59 #define XGMAC_DMA_BUSMODE_AAL 0x02000000
60
61 #define XGMAC_DMA_AXIMODE_ENLPI 0x80000000
62 #define XGMAC_DMA_AXIMODE_MGK 0x40000000
63 #define XGMAC_DMA_AXIMODE_WROSR 0x00100000
64 #define XGMAC_DMA_AXIMODE_WROSR_MASK 0x00F00000
65 #define XGMAC_DMA_AXIMODE_WROSR_SHIFT 20
66 #define XGMAC_DMA_AXIMODE_RDOSR 0x00010000
67 #define XGMAC_DMA_AXIMODE_RDOSR_MASK 0x000F0000
68 #define XGMAC_DMA_AXIMODE_RDOSR_SHIFT 16
69 #define XGMAC_DMA_AXIMODE_AAL 0x00001000
70 #define XGMAC_DMA_AXIMODE_BLEN256 0x00000080
71 #define XGMAC_DMA_AXIMODE_BLEN128 0x00000040
72 #define XGMAC_DMA_AXIMODE_BLEN64 0x00000020
73 #define XGMAC_DMA_AXIMODE_BLEN32 0x00000010
74 #define XGMAC_DMA_AXIMODE_BLEN16 0x00000008
75 #define XGMAC_DMA_AXIMODE_BLEN8 0x00000004
76 #define XGMAC_DMA_AXIMODE_BLEN4 0x00000002
77 #define XGMAC_DMA_AXIMODE_UNDEF 0x00000001
78
79 #define XGMAC_CORE_OMR_RTC_SHIFT 3
80 #define XGMAC_CORE_OMR_RTC_MASK 0x00000018
81 #define XGMAC_CORE_OMR_RTC 0x00000010
82 #define XGMAC_CORE_OMR_RSF 0x00000020
83 #define XGMAC_CORE_OMR_DT 0x00000040
84 #define XGMAC_CORE_OMR_FEF 0x00000080
85 #define XGMAC_CORE_OMR_EFC 0x00000100
86 #define XGMAC_CORE_OMR_RFA_SHIFT 9
87 #define XGMAC_CORE_OMR_RFA_MASK 0x00000E00
88 #define XGMAC_CORE_OMR_RFD_SHIFT 12
89 #define XGMAC_CORE_OMR_RFD_MASK 0x00007000
90 #define XGMAC_CORE_OMR_TTC_SHIFT 16
91 #define XGMAC_CORE_OMR_TTC_MASK 0x00030000
92 #define XGMAC_CORE_OMR_TTC 0x00020000
93 #define XGMAC_CORE_OMR_FTF 0x00100000
94 #define XGMAC_CORE_OMR_TSF 0x00200000
95
96 #define FIFO_MINUS_1K 0x0
97 #define FIFO_MINUS_2K 0x1
98 #define FIFO_MINUS_3K 0x2
99 #define FIFO_MINUS_4K 0x3
100 #define FIFO_MINUS_6K 0x4
101 #define FIFO_MINUS_8K 0x5
102 #define FIFO_MINUS_12K 0x6
103 #define FIFO_MINUS_16K 0x7
104
105 #define XGMAC_CORE_FLOW_PT_SHIFT 16
106 #define XGMAC_CORE_FLOW_PT_MASK 0xFFFF0000
107 #define XGMAC_CORE_FLOW_PT 0x00010000
108 #define XGMAC_CORE_FLOW_DZQP 0x00000080
109 #define XGMAC_CORE_FLOW_PLT_SHIFT 4
110 #define XGMAC_CORE_FLOW_PLT_MASK 0x00000030
111 #define XGMAC_CORE_FLOW_PLT 0x00000010
112 #define XGMAC_CORE_FLOW_UP 0x00000008
113 #define XGMAC_CORE_FLOW_RFE 0x00000004
114 #define XGMAC_CORE_FLOW_TFE 0x00000002
115 #define XGMAC_CORE_FLOW_FCB 0x00000001
116
117 /* XGMAC Descriptor Defines */
118 #define MAX_DESC_BUF_SZ (0x2000 - 8)
119
120 #define RXDESC_EXT_STATUS 0x00000001
121 #define RXDESC_CRC_ERR 0x00000002
122 #define RXDESC_RX_ERR 0x00000008
123 #define RXDESC_RX_WDOG 0x00000010
124 #define RXDESC_FRAME_TYPE 0x00000020
125 #define RXDESC_GIANT_FRAME 0x00000080
126 #define RXDESC_LAST_SEG 0x00000100
127 #define RXDESC_FIRST_SEG 0x00000200
128 #define RXDESC_VLAN_FRAME 0x00000400
129 #define RXDESC_OVERFLOW_ERR 0x00000800
130 #define RXDESC_LENGTH_ERR 0x00001000
131 #define RXDESC_SA_FILTER_FAIL 0x00002000
132 #define RXDESC_DESCRIPTOR_ERR 0x00004000
133 #define RXDESC_ERROR_SUMMARY 0x00008000
134 #define RXDESC_FRAME_LEN_OFFSET 16
135 #define RXDESC_FRAME_LEN_MASK 0x3fff0000
136 #define RXDESC_DA_FILTER_FAIL 0x40000000
137
138 #define RXDESC1_END_RING 0x00008000
139
140 #define RXDESC_IP_PAYLOAD_MASK 0x00000003
141 #define RXDESC_IP_PAYLOAD_UDP 0x00000001
142 #define RXDESC_IP_PAYLOAD_TCP 0x00000002
143 #define RXDESC_IP_PAYLOAD_ICMP 0x00000003
144 #define RXDESC_IP_HEADER_ERR 0x00000008
145 #define RXDESC_IP_PAYLOAD_ERR 0x00000010
146 #define RXDESC_IPV4_PACKET 0x00000040
147 #define RXDESC_IPV6_PACKET 0x00000080
148 #define TXDESC_UNDERFLOW_ERR 0x00000001
149 #define TXDESC_JABBER_TIMEOUT 0x00000002
150 #define TXDESC_LOCAL_FAULT 0x00000004
151 #define TXDESC_REMOTE_FAULT 0x00000008
152 #define TXDESC_VLAN_FRAME 0x00000010
153 #define TXDESC_FRAME_FLUSHED 0x00000020
154 #define TXDESC_IP_HEADER_ERR 0x00000040
155 #define TXDESC_PAYLOAD_CSUM_ERR 0x00000080
156 #define TXDESC_ERROR_SUMMARY 0x00008000
157 #define TXDESC_SA_CTRL_INSERT 0x00040000
158 #define TXDESC_SA_CTRL_REPLACE 0x00080000
159 #define TXDESC_2ND_ADDR_CHAINED 0x00100000
160 #define TXDESC_END_RING 0x00200000
161 #define TXDESC_CSUM_IP 0x00400000
162 #define TXDESC_CSUM_IP_PAYLD 0x00800000
163 #define TXDESC_CSUM_ALL 0x00C00000
164 #define TXDESC_CRC_EN_REPLACE 0x01000000
165 #define TXDESC_CRC_EN_APPEND 0x02000000
166 #define TXDESC_DISABLE_PAD 0x04000000
167 #define TXDESC_FIRST_SEG 0x10000000
168 #define TXDESC_LAST_SEG 0x20000000
169 #define TXDESC_INTERRUPT 0x40000000
170
171 #define DESC_OWN 0x80000000
172 #define DESC_BUFFER1_SZ_MASK 0x00001fff
173 #define DESC_BUFFER2_SZ_MASK 0x1fff0000
174 #define DESC_BUFFER2_SZ_OFFSET 16
175
176 struct xgmac_regs {
177 u32 config;
178 u32 framefilter;
179 u32 resv_1[4];
180 u32 flow_control;
181 u32 vlantag;
182 u32 version;
183 u32 vlaninclude;
184 u32 resv_2[2];
185 u32 pacestretch;
186 u32 vlanhash;
187 u32 resv_3;
188 u32 intreg;
189 struct {
190 u32 hi; /* 0x40 */
191 u32 lo; /* 0x44 */
192 } macaddr[16];
193 u32 resv_4[0xd0];
194 u32 core_opmode; /* 0x400 */
195 u32 resv_5[0x2bf];
196 u32 busmode; /* 0xf00 */
197 u32 txpoll;
198 u32 rxpoll;
199 u32 rxdesclist;
200 u32 txdesclist;
201 u32 dma_status;
202 u32 dma_opmode;
203 u32 intenable;
204 u32 resv_6[2];
205 u32 axi_mode; /* 0xf28 */
206 };
207
208 struct xgmac_dma_desc {
209 __le32 flags;
210 __le32 buf_size;
211 __le32 buf1_addr; /* Buffer 1 Address Pointer */
212 __le32 buf2_addr; /* Buffer 2 Address Pointer */
213 __le32 ext_status;
214 __le32 res[3];
215 };
216
xgmac_get_regs(struct eth_pdata * pdata)217 static struct xgmac_regs *xgmac_get_regs(struct eth_pdata *pdata)
218 {
219 /*
220 * We use PHYS_64BIT on Highbank, so phys_addr_t is bigger than
221 * a pointer. U-Boot doesn't use LPAE (not even the MMU on highbank),
222 * so we can't access anything above 4GB.
223 * We have a check in the probe function below the ensure this,
224 * so casting to a 32-bit pointer type is fine here.
225 */
226 return (struct xgmac_regs *)(uintptr_t)pdata->iobase;
227 }
228
229 /* XGMAC Descriptor Access Helpers */
desc_set_buf_len(struct xgmac_dma_desc * p,u32 buf_sz)230 static inline void desc_set_buf_len(struct xgmac_dma_desc *p, u32 buf_sz)
231 {
232 if (buf_sz > MAX_DESC_BUF_SZ)
233 p->buf_size = cpu_to_le32(MAX_DESC_BUF_SZ |
234 (buf_sz - MAX_DESC_BUF_SZ) << DESC_BUFFER2_SZ_OFFSET);
235 else
236 p->buf_size = cpu_to_le32(buf_sz);
237 }
238
desc_get_buf_len(struct xgmac_dma_desc * p)239 static inline int desc_get_buf_len(struct xgmac_dma_desc *p)
240 {
241 u32 len = le32_to_cpu(p->buf_size);
242 return (len & DESC_BUFFER1_SZ_MASK) +
243 ((len & DESC_BUFFER2_SZ_MASK) >> DESC_BUFFER2_SZ_OFFSET);
244 }
245
desc_init_rx_desc(struct xgmac_dma_desc * p,int ring_size,int buf_sz)246 static inline void desc_init_rx_desc(struct xgmac_dma_desc *p, int ring_size,
247 int buf_sz)
248 {
249 struct xgmac_dma_desc *end = p + ring_size - 1;
250
251 memset(p, 0, sizeof(*p) * ring_size);
252
253 for (; p <= end; p++)
254 desc_set_buf_len(p, buf_sz);
255
256 end->buf_size |= cpu_to_le32(RXDESC1_END_RING);
257 }
258
desc_init_tx_desc(struct xgmac_dma_desc * p,u32 ring_size)259 static inline void desc_init_tx_desc(struct xgmac_dma_desc *p, u32 ring_size)
260 {
261 memset(p, 0, sizeof(*p) * ring_size);
262 p[ring_size - 1].flags = cpu_to_le32(TXDESC_END_RING);
263 }
264
desc_get_owner(struct xgmac_dma_desc * p)265 static inline int desc_get_owner(struct xgmac_dma_desc *p)
266 {
267 return le32_to_cpu(p->flags) & DESC_OWN;
268 }
269
desc_set_rx_owner(struct xgmac_dma_desc * p)270 static inline void desc_set_rx_owner(struct xgmac_dma_desc *p)
271 {
272 /* Clear all fields and set the owner */
273 p->flags = cpu_to_le32(DESC_OWN);
274 }
275
desc_set_tx_owner(struct xgmac_dma_desc * p,u32 flags)276 static inline void desc_set_tx_owner(struct xgmac_dma_desc *p, u32 flags)
277 {
278 u32 tmpflags = le32_to_cpu(p->flags);
279 tmpflags &= TXDESC_END_RING;
280 tmpflags |= flags | DESC_OWN;
281 p->flags = cpu_to_le32(tmpflags);
282 }
283
desc_get_buf_addr(struct xgmac_dma_desc * p)284 static inline void *desc_get_buf_addr(struct xgmac_dma_desc *p)
285 {
286 return (void *)le32_to_cpu(p->buf1_addr);
287 }
288
desc_set_buf_addr(struct xgmac_dma_desc * p,void * paddr,int len)289 static inline void desc_set_buf_addr(struct xgmac_dma_desc *p,
290 void *paddr, int len)
291 {
292 p->buf1_addr = cpu_to_le32(paddr);
293 if (len > MAX_DESC_BUF_SZ)
294 p->buf2_addr = cpu_to_le32(paddr + MAX_DESC_BUF_SZ);
295 }
296
desc_set_buf_addr_and_size(struct xgmac_dma_desc * p,void * paddr,int len)297 static inline void desc_set_buf_addr_and_size(struct xgmac_dma_desc *p,
298 void *paddr, int len)
299 {
300 desc_set_buf_len(p, len);
301 desc_set_buf_addr(p, paddr, len);
302 }
303
desc_get_rx_frame_len(struct xgmac_dma_desc * p)304 static inline int desc_get_rx_frame_len(struct xgmac_dma_desc *p)
305 {
306 u32 data = le32_to_cpu(p->flags);
307 u32 len = (data & RXDESC_FRAME_LEN_MASK) >> RXDESC_FRAME_LEN_OFFSET;
308 if (data & RXDESC_FRAME_TYPE)
309 len -= 4;
310
311 return len;
312 }
313
314 struct calxeda_eth_dev {
315 struct xgmac_dma_desc rx_chain[RX_NUM_DESC];
316 struct xgmac_dma_desc tx_chain[TX_NUM_DESC];
317 char rxbuffer[RX_BUF_SZ];
318
319 u32 tx_currdesc;
320 u32 rx_currdesc;
321 } __aligned(32);
322
323 /*
324 * Initialize a descriptor ring. Calxeda XGMAC is configured to use
325 * advanced descriptors.
326 */
327
init_rx_desc(struct eth_pdata * pdata,struct calxeda_eth_dev * priv)328 static void init_rx_desc(struct eth_pdata *pdata, struct calxeda_eth_dev *priv)
329 {
330 struct xgmac_dma_desc *rxdesc = priv->rx_chain;
331 struct xgmac_regs *regs = xgmac_get_regs(pdata);
332 void *rxbuffer = priv->rxbuffer;
333 int i;
334
335 desc_init_rx_desc(rxdesc, RX_NUM_DESC, ETH_BUF_SZ);
336 writel((ulong)rxdesc, ®s->rxdesclist);
337
338 for (i = 0; i < RX_NUM_DESC; i++) {
339 desc_set_buf_addr(rxdesc + i, rxbuffer + (i * ETH_BUF_SZ),
340 ETH_BUF_SZ);
341 desc_set_rx_owner(rxdesc + i);
342 }
343 }
344
init_tx_desc(struct eth_pdata * pdata,struct calxeda_eth_dev * priv)345 static void init_tx_desc(struct eth_pdata *pdata, struct calxeda_eth_dev *priv)
346 {
347 struct xgmac_regs *regs = xgmac_get_regs(pdata);
348
349 desc_init_tx_desc(priv->tx_chain, TX_NUM_DESC);
350 writel((ulong)priv->tx_chain, ®s->txdesclist);
351 }
352
xgmac_reset(struct xgmac_regs * regs)353 static int xgmac_reset(struct xgmac_regs *regs)
354 {
355 int timeout = MAC_TIMEOUT;
356 u32 value;
357
358 value = readl(®s->config) & XGMAC_CONTROL_SPD_MASK;
359
360 writel(XGMAC_DMA_BUSMODE_RESET, ®s->busmode);
361 while ((timeout-- >= 0) &&
362 (readl(®s->busmode) & XGMAC_DMA_BUSMODE_RESET))
363 udelay(1);
364
365 writel(value, ®s->config);
366
367 return timeout;
368 }
369
xgmac_hwmacaddr(struct eth_pdata * pdata)370 static void xgmac_hwmacaddr(struct eth_pdata *pdata)
371 {
372 struct xgmac_regs *regs = xgmac_get_regs(pdata);
373 u32 macaddr[2];
374
375 memcpy(macaddr, pdata->enetaddr, ARP_HLEN);
376 writel(macaddr[1], ®s->macaddr[0].hi);
377 writel(macaddr[0], ®s->macaddr[0].lo);
378 }
379
xgmac_eth_start(struct udevice * dev)380 static int xgmac_eth_start(struct udevice *dev)
381 {
382 struct eth_pdata *pdata = dev_get_plat(dev);
383 struct xgmac_regs *regs = xgmac_get_regs(pdata);
384 struct calxeda_eth_dev *priv = dev_get_priv(dev);
385 u32 value;
386
387 if (xgmac_reset(regs) < 0)
388 return -ETIMEDOUT;
389
390 /* set the hardware MAC address */
391 xgmac_hwmacaddr(pdata);
392
393 /* set the AXI bus modes */
394 value = XGMAC_DMA_BUSMODE_ATDS |
395 (16 << XGMAC_DMA_BUSMODE_PBL_SHIFT) |
396 XGMAC_DMA_BUSMODE_FB | XGMAC_DMA_BUSMODE_AAL;
397 writel(value, ®s->busmode);
398
399 value = XGMAC_DMA_AXIMODE_AAL | XGMAC_DMA_AXIMODE_BLEN16 |
400 XGMAC_DMA_AXIMODE_BLEN8 | XGMAC_DMA_AXIMODE_BLEN4;
401 writel(value, ®s->axi_mode);
402
403 /* set flow control parameters and store and forward mode */
404 value = (FIFO_MINUS_12K << XGMAC_CORE_OMR_RFD_SHIFT) |
405 (FIFO_MINUS_4K << XGMAC_CORE_OMR_RFA_SHIFT) |
406 XGMAC_CORE_OMR_EFC | XGMAC_CORE_OMR_TSF;
407 writel(value, ®s->core_opmode);
408
409 /* enable pause frames */
410 value = (1024 << XGMAC_CORE_FLOW_PT_SHIFT) |
411 (1 << XGMAC_CORE_FLOW_PLT_SHIFT) |
412 XGMAC_CORE_FLOW_UP | XGMAC_CORE_FLOW_RFE | XGMAC_CORE_FLOW_TFE;
413 writel(value, ®s->flow_control);
414
415 /* Initialize the descriptor chains */
416 init_rx_desc(pdata, priv);
417 init_tx_desc(pdata, priv);
418
419 /* must set to 0, or when started up will cause issues */
420 priv->tx_currdesc = 0;
421 priv->rx_currdesc = 0;
422
423 /* set default core values */
424 value = readl(®s->config);
425 value &= XGMAC_CONTROL_SPD_MASK;
426 value |= XGMAC_CONTROL_DDIC | XGMAC_CONTROL_ACS |
427 XGMAC_CONTROL_IPC | XGMAC_CONTROL_CAR;
428
429 /* Everything is ready enable both mac and DMA */
430 value |= RXENABLE | TXENABLE;
431 writel(value, ®s->config);
432
433 value = readl(®s->dma_opmode);
434 value |= RXSTART | TXSTART;
435 writel(value, ®s->dma_opmode);
436
437 return 0;
438 }
439
xgmac_tx(struct udevice * dev,void * packet,int length)440 static int xgmac_tx(struct udevice *dev, void *packet, int length)
441 {
442 struct calxeda_eth_dev *priv = dev_get_priv(dev);
443 struct eth_pdata *pdata = dev_get_plat(dev);
444 struct xgmac_regs *regs = xgmac_get_regs(pdata);
445 u32 currdesc = priv->tx_currdesc;
446 struct xgmac_dma_desc *txdesc = &priv->tx_chain[currdesc];
447 int timeout;
448
449 desc_set_buf_addr_and_size(txdesc, packet, length);
450 desc_set_tx_owner(txdesc, TXDESC_FIRST_SEG |
451 TXDESC_LAST_SEG | TXDESC_CRC_EN_APPEND);
452
453 /* write poll demand */
454 writel(1, ®s->txpoll);
455
456 timeout = 1000000;
457 while (desc_get_owner(txdesc)) {
458 if (timeout-- < 0) {
459 printf("xgmac: TX timeout\n");
460 return -ETIMEDOUT;
461 }
462 udelay(1);
463 }
464
465 priv->tx_currdesc = (currdesc + 1) & (TX_NUM_DESC - 1);
466 return 0;
467 }
468
xgmac_rx(struct udevice * dev,int flags,uchar ** packetp)469 static int xgmac_rx(struct udevice *dev, int flags, uchar **packetp)
470 {
471 struct calxeda_eth_dev *priv = dev_get_priv(dev);
472 u32 currdesc = priv->rx_currdesc;
473 struct xgmac_dma_desc *rxdesc = &priv->rx_chain[currdesc];
474 int length = 0;
475
476 /* check if the host has the desc */
477 if (desc_get_owner(rxdesc))
478 return -EAGAIN; /* the MAC is still chewing on it */
479
480 length = desc_get_rx_frame_len(rxdesc);
481 *packetp = desc_get_buf_addr(rxdesc);
482
483 priv->rx_currdesc = (currdesc + 1) & (RX_NUM_DESC - 1);
484
485 return length;
486 }
487
xgmac_free_pkt(struct udevice * dev,uchar * packet,int length)488 static int xgmac_free_pkt(struct udevice *dev, uchar *packet, int length)
489 {
490 struct eth_pdata *pdata = dev_get_plat(dev);
491 struct xgmac_regs *regs = xgmac_get_regs(pdata);
492 struct calxeda_eth_dev *priv = dev_get_priv(dev);
493 u32 rxdesc = ((char *)packet - priv->rxbuffer) / ETH_BUF_SZ;
494 struct xgmac_dma_desc *p = &priv->rx_chain[rxdesc];
495
496 /* set descriptor back to owned by XGMAC */
497 desc_set_rx_owner(p);
498 writel(1, ®s->rxpoll);
499
500 return 0;
501 }
502
xgmac_eth_stop(struct udevice * dev)503 static void xgmac_eth_stop(struct udevice *dev)
504 {
505 struct calxeda_eth_dev *priv = dev_get_priv(dev);
506 struct eth_pdata *pdata = dev_get_plat(dev);
507 struct xgmac_regs *regs = xgmac_get_regs(pdata);
508 int value;
509
510 /* Disable TX/RX */
511 value = readl(®s->config);
512 value &= ~(RXENABLE | TXENABLE);
513 writel(value, ®s->config);
514
515 /* Disable DMA */
516 value = readl(®s->dma_opmode);
517 value &= ~(RXSTART | TXSTART);
518 writel(value, ®s->dma_opmode);
519
520 /* must set to 0, or when started up will cause issues */
521 priv->tx_currdesc = 0;
522 priv->rx_currdesc = 0;
523 }
524
525 /*
526 * Changing the MAC address is not a good idea, as the fabric would
527 * need to know about this as well (it does not learn MAC addresses).
528 */
xgmac_eth_write_hwaddr(struct udevice * dev)529 static int xgmac_eth_write_hwaddr(struct udevice *dev)
530 {
531 return -ENOSYS;
532 }
533
xgmac_eth_read_rom_hwaddr(struct udevice * dev)534 static int xgmac_eth_read_rom_hwaddr(struct udevice *dev)
535 {
536 struct eth_pdata *pdata = dev_get_plat(dev);
537 struct xgmac_regs *regs = xgmac_get_regs(pdata);
538 u32 macaddr[2];
539
540 /* The MAC address is already configured, so read it from registers. */
541 macaddr[1] = readl(®s->macaddr[0].hi);
542 macaddr[0] = readl(®s->macaddr[0].lo);
543 memcpy(pdata->enetaddr, macaddr, ARP_HLEN);
544
545 return 0;
546 }
547
xgmac_ofdata_to_platdata(struct udevice * dev)548 static int xgmac_ofdata_to_platdata(struct udevice *dev)
549 {
550 struct eth_pdata *pdata = dev_get_plat(dev);
551 struct calxeda_eth_dev *priv;
552
553 /* Structure must be aligned, because it contains the descriptors */
554 priv = memalign(32, sizeof(*priv));
555 if (!priv)
556 return -ENOMEM;
557 dev_set_priv(dev, priv);
558
559 pdata->iobase = devfdt_get_addr(dev);
560 if (pdata->iobase == FDT_ADDR_T_NONE) {
561 printf("%s: Cannot find XGMAC base address\n", __func__);
562 return -EINVAL;
563 }
564 if (pdata->iobase >= (1ULL << 32)) {
565 printf("%s: MMIO base address cannot be above 4GB\n", __func__);
566 return -EINVAL;
567 }
568
569 return 0;
570 }
571
xgmac_eth_probe(struct udevice * dev)572 static int xgmac_eth_probe(struct udevice *dev)
573 {
574 struct eth_pdata *pdata = dev_get_plat(dev);
575 struct xgmac_regs *regs = xgmac_get_regs(pdata);
576
577 /* check hardware version */
578 if (readl(®s->version) != 0x1012)
579 return -ENODEV;
580
581 xgmac_eth_read_rom_hwaddr(dev);
582
583 return 0;
584 }
585
586 static const struct eth_ops xgmac_eth_ops = {
587 .start = xgmac_eth_start,
588 .send = xgmac_tx,
589 .recv = xgmac_rx,
590 .free_pkt = xgmac_free_pkt,
591 .stop = xgmac_eth_stop,
592 .write_hwaddr = xgmac_eth_write_hwaddr,
593 .read_rom_hwaddr = xgmac_eth_read_rom_hwaddr,
594 };
595
596 static const struct udevice_id xgmac_eth_ids[] = {
597 { .compatible = "calxeda,hb-xgmac" },
598 { }
599 };
600
601 U_BOOT_DRIVER(eth_xgmac) = {
602 .name = "eth_xgmac",
603 .id = UCLASS_ETH,
604 .of_match = xgmac_eth_ids,
605 .of_to_plat = xgmac_ofdata_to_platdata,
606 .probe = xgmac_eth_probe,
607 .ops = &xgmac_eth_ops,
608 .plat_auto = sizeof(struct eth_pdata),
609 };
610