1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J7200 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 msmc_ram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x00 0x70000000 0x00 0x100000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x00 0x00 0x70000000 0x100000>; 15 16 atf-sram@0 { 17 reg = <0x00 0x20000>; 18 }; 19 }; 20 21 scm_conf: scm-conf@100000 { 22 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 23 reg = <0x00 0x00100000 0x00 0x1c000>; 24 #address-cells = <1>; 25 #size-cells = <1>; 26 ranges = <0x00 0x00 0x00100000 0x1c000>; 27 28 serdes_ln_ctrl: serdes-ln-ctrl@4080 { 29 compatible = "mmio-mux"; 30 #mux-control-cells = <1>; 31 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 32 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ 33 }; 34 35 usb_serdes_mux: mux-controller@4000 { 36 compatible = "mmio-mux"; 37 #mux-control-cells = <1>; 38 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ 39 }; 40 }; 41 42 gic500: interrupt-controller@1800000 { 43 compatible = "arm,gic-v3"; 44 #address-cells = <2>; 45 #size-cells = <2>; 46 ranges; 47 #interrupt-cells = <3>; 48 interrupt-controller; 49 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 50 <0x00 0x01900000 0x00 0x100000>; /* GICR */ 51 52 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 53 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 54 55 gic_its: msi-controller@1820000 { 56 compatible = "arm,gic-v3-its"; 57 reg = <0x00 0x01820000 0x00 0x10000>; 58 socionext,synquacer-pre-its = <0x1000000 0x400000>; 59 msi-controller; 60 #msi-cells = <1>; 61 }; 62 }; 63 64 main_gpio_intr: interrupt-controller0 { 65 compatible = "ti,sci-intr"; 66 ti,intr-trigger-type = <1>; 67 interrupt-controller; 68 interrupt-parent = <&gic500>; 69 #interrupt-cells = <1>; 70 ti,sci = <&dmsc>; 71 ti,sci-dev-id = <131>; 72 ti,interrupt-ranges = <8 392 56>; 73 }; 74 75 main_navss: bus@30000000 { 76 compatible = "simple-mfd"; 77 #address-cells = <2>; 78 #size-cells = <2>; 79 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 80 ti,sci-dev-id = <199>; 81 82 main_navss_intr: interrupt-controller1 { 83 compatible = "ti,sci-intr"; 84 ti,intr-trigger-type = <4>; 85 interrupt-controller; 86 interrupt-parent = <&gic500>; 87 #interrupt-cells = <1>; 88 ti,sci = <&dmsc>; 89 ti,sci-dev-id = <213>; 90 ti,interrupt-ranges = <0 64 64>, 91 <64 448 64>, 92 <128 672 64>; 93 }; 94 95 main_udmass_inta: msi-controller@33d00000 { 96 compatible = "ti,sci-inta"; 97 reg = <0x00 0x33d00000 0x00 0x100000>; 98 interrupt-controller; 99 #interrupt-cells = <0>; 100 interrupt-parent = <&main_navss_intr>; 101 msi-controller; 102 ti,sci = <&dmsc>; 103 ti,sci-dev-id = <209>; 104 ti,interrupt-ranges = <0 0 256>; 105 }; 106 107 secure_proxy_main: mailbox@32c00000 { 108 compatible = "ti,am654-secure-proxy"; 109 #mbox-cells = <1>; 110 reg-names = "target_data", "rt", "scfg"; 111 reg = <0x00 0x32c00000 0x00 0x100000>, 112 <0x00 0x32400000 0x00 0x100000>, 113 <0x00 0x32800000 0x00 0x100000>; 114 interrupt-names = "rx_011"; 115 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 116 }; 117 118 hwspinlock: spinlock@30e00000 { 119 compatible = "ti,am654-hwspinlock"; 120 reg = <0x00 0x30e00000 0x00 0x1000>; 121 #hwlock-cells = <1>; 122 }; 123 124 mailbox0_cluster0: mailbox@31f80000 { 125 compatible = "ti,am654-mailbox"; 126 reg = <0x00 0x31f80000 0x00 0x200>; 127 #mbox-cells = <1>; 128 ti,mbox-num-users = <4>; 129 ti,mbox-num-fifos = <16>; 130 interrupt-parent = <&main_navss_intr>; 131 }; 132 133 mailbox0_cluster1: mailbox@31f81000 { 134 compatible = "ti,am654-mailbox"; 135 reg = <0x00 0x31f81000 0x00 0x200>; 136 #mbox-cells = <1>; 137 ti,mbox-num-users = <4>; 138 ti,mbox-num-fifos = <16>; 139 interrupt-parent = <&main_navss_intr>; 140 }; 141 142 mailbox0_cluster2: mailbox@31f82000 { 143 compatible = "ti,am654-mailbox"; 144 reg = <0x00 0x31f82000 0x00 0x200>; 145 #mbox-cells = <1>; 146 ti,mbox-num-users = <4>; 147 ti,mbox-num-fifos = <16>; 148 interrupt-parent = <&main_navss_intr>; 149 }; 150 151 mailbox0_cluster3: mailbox@31f83000 { 152 compatible = "ti,am654-mailbox"; 153 reg = <0x00 0x31f83000 0x00 0x200>; 154 #mbox-cells = <1>; 155 ti,mbox-num-users = <4>; 156 ti,mbox-num-fifos = <16>; 157 interrupt-parent = <&main_navss_intr>; 158 }; 159 160 mailbox0_cluster4: mailbox@31f84000 { 161 compatible = "ti,am654-mailbox"; 162 reg = <0x00 0x31f84000 0x00 0x200>; 163 #mbox-cells = <1>; 164 ti,mbox-num-users = <4>; 165 ti,mbox-num-fifos = <16>; 166 interrupt-parent = <&main_navss_intr>; 167 }; 168 169 mailbox0_cluster5: mailbox@31f85000 { 170 compatible = "ti,am654-mailbox"; 171 reg = <0x00 0x31f85000 0x00 0x200>; 172 #mbox-cells = <1>; 173 ti,mbox-num-users = <4>; 174 ti,mbox-num-fifos = <16>; 175 interrupt-parent = <&main_navss_intr>; 176 }; 177 178 mailbox0_cluster6: mailbox@31f86000 { 179 compatible = "ti,am654-mailbox"; 180 reg = <0x00 0x31f86000 0x00 0x200>; 181 #mbox-cells = <1>; 182 ti,mbox-num-users = <4>; 183 ti,mbox-num-fifos = <16>; 184 interrupt-parent = <&main_navss_intr>; 185 }; 186 187 mailbox0_cluster7: mailbox@31f87000 { 188 compatible = "ti,am654-mailbox"; 189 reg = <0x00 0x31f87000 0x00 0x200>; 190 #mbox-cells = <1>; 191 ti,mbox-num-users = <4>; 192 ti,mbox-num-fifos = <16>; 193 interrupt-parent = <&main_navss_intr>; 194 }; 195 196 mailbox0_cluster8: mailbox@31f88000 { 197 compatible = "ti,am654-mailbox"; 198 reg = <0x00 0x31f88000 0x00 0x200>; 199 #mbox-cells = <1>; 200 ti,mbox-num-users = <4>; 201 ti,mbox-num-fifos = <16>; 202 interrupt-parent = <&main_navss_intr>; 203 }; 204 205 mailbox0_cluster9: mailbox@31f89000 { 206 compatible = "ti,am654-mailbox"; 207 reg = <0x00 0x31f89000 0x00 0x200>; 208 #mbox-cells = <1>; 209 ti,mbox-num-users = <4>; 210 ti,mbox-num-fifos = <16>; 211 interrupt-parent = <&main_navss_intr>; 212 }; 213 214 mailbox0_cluster10: mailbox@31f8a000 { 215 compatible = "ti,am654-mailbox"; 216 reg = <0x00 0x31f8a000 0x00 0x200>; 217 #mbox-cells = <1>; 218 ti,mbox-num-users = <4>; 219 ti,mbox-num-fifos = <16>; 220 interrupt-parent = <&main_navss_intr>; 221 }; 222 223 mailbox0_cluster11: mailbox@31f8b000 { 224 compatible = "ti,am654-mailbox"; 225 reg = <0x00 0x31f8b000 0x00 0x200>; 226 #mbox-cells = <1>; 227 ti,mbox-num-users = <4>; 228 ti,mbox-num-fifos = <16>; 229 interrupt-parent = <&main_navss_intr>; 230 }; 231 232 main_ringacc: ringacc@3c000000 { 233 compatible = "ti,am654-navss-ringacc"; 234 reg = <0x00 0x3c000000 0x00 0x400000>, 235 <0x00 0x38000000 0x00 0x400000>, 236 <0x00 0x31120000 0x00 0x100>, 237 <0x00 0x33000000 0x00 0x40000>; 238 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 239 ti,num-rings = <1024>; 240 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 241 ti,sci = <&dmsc>; 242 ti,sci-dev-id = <211>; 243 msi-parent = <&main_udmass_inta>; 244 }; 245 246 main_udmap: dma-controller@31150000 { 247 compatible = "ti,j721e-navss-main-udmap"; 248 reg = <0x00 0x31150000 0x00 0x100>, 249 <0x00 0x34000000 0x00 0x100000>, 250 <0x00 0x35000000 0x00 0x100000>; 251 reg-names = "gcfg", "rchanrt", "tchanrt"; 252 msi-parent = <&main_udmass_inta>; 253 #dma-cells = <1>; 254 255 ti,sci = <&dmsc>; 256 ti,sci-dev-id = <212>; 257 ti,ringacc = <&main_ringacc>; 258 259 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 260 <0x0f>, /* TX_HCHAN */ 261 <0x10>; /* TX_UHCHAN */ 262 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 263 <0x0b>, /* RX_HCHAN */ 264 <0x0c>; /* RX_UHCHAN */ 265 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 266 }; 267 268 cpts@310d0000 { 269 compatible = "ti,j721e-cpts"; 270 reg = <0x00 0x310d0000 0x00 0x400>; 271 reg-names = "cpts"; 272 clocks = <&k3_clks 201 1>; 273 clock-names = "cpts"; 274 interrupts-extended = <&main_navss_intr 391>; 275 interrupt-names = "cpts"; 276 ti,cpts-periodic-outputs = <6>; 277 ti,cpts-ext-ts-inputs = <8>; 278 }; 279 }; 280 281 main_pmx0: pinctrl@11c000 { 282 compatible = "pinctrl-single"; 283 /* Proxy 0 addressing */ 284 reg = <0x00 0x11c000 0x00 0x2b4>; 285 #pinctrl-cells = <1>; 286 pinctrl-single,register-width = <32>; 287 pinctrl-single,function-mask = <0xffffffff>; 288 }; 289 290 main_uart0: serial@2800000 { 291 compatible = "ti,j721e-uart", "ti,am654-uart"; 292 reg = <0x00 0x02800000 0x00 0x100>; 293 reg-shift = <2>; 294 reg-io-width = <4>; 295 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 296 clock-frequency = <48000000>; 297 current-speed = <115200>; 298 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 299 clocks = <&k3_clks 146 2>; 300 clock-names = "fclk"; 301 }; 302 303 main_uart1: serial@2810000 { 304 compatible = "ti,j721e-uart", "ti,am654-uart"; 305 reg = <0x00 0x02810000 0x00 0x100>; 306 reg-shift = <2>; 307 reg-io-width = <4>; 308 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 309 clock-frequency = <48000000>; 310 current-speed = <115200>; 311 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 312 clocks = <&k3_clks 278 2>; 313 clock-names = "fclk"; 314 }; 315 316 main_uart2: serial@2820000 { 317 compatible = "ti,j721e-uart", "ti,am654-uart"; 318 reg = <0x00 0x02820000 0x00 0x100>; 319 reg-shift = <2>; 320 reg-io-width = <4>; 321 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 322 clock-frequency = <48000000>; 323 current-speed = <115200>; 324 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 325 clocks = <&k3_clks 279 2>; 326 clock-names = "fclk"; 327 }; 328 329 main_uart3: serial@2830000 { 330 compatible = "ti,j721e-uart", "ti,am654-uart"; 331 reg = <0x00 0x02830000 0x00 0x100>; 332 reg-shift = <2>; 333 reg-io-width = <4>; 334 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 335 clock-frequency = <48000000>; 336 current-speed = <115200>; 337 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 338 clocks = <&k3_clks 280 2>; 339 clock-names = "fclk"; 340 }; 341 342 main_uart4: serial@2840000 { 343 compatible = "ti,j721e-uart", "ti,am654-uart"; 344 reg = <0x00 0x02840000 0x00 0x100>; 345 reg-shift = <2>; 346 reg-io-width = <4>; 347 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 348 clock-frequency = <48000000>; 349 current-speed = <115200>; 350 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 351 clocks = <&k3_clks 281 2>; 352 clock-names = "fclk"; 353 }; 354 355 main_uart5: serial@2850000 { 356 compatible = "ti,j721e-uart", "ti,am654-uart"; 357 reg = <0x00 0x02850000 0x00 0x100>; 358 reg-shift = <2>; 359 reg-io-width = <4>; 360 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 361 clock-frequency = <48000000>; 362 current-speed = <115200>; 363 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 364 clocks = <&k3_clks 282 2>; 365 clock-names = "fclk"; 366 }; 367 368 main_uart6: serial@2860000 { 369 compatible = "ti,j721e-uart", "ti,am654-uart"; 370 reg = <0x00 0x02860000 0x00 0x100>; 371 reg-shift = <2>; 372 reg-io-width = <4>; 373 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 374 clock-frequency = <48000000>; 375 current-speed = <115200>; 376 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 377 clocks = <&k3_clks 283 2>; 378 clock-names = "fclk"; 379 }; 380 381 main_uart7: serial@2870000 { 382 compatible = "ti,j721e-uart", "ti,am654-uart"; 383 reg = <0x00 0x02870000 0x00 0x100>; 384 reg-shift = <2>; 385 reg-io-width = <4>; 386 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 387 clock-frequency = <48000000>; 388 current-speed = <115200>; 389 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 390 clocks = <&k3_clks 284 2>; 391 clock-names = "fclk"; 392 }; 393 394 main_uart8: serial@2880000 { 395 compatible = "ti,j721e-uart", "ti,am654-uart"; 396 reg = <0x00 0x02880000 0x00 0x100>; 397 reg-shift = <2>; 398 reg-io-width = <4>; 399 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 400 clock-frequency = <48000000>; 401 current-speed = <115200>; 402 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 403 clocks = <&k3_clks 285 2>; 404 clock-names = "fclk"; 405 }; 406 407 main_uart9: serial@2890000 { 408 compatible = "ti,j721e-uart", "ti,am654-uart"; 409 reg = <0x00 0x02890000 0x00 0x100>; 410 reg-shift = <2>; 411 reg-io-width = <4>; 412 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 413 clock-frequency = <48000000>; 414 current-speed = <115200>; 415 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 416 clocks = <&k3_clks 286 2>; 417 clock-names = "fclk"; 418 }; 419 420 main_sdhci0: sdhci@4f80000 { 421 compatible = "ti,j721e-sdhci-8bit"; 422 reg = <0x0 0x04f80000 0x0 0x260>, <0x0 0x4f88000 0x0 0x134>; 423 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 424 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 425 clock-names = "clk_xin", "clk_ahb"; 426 clocks = <&k3_clks 91 3>, <&k3_clks 91 0>; 427 ti,otap-del-sel-legacy = <0x0>; 428 ti,otap-del-sel-mmc-hs = <0x0>; 429 ti,otap-del-sel-ddr52 = <0x6>; 430 ti,otap-del-sel-hs200 = <0x8>; 431 ti,otap-del-sel-hs400 = <0x0>; 432 ti,strobe-sel = <0x77>; 433 ti,trm-icp = <0x8>; 434 bus-width = <8>; 435 mmc-hs200-1_8v; 436 mmc-ddr-1_8v; 437 dma-coherent; 438 }; 439 440 main_sdhci1: sdhci@4fb0000 { 441 compatible = "ti,j721e-sdhci-4bit"; 442 reg = <0x0 0x04fb0000 0x0 0x260>, <0x0 0x4fb8000 0x0 0x134>; 443 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 444 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 445 clock-names = "clk_xin", "clk_ahb"; 446 clocks = <&k3_clks 92 2>, <&k3_clks 92 1>; 447 ti,otap-del-sel-legacy = <0x0>; 448 ti,otap-del-sel-sd-hs = <0x0>; 449 ti,otap-del-sel-sdr12 = <0xf>; 450 ti,otap-del-sel-sdr25 = <0xf>; 451 ti,otap-del-sel-sdr50 = <0xc>; 452 ti,otap-del-sel-sdr104 = <0x5>; 453 ti,otap-del-sel-ddr50 = <0xc>; 454 ti,clkbuf-sel = <0x7>; 455 dma-coherent; 456 }; 457 458 main_i2c0: i2c@2000000 { 459 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 460 reg = <0x00 0x2000000 0x00 0x100>; 461 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 462 #address-cells = <1>; 463 #size-cells = <0>; 464 clock-names = "fck"; 465 clocks = <&k3_clks 187 1>; 466 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 467 }; 468 469 main_i2c1: i2c@2010000 { 470 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 471 reg = <0x00 0x2010000 0x00 0x100>; 472 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 clock-names = "fck"; 476 clocks = <&k3_clks 188 1>; 477 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 478 }; 479 480 main_i2c2: i2c@2020000 { 481 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 482 reg = <0x00 0x2020000 0x00 0x100>; 483 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 484 #address-cells = <1>; 485 #size-cells = <0>; 486 clock-names = "fck"; 487 clocks = <&k3_clks 189 1>; 488 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 489 }; 490 491 main_i2c3: i2c@2030000 { 492 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 493 reg = <0x00 0x2030000 0x00 0x100>; 494 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 495 #address-cells = <1>; 496 #size-cells = <0>; 497 clock-names = "fck"; 498 clocks = <&k3_clks 190 1>; 499 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 500 }; 501 502 main_i2c4: i2c@2040000 { 503 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 504 reg = <0x00 0x2040000 0x00 0x100>; 505 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 506 #address-cells = <1>; 507 #size-cells = <0>; 508 clock-names = "fck"; 509 clocks = <&k3_clks 191 1>; 510 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 511 }; 512 513 main_i2c5: i2c@2050000 { 514 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 515 reg = <0x00 0x2050000 0x00 0x100>; 516 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 clock-names = "fck"; 520 clocks = <&k3_clks 192 1>; 521 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 522 }; 523 524 main_i2c6: i2c@2060000 { 525 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 526 reg = <0x00 0x2060000 0x00 0x100>; 527 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 clock-names = "fck"; 531 clocks = <&k3_clks 193 1>; 532 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 533 }; 534 535 main_gpio0: gpio@600000 { 536 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 537 reg = <0x0 0x00600000 0x0 0x100>; 538 gpio-controller; 539 #gpio-cells = <2>; 540 interrupts = <105 0 IRQ_TYPE_EDGE_RISING>, 541 <105 1 IRQ_TYPE_EDGE_RISING>, 542 <105 2 IRQ_TYPE_EDGE_RISING>, 543 <105 3 IRQ_TYPE_EDGE_RISING>, 544 <105 4 IRQ_TYPE_EDGE_RISING>, 545 <105 5 IRQ_TYPE_EDGE_RISING>, 546 <105 6 IRQ_TYPE_EDGE_RISING>, 547 <105 7 IRQ_TYPE_EDGE_RISING>; 548 interrupt-controller; 549 #interrupt-cells = <2>; 550 ti,ngpio = <69>; 551 ti,davinci-gpio-unbanked = <0>; 552 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 553 clocks = <&k3_clks 105 0>; 554 clock-names = "gpio"; 555 }; 556 557 usbss0: cdns-usb@4104000 { 558 compatible = "ti,j721e-usb"; 559 reg = <0x00 0x4104000 0x00 0x100>; 560 dma-coherent; 561 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 562 clocks = <&k3_clks 288 12>, <&k3_clks 288 3>; 563 clock-names = "ref", "lpm"; 564 assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */ 565 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */ 566 #address-cells = <2>; 567 #size-cells = <2>; 568 ranges; 569 570 usb0: usb@6000000 { 571 compatible = "cdns,usb3"; 572 reg = <0x00 0x6000000 0x00 0x10000>, 573 <0x00 0x6010000 0x00 0x10000>, 574 <0x00 0x6020000 0x00 0x10000>; 575 reg-names = "otg", "xhci", "dev"; 576 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 577 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 578 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 579 interrupt-names = "host", 580 "peripheral", 581 "otg"; 582 maximum-speed = "super-speed"; 583 dr_mode = "otg"; 584 }; 585 }; 586 587 main_r5fss0: r5fss@5c00000 { 588 compatible = "ti,j7200-r5fss"; 589 ti,cluster-mode = <0>; 590 #address-cells = <1>; 591 #size-cells = <1>; 592 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 593 <0x5d00000 0x00 0x5d00000 0x20000>; 594 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; 595 596 main_r5fss0_core0: r5f@5c00000 { 597 compatible = "ti,j7200-r5f"; 598 reg = <0x5c00000 0x00010000>, 599 <0x5c10000 0x00010000>; 600 reg-names = "atcm", "btcm"; 601 ti,sci = <&dmsc>; 602 ti,sci-dev-id = <245>; 603 ti,sci-proc-ids = <0x06 0xFF>; 604 resets = <&k3_reset 245 1>; 605 firmware-name = "j7200-main-r5f0_0-fw"; 606 ti,atcm-enable = <1>; 607 ti,btcm-enable = <1>; 608 ti,loczrama = <1>; 609 }; 610 611 main_r5fss0_core1: r5f@5d00000 { 612 compatible = "ti,j7200-r5f"; 613 reg = <0x5d00000 0x00008000>, 614 <0x5d10000 0x00008000>; 615 reg-names = "atcm", "btcm"; 616 ti,sci = <&dmsc>; 617 ti,sci-dev-id = <246>; 618 ti,sci-proc-ids = <0x07 0xFF>; 619 resets = <&k3_reset 246 1>; 620 firmware-name = "j7200-main-r5f0_1-fw"; 621 ti,atcm-enable = <1>; 622 ti,btcm-enable = <1>; 623 ti,loczrama = <1>; 624 }; 625 }; 626}; 627