1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 */
9
10 #include <common.h>
11 #include <init.h>
12 #include <pci.h>
13 #include <asm/global_data.h>
14 #include <asm/immap.h>
15 #include <asm/io.h>
16 #include <linux/delay.h>
17
18 DECLARE_GLOBAL_DATA_PTR;
19
checkboard(void)20 int checkboard(void)
21 {
22 puts("Board: ");
23 puts("Freescale M54455 EVB\n");
24 return 0;
25 };
26
dram_init(void)27 int dram_init(void)
28 {
29 u32 dramsize;
30 #ifdef CONFIG_CF_SBF
31 /*
32 * Serial Boot: The dram is already initialized in start.S
33 * only require to return DRAM size
34 */
35 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
36 #else
37 sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
38 gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
39 u32 i;
40
41 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
42
43 for (i = 0x13; i < 0x20; i++) {
44 if (dramsize == (1 << i))
45 break;
46 }
47 i--;
48
49 out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
50
51 out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
52 out_be32(&sdram->sdcs1, CONFIG_SYS_SDRAM_BASE1 | i);
53
54 out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
55 out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
56
57 /* Issue PALL */
58 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
59
60 /* Issue LEMR */
61 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD | 0x408);
62 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x300);
63
64 udelay(500);
65
66 /* Issue PALL */
67 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
68
69 /* Perform two refresh cycles */
70 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
71 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
72
73 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x200);
74
75 out_be32(&sdram->sdcr,
76 (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
77
78 udelay(100);
79 #endif
80 gd->ram_size = dramsize << 1;
81
82 return 0;
83 };
84
testdram(void)85 int testdram(void)
86 {
87 /* TODO: XXX XXX XXX */
88 printf("DRAM test not implemented!\n");
89
90 return (0);
91 }
92
93 #if defined(CONFIG_IDE)
94 #include <ata.h>
95
ide_preinit(void)96 int ide_preinit(void)
97 {
98 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
99 u32 tmp;
100
101 tmp = (in_8(&gpio->par_fec) & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10;
102 setbits_8(&gpio->par_fec, tmp);
103 tmp = ((in_be16(&gpio->par_feci2c) & 0xf0ff) |
104 (GPIO_PAR_FECI2C_MDC1_ATA_DIOR | GPIO_PAR_FECI2C_MDIO1_ATA_DIOW));
105 setbits_be16(&gpio->par_feci2c, tmp);
106
107 setbits_be16(&gpio->par_ata,
108 GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
109 GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0 |
110 GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
111 GPIO_PAR_ATA_IORDY_IORDY);
112 setbits_be16(&gpio->par_pci,
113 GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
114
115 return (0);
116 }
117
ide_set_reset(int idereset)118 void ide_set_reset(int idereset)
119 {
120 atac_t *ata = (atac_t *) MMAP_ATA;
121 long period;
122 /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
123 int piotms[5][9] = {
124 {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
125 {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
126 {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
127 {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
128 {25, 70, 20, 10, 20, 5, 10, 0, 35}
129 }; /* PIO 4 */
130
131 if (idereset) {
132 /* control reset */
133 out_8(&ata->cr, 0);
134 udelay(10000);
135 } else {
136 #define CALC_TIMING(t) (t + period - 1) / period
137 period = 1000000000 / gd->bus_clk; /* period in ns */
138
139 /*ata->ton = CALC_TIMING (180); */
140 out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
141 out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
142 out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
143 out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
144 out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
145 out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
146 out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
147
148 /* IORDY enable */
149 out_8(&ata->cr, 0x40);
150 udelay(200000);
151 /* IORDY enable */
152 setbits_8(&ata->cr, 0x01);
153 }
154 }
155 #endif
156
157 #if defined(CONFIG_PCI)
158 /*
159 * Initialize PCI devices, report devices found.
160 */
161 static struct pci_controller hose;
162 extern void pci_mcf5445x_init(struct pci_controller *hose);
163
pci_init_board(void)164 void pci_init_board(void)
165 {
166 pci_mcf5445x_init(&hose);
167 }
168 #endif /* CONFIG_PCI */
169
170 #if defined(CONFIG_FLASH_CFI_LEGACY)
171 #include <flash.h>
board_flash_get_legacy(ulong base,int banknum,flash_info_t * info)172 ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
173 {
174 int sect[] = CONFIG_SYS_ATMEL_SECT;
175 int sectsz[] = CONFIG_SYS_ATMEL_SECTSZ;
176 int i, j, k;
177
178 if (base != CONFIG_SYS_ATMEL_BASE)
179 return 0;
180
181 info->flash_id = 0x01000000;
182 info->portwidth = 1;
183 info->chipwidth = 1;
184 info->buffer_size = 1;
185 info->erase_blk_tout = 16384;
186 info->write_tout = 2;
187 info->buffer_write_tout = 5;
188 info->vendor = 0xFFF0; /* CFI_CMDSET_AMD_LEGACY */
189 info->cmd_reset = 0x00F0;
190 info->interface = FLASH_CFI_X8;
191 info->legacy_unlock = 0;
192 info->manufacturer_id = (u16) ATM_MANUFACT;
193 info->device_id = ATM_ID_LV040;
194 info->device_id2 = 0;
195
196 info->ext_addr = 0;
197 info->cfi_version = 0x3133;
198 info->cfi_offset = 0x0000;
199 info->addr_unlock1 = 0x00000555;
200 info->addr_unlock2 = 0x000002AA;
201 info->name = "CFI conformant";
202
203 info->size = 0;
204 info->sector_count = CONFIG_SYS_ATMEL_TOTALSECT;
205 info->start[0] = base;
206 for (k = 0, i = 0; i < CONFIG_SYS_ATMEL_REGION; i++) {
207 info->size += sect[i] * sectsz[i];
208
209 for (j = 0; j < sect[i]; j++, k++) {
210 info->start[k + 1] = info->start[k] + sectsz[i];
211 info->protect[k] = 0;
212 }
213 }
214
215 return 1;
216 }
217 #endif /* CONFIG_SYS_FLASH_CFI */
218