1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) Excito Elektronik i Skåne AB, 2010.
4 * Author: Tor Krill <tor@excito.com>
5 *
6 * Copyright (C) 2015, 2019 Stefan Roese <sr@denx.de>
7 */
8
9 /*
10 * This driver supports the SATA controller of some Mavell SoC's.
11 * Here a (most likely incomplete) list of the supported SoC's:
12 * - Kirkwood
13 * - Armada 370
14 * - Armada XP
15 *
16 * This driver implementation is an alternative to the already available
17 * driver via the "ide" commands interface (drivers/block/mvsata_ide.c).
18 * But this driver only supports PIO mode and as this new driver also
19 * supports transfer via DMA, its much faster.
20 *
21 * Please note, that the newer SoC's (e.g. Armada 38x) are not supported
22 * by this driver. As they have an AHCI compatible SATA controller
23 * integrated.
24 */
25
26 /*
27 * TODO:
28 * Better error recovery
29 * No support for using PRDs (Thus max 64KB transfers)
30 * No NCQ support
31 * No port multiplier support
32 */
33
34 #include <common.h>
35 #include <ahci.h>
36 #include <blk.h>
37 #include <cpu_func.h>
38 #include <dm.h>
39 #include <log.h>
40 #include <asm/cache.h>
41 #include <asm/global_data.h>
42 #include <dm/device-internal.h>
43 #include <dm/lists.h>
44 #include <fis.h>
45 #include <libata.h>
46 #include <malloc.h>
47 #include <sata.h>
48 #include <linux/bitops.h>
49 #include <linux/delay.h>
50 #include <linux/errno.h>
51 #include <asm/io.h>
52 #include <linux/mbus.h>
53
54 #include <asm/arch/soc.h>
55 #if defined(CONFIG_ARCH_KIRKWOOD)
56 #define SATAHC_BASE KW_SATA_BASE
57 #else
58 #define SATAHC_BASE MVEBU_AXP_SATA_BASE
59 #endif
60
61 #define SATA0_BASE (SATAHC_BASE + 0x2000)
62 #define SATA1_BASE (SATAHC_BASE + 0x4000)
63
64 /* EDMA registers */
65 #define EDMA_CFG 0x000
66 #define EDMA_CFG_NCQ (1 << 5)
67 #define EDMA_CFG_EQUE (1 << 9)
68 #define EDMA_TIMER 0x004
69 #define EDMA_IECR 0x008
70 #define EDMA_IEMR 0x00c
71 #define EDMA_RQBA_HI 0x010
72 #define EDMA_RQIPR 0x014
73 #define EDMA_RQIPR_IPMASK (0x1f << 5)
74 #define EDMA_RQIPR_IPSHIFT 5
75 #define EDMA_RQOPR 0x018
76 #define EDMA_RQOPR_OPMASK (0x1f << 5)
77 #define EDMA_RQOPR_OPSHIFT 5
78 #define EDMA_RSBA_HI 0x01c
79 #define EDMA_RSIPR 0x020
80 #define EDMA_RSIPR_IPMASK (0x1f << 3)
81 #define EDMA_RSIPR_IPSHIFT 3
82 #define EDMA_RSOPR 0x024
83 #define EDMA_RSOPR_OPMASK (0x1f << 3)
84 #define EDMA_RSOPR_OPSHIFT 3
85 #define EDMA_CMD 0x028
86 #define EDMA_CMD_ENEDMA (0x01 << 0)
87 #define EDMA_CMD_DISEDMA (0x01 << 1)
88 #define EDMA_CMD_ATARST (0x01 << 2)
89 #define EDMA_CMD_FREEZE (0x01 << 4)
90 #define EDMA_TEST_CTL 0x02c
91 #define EDMA_STATUS 0x030
92 #define EDMA_IORTO 0x034
93 #define EDMA_CDTR 0x040
94 #define EDMA_HLTCND 0x060
95 #define EDMA_NTSR 0x094
96
97 /* Basic DMA registers */
98 #define BDMA_CMD 0x224
99 #define BDMA_STATUS 0x228
100 #define BDMA_DTLB 0x22c
101 #define BDMA_DTHB 0x230
102 #define BDMA_DRL 0x234
103 #define BDMA_DRH 0x238
104
105 /* SATA Interface registers */
106 #define SIR_ICFG 0x050
107 #define SIR_CFG_GEN2EN (0x1 << 7)
108 #define SIR_PLL_CFG 0x054
109 #define SIR_SSTATUS 0x300
110 #define SSTATUS_DET_MASK (0x0f << 0)
111 #define SIR_SERROR 0x304
112 #define SIR_SCONTROL 0x308
113 #define SIR_SCONTROL_DETEN (0x01 << 0)
114 #define SIR_LTMODE 0x30c
115 #define SIR_LTMODE_NELBE (0x01 << 7)
116 #define SIR_PHYMODE3 0x310
117 #define SIR_PHYMODE4 0x314
118 #define SIR_PHYMODE1 0x32c
119 #define SIR_PHYMODE2 0x330
120 #define SIR_BIST_CTRL 0x334
121 #define SIR_BIST_DW1 0x338
122 #define SIR_BIST_DW2 0x33c
123 #define SIR_SERR_IRQ_MASK 0x340
124 #define SIR_SATA_IFCTRL 0x344
125 #define SIR_SATA_TESTCTRL 0x348
126 #define SIR_SATA_IFSTATUS 0x34c
127 #define SIR_VEND_UNIQ 0x35c
128 #define SIR_FIS_CFG 0x360
129 #define SIR_FIS_IRQ_CAUSE 0x364
130 #define SIR_FIS_IRQ_MASK 0x368
131 #define SIR_FIS_DWORD0 0x370
132 #define SIR_FIS_DWORD1 0x374
133 #define SIR_FIS_DWORD2 0x378
134 #define SIR_FIS_DWORD3 0x37c
135 #define SIR_FIS_DWORD4 0x380
136 #define SIR_FIS_DWORD5 0x384
137 #define SIR_FIS_DWORD6 0x388
138 #define SIR_PHYM9_GEN2 0x398
139 #define SIR_PHYM9_GEN1 0x39c
140 #define SIR_PHY_CFG 0x3a0
141 #define SIR_PHYCTL 0x3a4
142 #define SIR_PHYM10 0x3a8
143 #define SIR_PHYM12 0x3b0
144
145 /* Shadow registers */
146 #define PIO_DATA 0x100
147 #define PIO_ERR_FEATURES 0x104
148 #define PIO_SECTOR_COUNT 0x108
149 #define PIO_LBA_LOW 0x10c
150 #define PIO_LBA_MID 0x110
151 #define PIO_LBA_HI 0x114
152 #define PIO_DEVICE 0x118
153 #define PIO_CMD_STATUS 0x11c
154 #define PIO_STATUS_ERR (0x01 << 0)
155 #define PIO_STATUS_DRQ (0x01 << 3)
156 #define PIO_STATUS_DF (0x01 << 5)
157 #define PIO_STATUS_DRDY (0x01 << 6)
158 #define PIO_STATUS_BSY (0x01 << 7)
159 #define PIO_CTRL_ALTSTAT 0x120
160
161 /* SATAHC arbiter registers */
162 #define SATAHC_CFG 0x000
163 #define SATAHC_RQOP 0x004
164 #define SATAHC_RQIP 0x008
165 #define SATAHC_ICT 0x00c
166 #define SATAHC_ITT 0x010
167 #define SATAHC_ICR 0x014
168 #define SATAHC_ICR_PORT0 (0x01 << 0)
169 #define SATAHC_ICR_PORT1 (0x01 << 1)
170 #define SATAHC_MIC 0x020
171 #define SATAHC_MIM 0x024
172 #define SATAHC_LED_CFG 0x02c
173
174 #define REQUEST_QUEUE_SIZE 32
175 #define RESPONSE_QUEUE_SIZE REQUEST_QUEUE_SIZE
176
177 struct crqb {
178 u32 dtb_low; /* DW0 */
179 u32 dtb_high; /* DW1 */
180 u32 control_flags; /* DW2 */
181 u32 drb_count; /* DW3 */
182 u32 ata_cmd_feat; /* DW4 */
183 u32 ata_addr; /* DW5 */
184 u32 ata_addr_exp; /* DW6 */
185 u32 ata_sect_count; /* DW7 */
186 };
187
188 #define CRQB_ALIGN 0x400
189
190 #define CRQB_CNTRLFLAGS_DIR (0x01 << 0)
191 #define CRQB_CNTRLFLAGS_DQTAGMASK (0x1f << 1)
192 #define CRQB_CNTRLFLAGS_DQTAGSHIFT 1
193 #define CRQB_CNTRLFLAGS_PMPORTMASK (0x0f << 12)
194 #define CRQB_CNTRLFLAGS_PMPORTSHIFT 12
195 #define CRQB_CNTRLFLAGS_PRDMODE (0x01 << 16)
196 #define CRQB_CNTRLFLAGS_HQTAGMASK (0x1f << 17)
197 #define CRQB_CNTRLFLAGS_HQTAGSHIFT 17
198
199 #define CRQB_CMDFEAT_CMDMASK (0xff << 16)
200 #define CRQB_CMDFEAT_CMDSHIFT 16
201 #define CRQB_CMDFEAT_FEATMASK (0xff << 16)
202 #define CRQB_CMDFEAT_FEATSHIFT 24
203
204 #define CRQB_ADDR_LBA_LOWMASK (0xff << 0)
205 #define CRQB_ADDR_LBA_LOWSHIFT 0
206 #define CRQB_ADDR_LBA_MIDMASK (0xff << 8)
207 #define CRQB_ADDR_LBA_MIDSHIFT 8
208 #define CRQB_ADDR_LBA_HIGHMASK (0xff << 16)
209 #define CRQB_ADDR_LBA_HIGHSHIFT 16
210 #define CRQB_ADDR_DEVICE_MASK (0xff << 24)
211 #define CRQB_ADDR_DEVICE_SHIFT 24
212
213 #define CRQB_ADDR_LBA_LOW_EXP_MASK (0xff << 0)
214 #define CRQB_ADDR_LBA_LOW_EXP_SHIFT 0
215 #define CRQB_ADDR_LBA_MID_EXP_MASK (0xff << 8)
216 #define CRQB_ADDR_LBA_MID_EXP_SHIFT 8
217 #define CRQB_ADDR_LBA_HIGH_EXP_MASK (0xff << 16)
218 #define CRQB_ADDR_LBA_HIGH_EXP_SHIFT 16
219 #define CRQB_ADDR_FEATURE_EXP_MASK (0xff << 24)
220 #define CRQB_ADDR_FEATURE_EXP_SHIFT 24
221
222 #define CRQB_SECTCOUNT_COUNT_MASK (0xff << 0)
223 #define CRQB_SECTCOUNT_COUNT_SHIFT 0
224 #define CRQB_SECTCOUNT_COUNT_EXP_MASK (0xff << 8)
225 #define CRQB_SECTCOUNT_COUNT_EXP_SHIFT 8
226
227 #define MVSATA_WIN_CONTROL(w) (SATAHC_BASE + 0x30 + ((w) << 4))
228 #define MVSATA_WIN_BASE(w) (SATAHC_BASE + 0x34 + ((w) << 4))
229
230 struct eprd {
231 u32 phyaddr_low;
232 u32 bytecount_eot;
233 u32 phyaddr_hi;
234 u32 reserved;
235 };
236
237 #define EPRD_PHYADDR_MASK 0xfffffffe
238 #define EPRD_BYTECOUNT_MASK 0x0000ffff
239 #define EPRD_EOT (0x01 << 31)
240
241 struct crpb {
242 u32 id;
243 u32 flags;
244 u32 timestamp;
245 };
246
247 #define CRPB_ALIGN 0x100
248
249 #define READ_CMD 0
250 #define WRITE_CMD 1
251
252 /*
253 * Since we don't use PRDs yet max transfer size
254 * is 64KB
255 */
256 #define MV_ATA_MAX_SECTORS (65535 / ATA_SECT_SIZE)
257
258 /* Keep track if hw is initialized or not */
259 static u32 hw_init;
260
261 struct mv_priv {
262 char name[12];
263 u32 link;
264 u32 regbase;
265 u32 queue_depth;
266 u16 pio;
267 u16 mwdma;
268 u16 udma;
269 int dev_nr;
270
271 void *crqb_alloc;
272 struct crqb *request;
273
274 void *crpb_alloc;
275 struct crpb *response;
276 };
277
ata_wait_register(u32 * addr,u32 mask,u32 val,u32 timeout_msec)278 static int ata_wait_register(u32 *addr, u32 mask, u32 val, u32 timeout_msec)
279 {
280 ulong start;
281
282 start = get_timer(0);
283 do {
284 if ((in_le32(addr) & mask) == val)
285 return 0;
286 } while (get_timer(start) < timeout_msec);
287
288 return -ETIMEDOUT;
289 }
290
291 /* Cut from sata_mv in linux kernel */
mv_stop_edma_engine(struct udevice * dev,int port)292 static int mv_stop_edma_engine(struct udevice *dev, int port)
293 {
294 struct mv_priv *priv = dev_get_plat(dev);
295 int i;
296
297 /* Disable eDMA. The disable bit auto clears. */
298 out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_DISEDMA);
299
300 /* Wait for the chip to confirm eDMA is off. */
301 for (i = 10000; i > 0; i--) {
302 u32 reg = in_le32(priv->regbase + EDMA_CMD);
303 if (!(reg & EDMA_CMD_ENEDMA)) {
304 debug("EDMA stop on port %d succesful\n", port);
305 return 0;
306 }
307 udelay(10);
308 }
309 debug("EDMA stop on port %d failed\n", port);
310 return -1;
311 }
312
mv_start_edma_engine(struct udevice * dev,int port)313 static int mv_start_edma_engine(struct udevice *dev, int port)
314 {
315 struct mv_priv *priv = dev_get_plat(dev);
316 u32 tmp;
317
318 /* Check preconditions */
319 tmp = in_le32(priv->regbase + SIR_SSTATUS);
320 if ((tmp & SSTATUS_DET_MASK) != 0x03) {
321 printf("Device error on port: %d\n", port);
322 return -1;
323 }
324
325 tmp = in_le32(priv->regbase + PIO_CMD_STATUS);
326 if (tmp & (ATA_BUSY | ATA_DRQ)) {
327 printf("Device not ready on port: %d\n", port);
328 return -1;
329 }
330
331 /* Clear interrupt cause */
332 out_le32(priv->regbase + EDMA_IECR, 0x0);
333
334 tmp = in_le32(SATAHC_BASE + SATAHC_ICR);
335 tmp &= ~(port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1);
336 out_le32(SATAHC_BASE + SATAHC_ICR, tmp);
337
338 /* Configure edma operation */
339 tmp = in_le32(priv->regbase + EDMA_CFG);
340 tmp &= ~EDMA_CFG_NCQ; /* No NCQ */
341 tmp &= ~EDMA_CFG_EQUE; /* Dont queue operations */
342 out_le32(priv->regbase + EDMA_CFG, tmp);
343
344 out_le32(priv->regbase + SIR_FIS_IRQ_CAUSE, 0x0);
345
346 /* Configure fis, set all to no-wait for now */
347 out_le32(priv->regbase + SIR_FIS_CFG, 0x0);
348
349 /* Setup request queue */
350 out_le32(priv->regbase + EDMA_RQBA_HI, 0x0);
351 out_le32(priv->regbase + EDMA_RQIPR, priv->request);
352 out_le32(priv->regbase + EDMA_RQOPR, 0x0);
353
354 /* Setup response queue */
355 out_le32(priv->regbase + EDMA_RSBA_HI, 0x0);
356 out_le32(priv->regbase + EDMA_RSOPR, priv->response);
357 out_le32(priv->regbase + EDMA_RSIPR, 0x0);
358
359 /* Start edma */
360 out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ENEDMA);
361
362 return 0;
363 }
364
mv_reset_channel(struct udevice * dev,int port)365 static int mv_reset_channel(struct udevice *dev, int port)
366 {
367 struct mv_priv *priv = dev_get_plat(dev);
368
369 /* Make sure edma is stopped */
370 mv_stop_edma_engine(dev, port);
371
372 out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ATARST);
373 udelay(25); /* allow reset propagation */
374 out_le32(priv->regbase + EDMA_CMD, 0);
375 mdelay(10);
376
377 return 0;
378 }
379
mv_reset_port(struct udevice * dev,int port)380 static void mv_reset_port(struct udevice *dev, int port)
381 {
382 struct mv_priv *priv = dev_get_plat(dev);
383
384 mv_reset_channel(dev, port);
385
386 out_le32(priv->regbase + EDMA_CMD, 0x0);
387 out_le32(priv->regbase + EDMA_CFG, 0x101f);
388 out_le32(priv->regbase + EDMA_IECR, 0x0);
389 out_le32(priv->regbase + EDMA_IEMR, 0x0);
390 out_le32(priv->regbase + EDMA_RQBA_HI, 0x0);
391 out_le32(priv->regbase + EDMA_RQIPR, 0x0);
392 out_le32(priv->regbase + EDMA_RQOPR, 0x0);
393 out_le32(priv->regbase + EDMA_RSBA_HI, 0x0);
394 out_le32(priv->regbase + EDMA_RSIPR, 0x0);
395 out_le32(priv->regbase + EDMA_RSOPR, 0x0);
396 out_le32(priv->regbase + EDMA_IORTO, 0xfa);
397 }
398
mv_reset_one_hc(void)399 static void mv_reset_one_hc(void)
400 {
401 out_le32(SATAHC_BASE + SATAHC_ICT, 0x00);
402 out_le32(SATAHC_BASE + SATAHC_ITT, 0x00);
403 out_le32(SATAHC_BASE + SATAHC_ICR, 0x00);
404 }
405
probe_port(struct udevice * dev,int port)406 static int probe_port(struct udevice *dev, int port)
407 {
408 struct mv_priv *priv = dev_get_plat(dev);
409 int tries, tries2, set15 = 0;
410 u32 tmp;
411
412 debug("Probe port: %d\n", port);
413
414 for (tries = 0; tries < 2; tries++) {
415 /* Clear SError */
416 out_le32(priv->regbase + SIR_SERROR, 0x0);
417
418 /* trigger com-init */
419 tmp = in_le32(priv->regbase + SIR_SCONTROL);
420 tmp = (tmp & 0x0f0) | 0x300 | SIR_SCONTROL_DETEN;
421 out_le32(priv->regbase + SIR_SCONTROL, tmp);
422
423 mdelay(1);
424
425 tmp = in_le32(priv->regbase + SIR_SCONTROL);
426 tries2 = 5;
427 do {
428 tmp = (tmp & 0x0f0) | 0x300;
429 out_le32(priv->regbase + SIR_SCONTROL, tmp);
430 mdelay(10);
431 tmp = in_le32(priv->regbase + SIR_SCONTROL);
432 } while ((tmp & 0xf0f) != 0x300 && tries2--);
433
434 mdelay(10);
435
436 for (tries2 = 0; tries2 < 200; tries2++) {
437 tmp = in_le32(priv->regbase + SIR_SSTATUS);
438 if ((tmp & SSTATUS_DET_MASK) == 0x03) {
439 debug("Found device on port\n");
440 return 0;
441 }
442 mdelay(1);
443 }
444
445 if ((tmp & SSTATUS_DET_MASK) == 0) {
446 debug("No device attached on port %d\n", port);
447 return -ENODEV;
448 }
449
450 if (!set15) {
451 /* Try on 1.5Gb/S */
452 debug("Try 1.5Gb link\n");
453 set15 = 1;
454 out_le32(priv->regbase + SIR_SCONTROL, 0x304);
455
456 tmp = in_le32(priv->regbase + SIR_ICFG);
457 tmp &= ~SIR_CFG_GEN2EN;
458 out_le32(priv->regbase + SIR_ICFG, tmp);
459
460 mv_reset_channel(dev, port);
461 }
462 }
463
464 debug("Failed to probe port\n");
465 return -1;
466 }
467
468 /* Get request queue in pointer */
get_reqip(struct udevice * dev,int port)469 static int get_reqip(struct udevice *dev, int port)
470 {
471 struct mv_priv *priv = dev_get_plat(dev);
472 u32 tmp;
473
474 tmp = in_le32(priv->regbase + EDMA_RQIPR) & EDMA_RQIPR_IPMASK;
475 tmp = tmp >> EDMA_RQIPR_IPSHIFT;
476
477 return tmp;
478 }
479
set_reqip(struct udevice * dev,int port,int reqin)480 static void set_reqip(struct udevice *dev, int port, int reqin)
481 {
482 struct mv_priv *priv = dev_get_plat(dev);
483 u32 tmp;
484
485 tmp = in_le32(priv->regbase + EDMA_RQIPR) & ~EDMA_RQIPR_IPMASK;
486 tmp |= ((reqin << EDMA_RQIPR_IPSHIFT) & EDMA_RQIPR_IPMASK);
487 out_le32(priv->regbase + EDMA_RQIPR, tmp);
488 }
489
490 /* Get next available slot, ignoring possible overwrite */
get_next_reqip(struct udevice * dev,int port)491 static int get_next_reqip(struct udevice *dev, int port)
492 {
493 int slot = get_reqip(dev, port);
494 slot = (slot + 1) % REQUEST_QUEUE_SIZE;
495 return slot;
496 }
497
498 /* Get response queue in pointer */
get_rspip(struct udevice * dev,int port)499 static int get_rspip(struct udevice *dev, int port)
500 {
501 struct mv_priv *priv = dev_get_plat(dev);
502 u32 tmp;
503
504 tmp = in_le32(priv->regbase + EDMA_RSIPR) & EDMA_RSIPR_IPMASK;
505 tmp = tmp >> EDMA_RSIPR_IPSHIFT;
506
507 return tmp;
508 }
509
510 /* Get response queue out pointer */
get_rspop(struct udevice * dev,int port)511 static int get_rspop(struct udevice *dev, int port)
512 {
513 struct mv_priv *priv = dev_get_plat(dev);
514 u32 tmp;
515
516 tmp = in_le32(priv->regbase + EDMA_RSOPR) & EDMA_RSOPR_OPMASK;
517 tmp = tmp >> EDMA_RSOPR_OPSHIFT;
518 return tmp;
519 }
520
521 /* Get next response queue pointer */
get_next_rspop(struct udevice * dev,int port)522 static int get_next_rspop(struct udevice *dev, int port)
523 {
524 return (get_rspop(dev, port) + 1) % RESPONSE_QUEUE_SIZE;
525 }
526
527 /* Set response queue pointer */
set_rspop(struct udevice * dev,int port,int reqin)528 static void set_rspop(struct udevice *dev, int port, int reqin)
529 {
530 struct mv_priv *priv = dev_get_plat(dev);
531 u32 tmp;
532
533 tmp = in_le32(priv->regbase + EDMA_RSOPR) & ~EDMA_RSOPR_OPMASK;
534 tmp |= ((reqin << EDMA_RSOPR_OPSHIFT) & EDMA_RSOPR_OPMASK);
535
536 out_le32(priv->regbase + EDMA_RSOPR, tmp);
537 }
538
wait_dma_completion(struct udevice * dev,int port,int index,u32 timeout_msec)539 static int wait_dma_completion(struct udevice *dev, int port, int index,
540 u32 timeout_msec)
541 {
542 u32 tmp, res;
543
544 tmp = port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1;
545 res = ata_wait_register((u32 *)(SATAHC_BASE + SATAHC_ICR), tmp,
546 tmp, timeout_msec);
547 if (res)
548 printf("Failed to wait for completion on port %d\n", port);
549
550 return res;
551 }
552
process_responses(struct udevice * dev,int port)553 static void process_responses(struct udevice *dev, int port)
554 {
555 #ifdef DEBUG
556 struct mv_priv *priv = dev_get_plat(dev);
557 #endif
558 u32 tmp;
559 u32 outind = get_rspop(dev, port);
560
561 /* Ack interrupts */
562 tmp = in_le32(SATAHC_BASE + SATAHC_ICR);
563 if (port == 0)
564 tmp &= ~(BIT(0) | BIT(8));
565 else
566 tmp &= ~(BIT(1) | BIT(9));
567 tmp &= ~(BIT(4));
568 out_le32(SATAHC_BASE + SATAHC_ICR, tmp);
569
570 while (get_rspip(dev, port) != outind) {
571 #ifdef DEBUG
572 debug("Response index %d flags %08x on port %d\n", outind,
573 priv->response[outind].flags, port);
574 #endif
575 outind = get_next_rspop(dev, port);
576 set_rspop(dev, port, outind);
577 }
578 }
579
mv_ata_exec_ata_cmd(struct udevice * dev,int port,struct sata_fis_h2d * cfis,u8 * buffer,u32 len,u32 iswrite)580 static int mv_ata_exec_ata_cmd(struct udevice *dev, int port,
581 struct sata_fis_h2d *cfis,
582 u8 *buffer, u32 len, u32 iswrite)
583 {
584 struct mv_priv *priv = dev_get_plat(dev);
585 struct crqb *req;
586 int slot;
587 u32 start;
588
589 if (len >= 64 * 1024) {
590 printf("We only support <64K transfers for now\n");
591 return -1;
592 }
593
594 /* Initialize request */
595 slot = get_reqip(dev, port);
596 memset(&priv->request[slot], 0, sizeof(struct crqb));
597 req = &priv->request[slot];
598
599 req->dtb_low = (u32)buffer;
600
601 /* Dont use PRDs */
602 req->control_flags = CRQB_CNTRLFLAGS_PRDMODE;
603 req->control_flags |= iswrite ? 0 : CRQB_CNTRLFLAGS_DIR;
604 req->control_flags |=
605 ((cfis->pm_port_c << CRQB_CNTRLFLAGS_PMPORTSHIFT)
606 & CRQB_CNTRLFLAGS_PMPORTMASK);
607
608 req->drb_count = len;
609
610 req->ata_cmd_feat = (cfis->command << CRQB_CMDFEAT_CMDSHIFT) &
611 CRQB_CMDFEAT_CMDMASK;
612 req->ata_cmd_feat |= (cfis->features << CRQB_CMDFEAT_FEATSHIFT) &
613 CRQB_CMDFEAT_FEATMASK;
614
615 req->ata_addr = (cfis->lba_low << CRQB_ADDR_LBA_LOWSHIFT) &
616 CRQB_ADDR_LBA_LOWMASK;
617 req->ata_addr |= (cfis->lba_mid << CRQB_ADDR_LBA_MIDSHIFT) &
618 CRQB_ADDR_LBA_MIDMASK;
619 req->ata_addr |= (cfis->lba_high << CRQB_ADDR_LBA_HIGHSHIFT) &
620 CRQB_ADDR_LBA_HIGHMASK;
621 req->ata_addr |= (cfis->device << CRQB_ADDR_DEVICE_SHIFT) &
622 CRQB_ADDR_DEVICE_MASK;
623
624 req->ata_addr_exp = (cfis->lba_low_exp << CRQB_ADDR_LBA_LOW_EXP_SHIFT) &
625 CRQB_ADDR_LBA_LOW_EXP_MASK;
626 req->ata_addr_exp |=
627 (cfis->lba_mid_exp << CRQB_ADDR_LBA_MID_EXP_SHIFT) &
628 CRQB_ADDR_LBA_MID_EXP_MASK;
629 req->ata_addr_exp |=
630 (cfis->lba_high_exp << CRQB_ADDR_LBA_HIGH_EXP_SHIFT) &
631 CRQB_ADDR_LBA_HIGH_EXP_MASK;
632 req->ata_addr_exp |=
633 (cfis->features_exp << CRQB_ADDR_FEATURE_EXP_SHIFT) &
634 CRQB_ADDR_FEATURE_EXP_MASK;
635
636 req->ata_sect_count =
637 (cfis->sector_count << CRQB_SECTCOUNT_COUNT_SHIFT) &
638 CRQB_SECTCOUNT_COUNT_MASK;
639 req->ata_sect_count |=
640 (cfis->sector_count_exp << CRQB_SECTCOUNT_COUNT_EXP_SHIFT) &
641 CRQB_SECTCOUNT_COUNT_EXP_MASK;
642
643 /* Flush data */
644 start = (u32)req & ~(ARCH_DMA_MINALIGN - 1);
645 flush_dcache_range(start,
646 start + ALIGN(sizeof(*req), ARCH_DMA_MINALIGN));
647
648 /* Trigger operation */
649 slot = get_next_reqip(dev, port);
650 set_reqip(dev, port, slot);
651
652 /* Wait for completion */
653 if (wait_dma_completion(dev, port, slot, 10000)) {
654 printf("ATA operation timed out\n");
655 return -1;
656 }
657
658 process_responses(dev, port);
659
660 /* Invalidate data on read */
661 if (buffer && len) {
662 start = (u32)buffer & ~(ARCH_DMA_MINALIGN - 1);
663 invalidate_dcache_range(start,
664 start + ALIGN(len, ARCH_DMA_MINALIGN));
665 }
666
667 return len;
668 }
669
mv_sata_rw_cmd_ext(struct udevice * dev,int port,lbaint_t start,u32 blkcnt,u8 * buffer,int is_write)670 static u32 mv_sata_rw_cmd_ext(struct udevice *dev, int port, lbaint_t start,
671 u32 blkcnt,
672 u8 *buffer, int is_write)
673 {
674 struct sata_fis_h2d cfis;
675 u32 res;
676 u64 block;
677
678 block = (u64)start;
679
680 memset(&cfis, 0, sizeof(struct sata_fis_h2d));
681
682 cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
683 cfis.command = (is_write) ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
684
685 cfis.lba_high_exp = (block >> 40) & 0xff;
686 cfis.lba_mid_exp = (block >> 32) & 0xff;
687 cfis.lba_low_exp = (block >> 24) & 0xff;
688 cfis.lba_high = (block >> 16) & 0xff;
689 cfis.lba_mid = (block >> 8) & 0xff;
690 cfis.lba_low = block & 0xff;
691 cfis.device = ATA_LBA;
692 cfis.sector_count_exp = (blkcnt >> 8) & 0xff;
693 cfis.sector_count = blkcnt & 0xff;
694
695 res = mv_ata_exec_ata_cmd(dev, port, &cfis, buffer,
696 ATA_SECT_SIZE * blkcnt, is_write);
697
698 return res >= 0 ? blkcnt : res;
699 }
700
mv_sata_rw_cmd(struct udevice * dev,int port,lbaint_t start,u32 blkcnt,u8 * buffer,int is_write)701 static u32 mv_sata_rw_cmd(struct udevice *dev, int port, lbaint_t start,
702 u32 blkcnt, u8 *buffer, int is_write)
703 {
704 struct sata_fis_h2d cfis;
705 lbaint_t block;
706 u32 res;
707
708 block = start;
709
710 memset(&cfis, 0, sizeof(struct sata_fis_h2d));
711
712 cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
713 cfis.command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
714 cfis.device = ATA_LBA;
715
716 cfis.device |= (block >> 24) & 0xf;
717 cfis.lba_high = (block >> 16) & 0xff;
718 cfis.lba_mid = (block >> 8) & 0xff;
719 cfis.lba_low = block & 0xff;
720 cfis.sector_count = (u8)(blkcnt & 0xff);
721
722 res = mv_ata_exec_ata_cmd(dev, port, &cfis, buffer,
723 ATA_SECT_SIZE * blkcnt, is_write);
724
725 return res >= 0 ? blkcnt : res;
726 }
727
ata_low_level_rw(struct udevice * dev,int port,lbaint_t blknr,lbaint_t blkcnt,void * buffer,int is_write)728 static u32 ata_low_level_rw(struct udevice *dev, int port, lbaint_t blknr,
729 lbaint_t blkcnt, void *buffer, int is_write)
730 {
731 struct blk_desc *desc = dev_get_uclass_plat(dev);
732 lbaint_t start, blks;
733 u8 *addr;
734 int max_blks;
735
736 debug("%s: " LBAFU " " LBAFU "\n", __func__, blknr, blkcnt);
737
738 start = blknr;
739 blks = blkcnt;
740 addr = (u8 *)buffer;
741
742 max_blks = MV_ATA_MAX_SECTORS;
743 do {
744 if (blks > max_blks) {
745 if (desc->lba48) {
746 mv_sata_rw_cmd_ext(dev, port, start, max_blks,
747 addr, is_write);
748 } else {
749 mv_sata_rw_cmd(dev, port, start, max_blks,
750 addr, is_write);
751 }
752 start += max_blks;
753 blks -= max_blks;
754 addr += ATA_SECT_SIZE * max_blks;
755 } else {
756 if (desc->lba48) {
757 mv_sata_rw_cmd_ext(dev, port, start, blks, addr,
758 is_write);
759 } else {
760 mv_sata_rw_cmd(dev, port, start, blks, addr,
761 is_write);
762 }
763 start += blks;
764 blks = 0;
765 addr += ATA_SECT_SIZE * blks;
766 }
767 } while (blks != 0);
768
769 return blkcnt;
770 }
771
mv_ata_exec_ata_cmd_nondma(struct udevice * dev,int port,struct sata_fis_h2d * cfis,u8 * buffer,u32 len,u32 iswrite)772 static int mv_ata_exec_ata_cmd_nondma(struct udevice *dev, int port,
773 struct sata_fis_h2d *cfis, u8 *buffer,
774 u32 len, u32 iswrite)
775 {
776 struct mv_priv *priv = dev_get_plat(dev);
777 int i;
778 u16 *tp;
779
780 debug("%s\n", __func__);
781
782 out_le32(priv->regbase + PIO_SECTOR_COUNT, cfis->sector_count);
783 out_le32(priv->regbase + PIO_LBA_HI, cfis->lba_high);
784 out_le32(priv->regbase + PIO_LBA_MID, cfis->lba_mid);
785 out_le32(priv->regbase + PIO_LBA_LOW, cfis->lba_low);
786 out_le32(priv->regbase + PIO_ERR_FEATURES, cfis->features);
787 out_le32(priv->regbase + PIO_DEVICE, cfis->device);
788 out_le32(priv->regbase + PIO_CMD_STATUS, cfis->command);
789
790 if (ata_wait_register((u32 *)(priv->regbase + PIO_CMD_STATUS),
791 ATA_BUSY, 0x0, 10000)) {
792 debug("Failed to wait for completion\n");
793 return -1;
794 }
795
796 if (len > 0) {
797 tp = (u16 *)buffer;
798 for (i = 0; i < len / 2; i++) {
799 if (iswrite)
800 out_le16(priv->regbase + PIO_DATA, *tp++);
801 else
802 *tp++ = in_le16(priv->regbase + PIO_DATA);
803 }
804 }
805
806 return len;
807 }
808
mv_sata_identify(struct udevice * dev,int port,u16 * id)809 static int mv_sata_identify(struct udevice *dev, int port, u16 *id)
810 {
811 struct sata_fis_h2d h2d;
812
813 memset(&h2d, 0, sizeof(struct sata_fis_h2d));
814
815 h2d.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
816 h2d.command = ATA_CMD_ID_ATA;
817
818 /* Give device time to get operational */
819 mdelay(10);
820
821 return mv_ata_exec_ata_cmd_nondma(dev, port, &h2d, (u8 *)id,
822 ATA_ID_WORDS * 2, READ_CMD);
823 }
824
mv_sata_xfer_mode(struct udevice * dev,int port,u16 * id)825 static void mv_sata_xfer_mode(struct udevice *dev, int port, u16 *id)
826 {
827 struct mv_priv *priv = dev_get_plat(dev);
828
829 priv->pio = id[ATA_ID_PIO_MODES];
830 priv->mwdma = id[ATA_ID_MWDMA_MODES];
831 priv->udma = id[ATA_ID_UDMA_MODES];
832 debug("pio %04x, mwdma %04x, udma %04x\n", priv->pio, priv->mwdma,
833 priv->udma);
834 }
835
mv_sata_set_features(struct udevice * dev,int port)836 static void mv_sata_set_features(struct udevice *dev, int port)
837 {
838 struct mv_priv *priv = dev_get_plat(dev);
839 struct sata_fis_h2d cfis;
840 u8 udma_cap;
841
842 memset(&cfis, 0, sizeof(struct sata_fis_h2d));
843
844 cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
845 cfis.command = ATA_CMD_SET_FEATURES;
846 cfis.features = SETFEATURES_XFER;
847
848 /* First check the device capablity */
849 udma_cap = (u8) (priv->udma & 0xff);
850
851 if (udma_cap == ATA_UDMA6)
852 cfis.sector_count = XFER_UDMA_6;
853 if (udma_cap == ATA_UDMA5)
854 cfis.sector_count = XFER_UDMA_5;
855 if (udma_cap == ATA_UDMA4)
856 cfis.sector_count = XFER_UDMA_4;
857 if (udma_cap == ATA_UDMA3)
858 cfis.sector_count = XFER_UDMA_3;
859
860 mv_ata_exec_ata_cmd_nondma(dev, port, &cfis, NULL, 0, READ_CMD);
861 }
862
863 /*
864 * Initialize SATA memory windows
865 */
mvsata_ide_conf_mbus_windows(void)866 static void mvsata_ide_conf_mbus_windows(void)
867 {
868 const struct mbus_dram_target_info *dram;
869 int i;
870
871 dram = mvebu_mbus_dram_info();
872
873 /* Disable windows, Set Size/Base to 0 */
874 for (i = 0; i < 4; i++) {
875 writel(0, MVSATA_WIN_CONTROL(i));
876 writel(0, MVSATA_WIN_BASE(i));
877 }
878
879 for (i = 0; i < dram->num_cs; i++) {
880 const struct mbus_dram_window *cs = dram->cs + i;
881 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
882 (dram->mbus_dram_target_id << 4) | 1,
883 MVSATA_WIN_CONTROL(i));
884 writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i));
885 }
886 }
887
sata_mv_init_sata(struct udevice * dev,int port)888 static int sata_mv_init_sata(struct udevice *dev, int port)
889 {
890 struct mv_priv *priv = dev_get_plat(dev);
891
892 debug("Initialize sata dev: %d\n", port);
893
894 if (port < 0 || port >= CONFIG_SYS_SATA_MAX_DEVICE) {
895 printf("Invalid sata device %d\n", port);
896 return -1;
897 }
898
899 /* Allocate and align request buffer */
900 priv->crqb_alloc = malloc(sizeof(struct crqb) * REQUEST_QUEUE_SIZE +
901 CRQB_ALIGN);
902 if (!priv->crqb_alloc) {
903 printf("Unable to allocate memory for request queue\n");
904 return -ENOMEM;
905 }
906 memset(priv->crqb_alloc, 0,
907 sizeof(struct crqb) * REQUEST_QUEUE_SIZE + CRQB_ALIGN);
908 priv->request = (struct crqb *)(((u32) priv->crqb_alloc + CRQB_ALIGN) &
909 ~(CRQB_ALIGN - 1));
910
911 /* Allocate and align response buffer */
912 priv->crpb_alloc = malloc(sizeof(struct crpb) * REQUEST_QUEUE_SIZE +
913 CRPB_ALIGN);
914 if (!priv->crpb_alloc) {
915 printf("Unable to allocate memory for response queue\n");
916 return -ENOMEM;
917 }
918 memset(priv->crpb_alloc, 0,
919 sizeof(struct crpb) * REQUEST_QUEUE_SIZE + CRPB_ALIGN);
920 priv->response = (struct crpb *)(((u32) priv->crpb_alloc + CRPB_ALIGN) &
921 ~(CRPB_ALIGN - 1));
922
923 sprintf(priv->name, "SATA%d", port);
924
925 priv->regbase = port == 0 ? SATA0_BASE : SATA1_BASE;
926
927 if (!hw_init) {
928 debug("Initialize sata hw\n");
929 hw_init = 1;
930 mv_reset_one_hc();
931 mvsata_ide_conf_mbus_windows();
932 }
933
934 mv_reset_port(dev, port);
935
936 if (probe_port(dev, port)) {
937 priv->link = 0;
938 return -ENODEV;
939 }
940 priv->link = 1;
941
942 return 0;
943 }
944
sata_mv_scan_sata(struct udevice * dev,int port)945 static int sata_mv_scan_sata(struct udevice *dev, int port)
946 {
947 struct blk_desc *desc = dev_get_uclass_plat(dev);
948 struct mv_priv *priv = dev_get_plat(dev);
949 unsigned char serial[ATA_ID_SERNO_LEN + 1];
950 unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
951 unsigned char product[ATA_ID_PROD_LEN + 1];
952 u64 n_sectors;
953 u16 *id;
954
955 if (!priv->link)
956 return -ENODEV;
957
958 id = (u16 *)malloc(ATA_ID_WORDS * 2);
959 if (!id) {
960 printf("Failed to malloc id data\n");
961 return -ENOMEM;
962 }
963
964 mv_sata_identify(dev, port, id);
965 ata_swap_buf_le16(id, ATA_ID_WORDS);
966 #ifdef DEBUG
967 ata_dump_id(id);
968 #endif
969
970 /* Serial number */
971 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
972 memcpy(desc->product, serial, sizeof(serial));
973
974 /* Firmware version */
975 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
976 memcpy(desc->revision, firmware, sizeof(firmware));
977
978 /* Product model */
979 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
980 memcpy(desc->vendor, product, sizeof(product));
981
982 /* Total sectors */
983 n_sectors = ata_id_n_sectors(id);
984 desc->lba = n_sectors;
985
986 /* Check if support LBA48 */
987 if (ata_id_has_lba48(id)) {
988 desc->lba48 = 1;
989 debug("Device support LBA48\n");
990 }
991
992 /* Get the NCQ queue depth from device */
993 priv->queue_depth = ata_id_queue_depth(id);
994
995 /* Get the xfer mode from device */
996 mv_sata_xfer_mode(dev, port, id);
997
998 /* Set the xfer mode to highest speed */
999 mv_sata_set_features(dev, port);
1000
1001 /* Start up */
1002 mv_start_edma_engine(dev, port);
1003
1004 return 0;
1005 }
1006
sata_mv_read(struct udevice * blk,lbaint_t blknr,lbaint_t blkcnt,void * buffer)1007 static ulong sata_mv_read(struct udevice *blk, lbaint_t blknr,
1008 lbaint_t blkcnt, void *buffer)
1009 {
1010 struct mv_priv *priv = dev_get_plat(blk);
1011
1012 return ata_low_level_rw(blk, priv->dev_nr, blknr, blkcnt,
1013 buffer, READ_CMD);
1014 }
1015
sata_mv_write(struct udevice * blk,lbaint_t blknr,lbaint_t blkcnt,const void * buffer)1016 static ulong sata_mv_write(struct udevice *blk, lbaint_t blknr,
1017 lbaint_t blkcnt, const void *buffer)
1018 {
1019 struct mv_priv *priv = dev_get_plat(blk);
1020
1021 return ata_low_level_rw(blk, priv->dev_nr, blknr, blkcnt,
1022 (void *)buffer, WRITE_CMD);
1023 }
1024
1025 static const struct blk_ops sata_mv_blk_ops = {
1026 .read = sata_mv_read,
1027 .write = sata_mv_write,
1028 };
1029
1030 U_BOOT_DRIVER(sata_mv_driver) = {
1031 .name = "sata_mv_blk",
1032 .id = UCLASS_BLK,
1033 .ops = &sata_mv_blk_ops,
1034 .plat_auto = sizeof(struct mv_priv),
1035 };
1036
sata_mv_probe(struct udevice * dev)1037 static int sata_mv_probe(struct udevice *dev)
1038 {
1039 const void *blob = gd->fdt_blob;
1040 int node = dev_of_offset(dev);
1041 struct mv_priv *priv;
1042 struct udevice *blk;
1043 int nr_ports;
1044 int ret;
1045 int i;
1046
1047 /* Get number of ports of this SATA controller */
1048 nr_ports = min(fdtdec_get_int(blob, node, "nr-ports", -1),
1049 CONFIG_SYS_SATA_MAX_DEVICE);
1050
1051 for (i = 0; i < nr_ports; i++) {
1052 ret = blk_create_devicef(dev, "sata_mv_blk", "blk",
1053 IF_TYPE_SATA, -1, 512, 0, &blk);
1054 if (ret) {
1055 debug("Can't create device\n");
1056 return ret;
1057 }
1058
1059 priv = dev_get_plat(blk);
1060 priv->dev_nr = i;
1061
1062 /* Init SATA port */
1063 ret = sata_mv_init_sata(blk, i);
1064 if (ret) {
1065 debug("%s: Failed to init bus\n", __func__);
1066 return ret;
1067 }
1068
1069 /* Scan SATA port */
1070 ret = sata_mv_scan_sata(blk, i);
1071 if (ret) {
1072 debug("%s: Failed to scan bus\n", __func__);
1073 return ret;
1074 }
1075 }
1076
1077 return 0;
1078 }
1079
sata_mv_scan(struct udevice * dev)1080 static int sata_mv_scan(struct udevice *dev)
1081 {
1082 /* Nothing to do here */
1083
1084 return 0;
1085 }
1086
1087 static const struct udevice_id sata_mv_ids[] = {
1088 { .compatible = "marvell,armada-370-sata" },
1089 { .compatible = "marvell,orion-sata" },
1090 { }
1091 };
1092
1093 struct ahci_ops sata_mv_ahci_ops = {
1094 .scan = sata_mv_scan,
1095 };
1096
1097 U_BOOT_DRIVER(sata_mv_ahci) = {
1098 .name = "sata_mv_ahci",
1099 .id = UCLASS_AHCI,
1100 .of_match = sata_mv_ids,
1101 .ops = &sata_mv_ahci_ops,
1102 .probe = sata_mv_probe,
1103 };
1104