1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MediaTek clock driver for MT8183 SoC
4 *
5 * Copyright (C) 2020 BayLibre, SAS
6 * Copyright (c) 2020 MediaTek Inc.
7 * Author: Fabien Parent <fparent@baylibre.com>
8 * Author: Weiyi Lu <weiyi.lu@mediatek.com>
9 */
10
11 #include <common.h>
12 #include <dm.h>
13 #include <asm/io.h>
14 #include <dt-bindings/clock/mt8183-clk.h>
15
16 #include "clk-mtk.h"
17
18 #define MT8183_PLL_FMAX (3800UL * MHZ)
19 #define MT8183_PLL_FMIN (1500UL * MHZ)
20
21 /* apmixedsys */
22 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, _pcwbits, \
23 _pcwibits, _pd_reg, _pd_shift, _pcw_reg, _pcw_shift) { \
24 .id = _id, \
25 .reg = _reg, \
26 .pwr_reg = _pwr_reg, \
27 .en_mask = _en_mask, \
28 .rst_bar_mask = _rst_bar_mask, \
29 .fmax = MT8183_PLL_FMAX, \
30 .fmin = MT8183_PLL_FMIN, \
31 .flags = _flags, \
32 .pcwbits = _pcwbits, \
33 .pcwibits = _pcwibits, \
34 .pd_reg = _pd_reg, \
35 .pd_shift = _pd_shift, \
36 .pcw_reg = _pcw_reg, \
37 .pcw_shift = _pcw_shift, \
38 }
39
40 static const struct mtk_pll_data apmixed_plls[] = {
41 PLL(CLK_APMIXED_ARMPLL_LL, 0x0200, 0x020C, 0x00000001,
42 HAVE_RST_BAR, BIT(24), 22, 8, 0x0204, 24,
43 0x0204, 0),
44 PLL(CLK_APMIXED_ARMPLL_L, 0x0210, 0x021C, 0x00000001,
45 HAVE_RST_BAR, BIT(24), 22, 8, 0x0214, 24,
46 0x0214, 0),
47 PLL(CLK_APMIXED_CCIPLL, 0x0290, 0x029C, 0x00000001,
48 HAVE_RST_BAR, BIT(24), 22, 8, 0x0294, 24,
49 0x0294, 0),
50 PLL(CLK_APMIXED_MAINPLL, 0x0220, 0x022C, 0x00000001,
51 HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24,
52 0x0224, 0),
53 PLL(CLK_APMIXED_UNIV2PLL, 0x0230, 0x023C, 0x00000001,
54 HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24,
55 0x0234, 0),
56 PLL(CLK_APMIXED_MSDCPLL, 0x0250, 0x025C, 0x00000001,
57 0, 0, 22, 8, 0x0254, 24, 0x0254, 0),
58 PLL(CLK_APMIXED_MMPLL, 0x0270, 0x027C, 0x00000001,
59 HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24,
60 0x0274, 0),
61 PLL(CLK_APMIXED_MFGPLL, 0x0240, 0x024C, 0x00000001,
62 0, 0, 22, 8, 0x0244, 24, 0x0244, 0),
63 PLL(CLK_APMIXED_TVDPLL, 0x0260, 0x026C, 0x00000001,
64 0, 0, 22, 8, 0x0264, 24, 0x0264, 0),
65 PLL(CLK_APMIXED_APLL1, 0x02A0, 0x02B0, 0x00000001,
66 0, 0, 32, 8, 0x02A0, 1, 0x02A4, 0),
67 PLL(CLK_APMIXED_APLL2, 0x02b4, 0x02c4, 0x00000001,
68 0, 0, 32, 8, 0x02B4, 1, 0x02B8, 0),
69 };
70
71 static const struct mtk_fixed_clk top_fixed_clks[] = {
72 FIXED_CLK(CLK_TOP_CLK26M, CLK_XTAL, 26000000),
73 FIXED_CLK(CLK_TOP_ULPOSC, CLK_XTAL, 250000),
74 FIXED_CLK(CLK_TOP_UNIVP_192M, CLK_TOP_UNIVPLL, 192000000),
75 };
76
77 static const struct mtk_fixed_factor top_fixed_divs[] = {
78 FACTOR(CLK_TOP_CLK13M, CLK_TOP_CLK26M, 1, 2, CLK_PARENT_TOPCKGEN),
79 FACTOR(CLK_TOP_F26M_CK_D2, CLK_TOP_CLK26M, 1, 2, CLK_PARENT_TOPCKGEN),
80 FACTOR(CLK_TOP_SYSPLL_CK, CLK_APMIXED_MAINPLL, 1,
81 1, CLK_PARENT_APMIXED),
82 FACTOR(CLK_TOP_SYSPLL_D2, CLK_TOP_SYSPLL_CK, 1,
83 2, CLK_PARENT_TOPCKGEN),
84 FACTOR(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1,
85 3, CLK_PARENT_APMIXED),
86 FACTOR(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1,
87 5, CLK_PARENT_APMIXED),
88 FACTOR(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1,
89 7, CLK_PARENT_APMIXED),
90 FACTOR(CLK_TOP_SYSPLL_D2_D2, CLK_TOP_SYSPLL_D2, 1,
91 2, CLK_PARENT_TOPCKGEN),
92 FACTOR(CLK_TOP_SYSPLL_D2_D4, CLK_TOP_SYSPLL_D2, 1,
93 4, CLK_PARENT_TOPCKGEN),
94 FACTOR(CLK_TOP_SYSPLL_D2_D8, CLK_TOP_SYSPLL_D2, 1,
95 8, CLK_PARENT_TOPCKGEN),
96 FACTOR(CLK_TOP_SYSPLL_D2_D16, CLK_TOP_SYSPLL_D2, 1,
97 16, CLK_PARENT_TOPCKGEN),
98 FACTOR(CLK_TOP_SYSPLL_D3_D2, CLK_TOP_SYSPLL_D3, 1,
99 2, CLK_PARENT_TOPCKGEN),
100 FACTOR(CLK_TOP_SYSPLL_D3_D4, CLK_TOP_SYSPLL_D3, 1,
101 4, CLK_PARENT_TOPCKGEN),
102 FACTOR(CLK_TOP_SYSPLL_D3_D8, CLK_TOP_SYSPLL_D3, 1,
103 8, CLK_PARENT_TOPCKGEN),
104 FACTOR(CLK_TOP_SYSPLL_D5_D2, CLK_TOP_SYSPLL_D5, 1,
105 2, CLK_PARENT_TOPCKGEN),
106 FACTOR(CLK_TOP_SYSPLL_D5_D4, CLK_TOP_SYSPLL_D5, 1,
107 4, CLK_PARENT_TOPCKGEN),
108 FACTOR(CLK_TOP_SYSPLL_D7_D2, CLK_TOP_SYSPLL_D7, 1,
109 2, CLK_PARENT_TOPCKGEN),
110 FACTOR(CLK_TOP_SYSPLL_D7_D4, CLK_TOP_SYSPLL_D7, 1,
111 4, CLK_PARENT_TOPCKGEN),
112 FACTOR(CLK_TOP_UNIVPLL_CK, CLK_TOP_UNIVPLL, 1, 1, CLK_PARENT_TOPCKGEN),
113 FACTOR(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL_CK, 1,
114 2, CLK_PARENT_TOPCKGEN),
115 FACTOR(CLK_TOP_UNIVPLL_D3, CLK_TOP_UNIVPLL, 1, 3, CLK_PARENT_TOPCKGEN),
116 FACTOR(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5, CLK_PARENT_TOPCKGEN),
117 FACTOR(CLK_TOP_UNIVPLL_D7, CLK_TOP_UNIVPLL, 1, 7, CLK_PARENT_TOPCKGEN),
118 FACTOR(CLK_TOP_UNIVPLL_D2_D2, CLK_TOP_UNIVPLL_D2, 1,
119 2, CLK_PARENT_TOPCKGEN),
120 FACTOR(CLK_TOP_UNIVPLL_D2_D4, CLK_TOP_UNIVPLL_D2, 1,
121 4, CLK_PARENT_TOPCKGEN),
122 FACTOR(CLK_TOP_UNIVPLL_D2_D8, CLK_TOP_UNIVPLL_D2, 1,
123 8, CLK_PARENT_TOPCKGEN),
124 FACTOR(CLK_TOP_UNIVPLL_D3_D2, CLK_TOP_UNIVPLL_D3, 1,
125 2, CLK_PARENT_TOPCKGEN),
126 FACTOR(CLK_TOP_UNIVPLL_D3_D4, CLK_TOP_UNIVPLL_D3, 1,
127 4, CLK_PARENT_TOPCKGEN),
128 FACTOR(CLK_TOP_UNIVPLL_D3_D8, CLK_TOP_UNIVPLL_D3, 1,
129 8, CLK_PARENT_TOPCKGEN),
130 FACTOR(CLK_TOP_UNIVPLL_D5_D2, CLK_TOP_UNIVPLL_D5, 1,
131 2, CLK_PARENT_TOPCKGEN),
132 FACTOR(CLK_TOP_UNIVPLL_D5_D4, CLK_TOP_UNIVPLL_D5, 1,
133 4, CLK_PARENT_TOPCKGEN),
134 FACTOR(CLK_TOP_UNIVPLL_D5_D8, CLK_TOP_UNIVPLL_D5, 1,
135 8, CLK_PARENT_TOPCKGEN),
136 FACTOR(CLK_TOP_UNIVP_192M_CK, CLK_TOP_UNIVP_192M, 1, 1,
137 CLK_PARENT_TOPCKGEN),
138 FACTOR(CLK_TOP_UNIVP_192M_D2, CLK_TOP_UNIVP_192M_CK, 1,
139 2, CLK_PARENT_TOPCKGEN),
140 FACTOR(CLK_TOP_UNIVP_192M_D4, CLK_TOP_UNIVP_192M_CK, 1,
141 4, CLK_PARENT_TOPCKGEN),
142 FACTOR(CLK_TOP_UNIVP_192M_D8, CLK_TOP_UNIVP_192M_CK, 1,
143 8, CLK_PARENT_TOPCKGEN),
144 FACTOR(CLK_TOP_UNIVP_192M_D16, CLK_TOP_UNIVP_192M_CK, 1,
145 16, CLK_PARENT_TOPCKGEN),
146 FACTOR(CLK_TOP_UNIVP_192M_D32, CLK_TOP_UNIVP_192M_CK, 1,
147 32, CLK_PARENT_TOPCKGEN),
148 FACTOR(CLK_TOP_APLL1_CK, CLK_APMIXED_APLL1, 1, 1, CLK_PARENT_APMIXED),
149 FACTOR(CLK_TOP_APLL1_D2, CLK_APMIXED_APLL1, 1, 2, CLK_PARENT_APMIXED),
150 FACTOR(CLK_TOP_APLL1_D4, CLK_APMIXED_APLL1, 1, 4, CLK_PARENT_APMIXED),
151 FACTOR(CLK_TOP_APLL1_D8, CLK_APMIXED_APLL1, 1, 8, CLK_PARENT_APMIXED),
152 FACTOR(CLK_TOP_APLL2_CK, CLK_APMIXED_APLL2, 1, 1, CLK_PARENT_APMIXED),
153 FACTOR(CLK_TOP_APLL2_D2, CLK_APMIXED_APLL2, 1, 2, CLK_PARENT_APMIXED),
154 FACTOR(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4, CLK_PARENT_APMIXED),
155 FACTOR(CLK_TOP_APLL2_D8, CLK_APMIXED_APLL2, 1, 8, CLK_PARENT_APMIXED),
156 FACTOR(CLK_TOP_TVDPLL_CK, CLK_APMIXED_TVDPLL, 1, 1, CLK_PARENT_APMIXED),
157 FACTOR(CLK_TOP_TVDPLL_D2, CLK_TOP_TVDPLL_CK, 1, 2, CLK_PARENT_TOPCKGEN),
158 FACTOR(CLK_TOP_TVDPLL_D4, CLK_APMIXED_TVDPLL, 1, 4, CLK_PARENT_APMIXED),
159 FACTOR(CLK_TOP_TVDPLL_D8, CLK_APMIXED_TVDPLL, 1, 8, CLK_PARENT_APMIXED),
160 FACTOR(CLK_TOP_TVDPLL_D16, CLK_APMIXED_TVDPLL, 1,
161 16, CLK_PARENT_APMIXED),
162 FACTOR(CLK_TOP_MMPLL_CK, CLK_APMIXED_MMPLL, 1, 1, CLK_PARENT_APMIXED),
163 FACTOR(CLK_TOP_MMPLL_D4, CLK_APMIXED_MMPLL, 1, 4, CLK_PARENT_APMIXED),
164 FACTOR(CLK_TOP_MMPLL_D4_D2, CLK_TOP_MMPLL_D4, 1,
165 2, CLK_PARENT_TOPCKGEN),
166 FACTOR(CLK_TOP_MMPLL_D4_D4, CLK_TOP_MMPLL_D4, 1, 4, CLK_PARENT_TOPCKGEN),
167 FACTOR(CLK_TOP_MMPLL_D5, CLK_APMIXED_MMPLL, 1, 5, CLK_PARENT_APMIXED),
168 FACTOR(CLK_TOP_MMPLL_D5_D2, CLK_TOP_MMPLL_D5, 1,
169 2, CLK_PARENT_TOPCKGEN),
170 FACTOR(CLK_TOP_MMPLL_D5_D4, CLK_TOP_MMPLL_D5, 1,
171 4, CLK_PARENT_TOPCKGEN),
172 FACTOR(CLK_TOP_MMPLL_D6, CLK_APMIXED_MMPLL, 1, 6, CLK_PARENT_APMIXED),
173 FACTOR(CLK_TOP_MMPLL_D7, CLK_APMIXED_MMPLL, 1, 7, CLK_PARENT_APMIXED),
174 FACTOR(CLK_TOP_MFGPLL_CK, CLK_APMIXED_MFGPLL, 1, 1, CLK_PARENT_APMIXED),
175 FACTOR(CLK_TOP_MSDCPLL_CK, CLK_APMIXED_MSDCPLL, 1,
176 1, CLK_PARENT_APMIXED),
177 FACTOR(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1,
178 2, CLK_PARENT_APMIXED),
179 FACTOR(CLK_TOP_MSDCPLL_D4, CLK_APMIXED_MSDCPLL, 1,
180 4, CLK_PARENT_APMIXED),
181 FACTOR(CLK_TOP_MSDCPLL_D8, CLK_APMIXED_MSDCPLL, 1,
182 8, CLK_PARENT_APMIXED),
183 FACTOR(CLK_TOP_MSDCPLL_D16, CLK_APMIXED_MSDCPLL, 1,
184 16, CLK_PARENT_APMIXED),
185 FACTOR(CLK_TOP_AD_OSC_CK, CLK_TOP_ULPOSC, 1, 1, CLK_PARENT_TOPCKGEN),
186 FACTOR(CLK_TOP_OSC_D2, CLK_TOP_ULPOSC, 1, 2, CLK_PARENT_TOPCKGEN),
187 FACTOR(CLK_TOP_OSC_D4, CLK_TOP_ULPOSC, 1, 4, CLK_PARENT_TOPCKGEN),
188 FACTOR(CLK_TOP_OSC_D8, CLK_TOP_ULPOSC, 1, 8, CLK_PARENT_TOPCKGEN),
189 FACTOR(CLK_TOP_OSC_D16, CLK_TOP_ULPOSC, 1, 16, CLK_PARENT_TOPCKGEN),
190 FACTOR(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIV2PLL, 1, 2, CLK_PARENT_APMIXED),
191 FACTOR(CLK_TOP_UNIVPLL_D3_D16, CLK_TOP_UNIVPLL_D3, 1,
192 16, CLK_PARENT_TOPCKGEN),
193 };
194
195 static const int axi_parents[] = {
196 CLK_TOP_CLK26M,
197 CLK_TOP_SYSPLL_D2_D4,
198 CLK_TOP_SYSPLL_D7,
199 CLK_TOP_OSC_D4
200 };
201
202 static const int mm_parents[] = {
203 CLK_TOP_CLK26M,
204 CLK_TOP_MMPLL_D7,
205 CLK_TOP_SYSPLL_D3,
206 CLK_TOP_UNIVPLL_D2_D2,
207 CLK_TOP_SYSPLL_D2_D2,
208 CLK_TOP_SYSPLL_D3_D2
209 };
210
211 static const int img_parents[] = {
212 CLK_TOP_CLK26M,
213 CLK_TOP_MMPLL_D6,
214 CLK_TOP_UNIVPLL_D3,
215 CLK_TOP_SYSPLL_D3,
216 CLK_TOP_UNIVPLL_D2_D2,
217 CLK_TOP_SYSPLL_D2_D2,
218 CLK_TOP_UNIVPLL_D3_D2,
219 CLK_TOP_SYSPLL_D3_D2
220 };
221
222 static const int cam_parents[] = {
223 CLK_TOP_CLK26M,
224 CLK_TOP_SYSPLL_D2,
225 CLK_TOP_MMPLL_D6,
226 CLK_TOP_SYSPLL_D3,
227 CLK_TOP_MMPLL_D7,
228 CLK_TOP_UNIVPLL_D3,
229 CLK_TOP_UNIVPLL_D2_D2,
230 CLK_TOP_SYSPLL_D2_D2,
231 CLK_TOP_SYSPLL_D3_D2,
232 CLK_TOP_UNIVPLL_D3_D2
233 };
234
235 static const int dsp_parents[] = {
236 CLK_TOP_CLK26M,
237 CLK_TOP_MMPLL_D6,
238 CLK_TOP_MMPLL_D7,
239 CLK_TOP_UNIVPLL_D3,
240 CLK_TOP_SYSPLL_D3,
241 CLK_TOP_UNIVPLL_D2_D2,
242 CLK_TOP_SYSPLL_D2_D2,
243 CLK_TOP_UNIVPLL_D3_D2,
244 CLK_TOP_SYSPLL_D3_D2
245 };
246
247 static const int dsp1_parents[] = {
248 CLK_TOP_CLK26M,
249 CLK_TOP_MMPLL_D6,
250 CLK_TOP_MMPLL_D7,
251 CLK_TOP_UNIVPLL_D3,
252 CLK_TOP_SYSPLL_D3,
253 CLK_TOP_UNIVPLL_D2_D2,
254 CLK_TOP_SYSPLL_D2_D2,
255 CLK_TOP_UNIVPLL_D3_D2,
256 CLK_TOP_SYSPLL_D3_D2
257 };
258
259 static const int dsp2_parents[] = {
260 CLK_TOP_CLK26M,
261 CLK_TOP_MMPLL_D6,
262 CLK_TOP_MMPLL_D7,
263 CLK_TOP_UNIVPLL_D3,
264 CLK_TOP_SYSPLL_D3,
265 CLK_TOP_UNIVPLL_D2_D2,
266 CLK_TOP_SYSPLL_D2_D2,
267 CLK_TOP_UNIVPLL_D3_D2,
268 CLK_TOP_SYSPLL_D3_D2
269 };
270
271 static const int ipu_if_parents[] = {
272 CLK_TOP_CLK26M,
273 CLK_TOP_MMPLL_D6,
274 CLK_TOP_MMPLL_D7,
275 CLK_TOP_UNIVPLL_D3,
276 CLK_TOP_SYSPLL_D3,
277 CLK_TOP_UNIVPLL_D2_D2,
278 CLK_TOP_SYSPLL_D2_D2,
279 CLK_TOP_UNIVPLL_D3_D2,
280 CLK_TOP_SYSPLL_D3_D2
281 };
282
283 static const int mfg_parents[] = {
284 CLK_TOP_CLK26M,
285 CLK_TOP_MFGPLL_CK,
286 CLK_TOP_UNIVPLL_D3,
287 CLK_TOP_SYSPLL_D3
288 };
289
290 static const int f52m_mfg_parents[] = {
291 CLK_TOP_CLK26M,
292 CLK_TOP_UNIVPLL_D3_D2,
293 CLK_TOP_UNIVPLL_D3_D4,
294 CLK_TOP_UNIVPLL_D3_D8
295 };
296
297 static const int camtg_parents[] = {
298 CLK_TOP_CLK26M,
299 CLK_TOP_UNIVP_192M_D8,
300 CLK_TOP_UNIVPLL_D3_D8,
301 CLK_TOP_UNIVP_192M_D4,
302 CLK_TOP_UNIVPLL_D3_D16,
303 CLK_TOP_F26M_CK_D2,
304 CLK_TOP_UNIVP_192M_D16,
305 CLK_TOP_UNIVP_192M_D32
306 };
307
308 static const int camtg2_parents[] = {
309 CLK_TOP_CLK26M,
310 CLK_TOP_UNIVP_192M_D8,
311 CLK_TOP_UNIVPLL_D3_D8,
312 CLK_TOP_UNIVP_192M_D4,
313 CLK_TOP_UNIVPLL_D3_D16,
314 CLK_TOP_F26M_CK_D2,
315 CLK_TOP_UNIVP_192M_D16,
316 CLK_TOP_UNIVP_192M_D32
317 };
318
319 static const int camtg3_parents[] = {
320 CLK_TOP_CLK26M,
321 CLK_TOP_UNIVP_192M_D8,
322 CLK_TOP_UNIVPLL_D3_D8,
323 CLK_TOP_UNIVP_192M_D4,
324 CLK_TOP_UNIVPLL_D3_D16,
325 CLK_TOP_F26M_CK_D2,
326 CLK_TOP_UNIVP_192M_D16,
327 CLK_TOP_UNIVP_192M_D32
328 };
329
330 static const int camtg4_parents[] = {
331 CLK_TOP_CLK26M,
332 CLK_TOP_UNIVP_192M_D8,
333 CLK_TOP_UNIVPLL_D3_D8,
334 CLK_TOP_UNIVP_192M_D4,
335 CLK_TOP_UNIVPLL_D3_D16,
336 CLK_TOP_F26M_CK_D2,
337 CLK_TOP_UNIVP_192M_D16,
338 CLK_TOP_UNIVP_192M_D32
339 };
340
341 static const int uart_parents[] = {
342 CLK_TOP_CLK26M,
343 CLK_TOP_UNIVPLL_D3_D8
344 };
345
346 static const int spi_parents[] = {
347 CLK_TOP_CLK26M,
348 CLK_TOP_SYSPLL_D5_D2,
349 CLK_TOP_SYSPLL_D3_D4,
350 CLK_TOP_MSDCPLL_D4
351 };
352
353 static const int msdc50_hclk_parents[] = {
354 CLK_TOP_CLK26M,
355 CLK_TOP_SYSPLL_D2_D2,
356 CLK_TOP_SYSPLL_D3_D2
357 };
358
359 static const int msdc50_0_parents[] = {
360 CLK_TOP_CLK26M,
361 CLK_TOP_MSDCPLL_CK,
362 CLK_TOP_MSDCPLL_D2,
363 CLK_TOP_UNIVPLL_D2_D4,
364 CLK_TOP_SYSPLL_D3_D2,
365 CLK_TOP_UNIVPLL_D2_D2
366 };
367
368 static const int msdc30_1_parents[] = {
369 CLK_TOP_CLK26M,
370 CLK_TOP_UNIVPLL_D3_D2,
371 CLK_TOP_SYSPLL_D3_D2,
372 CLK_TOP_SYSPLL_D7,
373 CLK_TOP_MSDCPLL_D2
374 };
375
376 static const int msdc30_2_parents[] = {
377 CLK_TOP_CLK26M,
378 CLK_TOP_UNIVPLL_D3_D2,
379 CLK_TOP_SYSPLL_D3_D2,
380 CLK_TOP_SYSPLL_D7,
381 CLK_TOP_MSDCPLL_D2
382 };
383
384 static const int audio_parents[] = {
385 CLK_TOP_CLK26M,
386 CLK_TOP_SYSPLL_D5_D4,
387 CLK_TOP_SYSPLL_D7_D4,
388 CLK_TOP_SYSPLL_D2_D16
389 };
390
391 static const int aud_intbus_parents[] = {
392 CLK_TOP_CLK26M,
393 CLK_TOP_SYSPLL_D2_D4,
394 CLK_TOP_SYSPLL_D7_D2
395 };
396
397 static const int pmicspi_parents[] = {
398 CLK_TOP_CLK26M,
399 CLK_TOP_SYSPLL_D2_D8,
400 CLK_TOP_OSC_D8
401 };
402
403 static const int fpwrap_ulposc_parents[] = {
404 CLK_TOP_CLK26M,
405 CLK_TOP_OSC_D16,
406 CLK_TOP_OSC_D4,
407 CLK_TOP_OSC_D8
408 };
409
410 static const int atb_parents[] = {
411 CLK_TOP_CLK26M,
412 CLK_TOP_SYSPLL_D2_D2,
413 CLK_TOP_SYSPLL_D5
414 };
415
416 static const int sspm_parents[] = {
417 CLK_TOP_CLK26M,
418 CLK_TOP_UNIVPLL_D2_D4,
419 CLK_TOP_SYSPLL_D2_D2,
420 CLK_TOP_UNIVPLL_D2_D2,
421 CLK_TOP_SYSPLL_D3
422 };
423
424 static const int dpi0_parents[] = {
425 CLK_TOP_CLK26M,
426 CLK_TOP_TVDPLL_D2,
427 CLK_TOP_TVDPLL_D4,
428 CLK_TOP_TVDPLL_D8,
429 CLK_TOP_TVDPLL_D16,
430 CLK_TOP_UNIVPLL_D5_D2,
431 CLK_TOP_UNIVPLL_D3_D4,
432 CLK_TOP_SYSPLL_D3_D4,
433 CLK_TOP_UNIVPLL_D3_D8
434 };
435
436 static const int scam_parents[] = {
437 CLK_TOP_CLK26M,
438 CLK_TOP_SYSPLL_D5_D2
439 };
440
441 static const int disppwm_parents[] = {
442 CLK_TOP_CLK26M,
443 CLK_TOP_UNIVPLL_D3_D4,
444 CLK_TOP_OSC_D2,
445 CLK_TOP_OSC_D4,
446 CLK_TOP_OSC_D16
447 };
448
449 static const int usb_top_parents[] = {
450 CLK_TOP_CLK26M,
451 CLK_TOP_UNIVPLL_D5_D4,
452 CLK_TOP_UNIVPLL_D3_D4,
453 CLK_TOP_UNIVPLL_D5_D2
454 };
455
456 static const int ssusb_top_xhci_parents[] = {
457 CLK_TOP_CLK26M,
458 CLK_TOP_UNIVPLL_D5_D4,
459 CLK_TOP_UNIVPLL_D3_D4,
460 CLK_TOP_UNIVPLL_D5_D2
461 };
462
463 static const int spm_parents[] = {
464 CLK_TOP_CLK26M,
465 CLK_TOP_SYSPLL_D2_D8
466 };
467
468 static const int i2c_parents[] = {
469 CLK_TOP_CLK26M,
470 CLK_TOP_SYSPLL_D2_D8,
471 CLK_TOP_UNIVPLL_D5_D2
472 };
473
474 static const int scp_parents[] = {
475 CLK_TOP_CLK26M,
476 CLK_TOP_UNIVPLL_D2_D8,
477 CLK_TOP_SYSPLL_D5,
478 CLK_TOP_SYSPLL_D2_D2,
479 CLK_TOP_UNIVPLL_D2_D2,
480 CLK_TOP_SYSPLL_D3,
481 CLK_TOP_UNIVPLL_D3
482 };
483
484 static const int seninf_parents[] = {
485 CLK_TOP_CLK26M,
486 CLK_TOP_UNIVPLL_D2_D2,
487 CLK_TOP_UNIVPLL_D3_D2,
488 CLK_TOP_UNIVPLL_D2_D4
489 };
490
491 static const int dxcc_parents[] = {
492 CLK_TOP_CLK26M,
493 CLK_TOP_SYSPLL_D2_D2,
494 CLK_TOP_SYSPLL_D2_D4,
495 CLK_TOP_SYSPLL_D2_D8
496 };
497
498 static const int aud_engen1_parents[] = {
499 CLK_TOP_CLK26M,
500 CLK_TOP_APLL1_D2,
501 CLK_TOP_APLL1_D4,
502 CLK_TOP_APLL1_D8
503 };
504
505 static const int aud_engen2_parents[] = {
506 CLK_TOP_CLK26M,
507 CLK_TOP_APLL2_D2,
508 CLK_TOP_APLL2_D4,
509 CLK_TOP_APLL2_D8
510 };
511
512 static const int faes_ufsfde_parents[] = {
513 CLK_TOP_CLK26M,
514 CLK_TOP_SYSPLL_D2,
515 CLK_TOP_SYSPLL_D2_D2,
516 CLK_TOP_SYSPLL_D3,
517 CLK_TOP_SYSPLL_D2_D4,
518 CLK_TOP_UNIVPLL_D3
519 };
520
521 static const int fufs_parents[] = {
522 CLK_TOP_CLK26M,
523 CLK_TOP_SYSPLL_D2_D4,
524 CLK_TOP_SYSPLL_D2_D8,
525 CLK_TOP_SYSPLL_D2_D16
526 };
527
528 static const int aud_1_parents[] = {
529 CLK_TOP_CLK26M,
530 CLK_TOP_APLL1_CK
531 };
532
533 static const int aud_2_parents[] = {
534 CLK_TOP_CLK26M,
535 CLK_TOP_APLL2_CK
536 };
537
538 static const struct mtk_composite top_muxes[] = {
539 /* CLK_CFG_0 */
540 MUX(CLK_TOP_MUX_AXI, axi_parents, 0x40, 0, 2),
541 MUX(CLK_TOP_MUX_MM, mm_parents, 0x40, 8, 3),
542 MUX(CLK_TOP_MUX_IMG, img_parents, 0x40, 16, 3),
543 MUX(CLK_TOP_MUX_CAM, cam_parents, 0x40, 24, 4),
544 /* CLK_CFG_1 */
545 MUX(CLK_TOP_MUX_DSP, dsp_parents, 0x50, 0, 4),
546 MUX(CLK_TOP_MUX_DSP1, dsp1_parents, 0x50, 8, 4),
547 MUX(CLK_TOP_MUX_DSP2, dsp2_parents, 0x50, 16, 4),
548 MUX(CLK_TOP_MUX_IPU_IF, ipu_if_parents, 0x50, 24, 4),
549 /* CLK_CFG_2 */
550 MUX(CLK_TOP_MUX_MFG, mfg_parents, 0x60, 0, 2),
551 MUX(CLK_TOP_MUX_F52M_MFG, f52m_mfg_parents, 0x60, 8, 2),
552 MUX(CLK_TOP_MUX_CAMTG, camtg_parents, 0x60, 16, 3),
553 MUX(CLK_TOP_MUX_CAMTG2, camtg2_parents, 0x60, 24, 3),
554 /* CLK_CFG_3 */
555 MUX(CLK_TOP_MUX_CAMTG3, camtg3_parents, 0x70, 0, 3),
556 MUX(CLK_TOP_MUX_CAMTG4, camtg4_parents, 0x70, 8, 3),
557 MUX(CLK_TOP_MUX_UART, uart_parents, 0x70, 16, 1),
558 MUX(CLK_TOP_MUX_SPI, spi_parents, 0x70, 24, 2),
559 /* CLK_CFG_4 */
560 MUX(CLK_TOP_MUX_MSDC50_0_HCLK, msdc50_hclk_parents, 0x80, 0, 2),
561 MUX(CLK_TOP_MUX_MSDC50_0, msdc50_0_parents, 0x80, 8, 3),
562 MUX(CLK_TOP_MUX_MSDC30_1, msdc30_1_parents, 0x80, 16, 3),
563 MUX(CLK_TOP_MUX_MSDC30_2, msdc30_2_parents, 0x80, 24, 3),
564 /* CLK_CFG_5 */
565 MUX(CLK_TOP_MUX_AUDIO, audio_parents, 0x90, 0, 2),
566 MUX(CLK_TOP_MUX_AUD_INTBUS, aud_intbus_parents, 0x90, 8, 2),
567 MUX(CLK_TOP_MUX_PMICSPI, pmicspi_parents, 0x90, 16, 2),
568 MUX(CLK_TOP_MUX_FPWRAP_ULPOSC, fpwrap_ulposc_parents, 0x90, 24, 2),
569 /* CLK_CFG_6 */
570 MUX(CLK_TOP_MUX_ATB, atb_parents, 0xa0, 0, 2),
571 MUX(CLK_TOP_MUX_SSPM, sspm_parents, 0xa0, 8, 3),
572 MUX(CLK_TOP_MUX_DPI0, dpi0_parents, 0xa0, 16, 4),
573 MUX(CLK_TOP_MUX_SCAM, scam_parents, 0xa0, 24, 1),
574 /* CLK_CFG_7 */
575 MUX(CLK_TOP_MUX_DISP_PWM, disppwm_parents, 0xb0, 0, 3),
576 MUX(CLK_TOP_MUX_USB_TOP, usb_top_parents, 0xb0, 8, 2),
577 MUX(CLK_TOP_MUX_SSUSB_TOP_XHCI, ssusb_top_xhci_parents, 0xb0, 16, 2),
578 MUX(CLK_TOP_MUX_SPM, spm_parents, 0xb0, 24, 1),
579 /* CLK_CFG_8 */
580 MUX(CLK_TOP_MUX_I2C, i2c_parents, 0xc0, 0, 2),
581 MUX(CLK_TOP_MUX_SCP, scp_parents, 0xc0, 8, 3),
582 MUX(CLK_TOP_MUX_SENINF, seninf_parents, 0xc0, 16, 2),
583 MUX(CLK_TOP_MUX_DXCC, dxcc_parents, 0xc0, 24, 2),
584 /* CLK_CFG_9 */
585 MUX(CLK_TOP_MUX_AUD_ENG1, aud_engen1_parents, 0xd0, 0, 2),
586 MUX(CLK_TOP_MUX_AUD_ENG2, aud_engen2_parents, 0xd0, 8, 2),
587 MUX(CLK_TOP_MUX_FAES_UFSFDE, faes_ufsfde_parents, 0xd0, 16, 3),
588 MUX(CLK_TOP_MUX_FUFS, fufs_parents, 0xd0, 24, 2),
589 /* CLK_CFG_10 */
590 MUX(CLK_TOP_MUX_AUD_1, aud_1_parents, 0xe0, 0, 1),
591 MUX(CLK_TOP_MUX_AUD_2, aud_2_parents, 0xe0, 8, 1),
592 };
593
594 static const struct mtk_clk_tree mt8183_clk_tree = {
595 .xtal_rate = 26 * MHZ,
596 .xtal2_rate = 26 * MHZ,
597 .fdivs_offs = CLK_TOP_CLK13M,
598 .muxes_offs = CLK_TOP_MUX_AXI,
599 .plls = apmixed_plls,
600 .fclks = top_fixed_clks,
601 .fdivs = top_fixed_divs,
602 .muxes = top_muxes,
603 };
604
605 static const struct mtk_gate_regs infra0_cg_regs = {
606 .set_ofs = 0x80,
607 .clr_ofs = 0x84,
608 .sta_ofs = 0x90,
609 };
610
611 static const struct mtk_gate_regs infra1_cg_regs = {
612 .set_ofs = 0x88,
613 .clr_ofs = 0x8c,
614 .sta_ofs = 0x94,
615 };
616
617 static const struct mtk_gate_regs infra2_cg_regs = {
618 .set_ofs = 0xa4,
619 .clr_ofs = 0xa8,
620 .sta_ofs = 0xac,
621 };
622
623 static const struct mtk_gate_regs infra3_cg_regs = {
624 .set_ofs = 0xc0,
625 .clr_ofs = 0xc4,
626 .sta_ofs = 0xc8,
627 };
628
629 #define GATE_INFRA0(_id, _parent, _shift) { \
630 .id = _id, \
631 .parent = _parent, \
632 .regs = &infra0_cg_regs, \
633 .shift = _shift, \
634 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
635 }
636
637 #define GATE_INFRA1(_id, _parent, _shift) { \
638 .id = _id, \
639 .parent = _parent, \
640 .regs = &infra1_cg_regs, \
641 .shift = _shift, \
642 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
643 }
644
645 #define GATE_INFRA2(_id, _parent, _shift) { \
646 .id = _id, \
647 .parent = _parent, \
648 .regs = &infra2_cg_regs, \
649 .shift = _shift, \
650 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
651 }
652
653 #define GATE_INFRA3(_id, _parent, _shift) { \
654 .id = _id, \
655 .parent = _parent, \
656 .regs = &infra3_cg_regs, \
657 .shift = _shift, \
658 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
659 }
660
661 static const struct mtk_gate infra_clks[] = {
662 /* INFRA0 */
663 GATE_INFRA0(CLK_INFRA_PMIC_TMR, CLK_TOP_MUX_AXI, 0),
664 GATE_INFRA0(CLK_INFRA_PMIC_AP, CLK_TOP_MUX_AXI, 1),
665 GATE_INFRA0(CLK_INFRA_PMIC_MD, CLK_TOP_MUX_AXI, 2),
666 GATE_INFRA0(CLK_INFRA_PMIC_CONN, CLK_TOP_MUX_AXI, 3),
667 GATE_INFRA0(CLK_INFRA_SCPSYS, CLK_TOP_MUX_SCP, 4),
668 GATE_INFRA0(CLK_INFRA_SEJ, CLK_TOP_CLK26M, 5),
669 GATE_INFRA0(CLK_INFRA_APXGPT, CLK_TOP_MUX_AXI, 6),
670 GATE_INFRA0(CLK_INFRA_ICUSB, CLK_TOP_MUX_AXI, 8),
671 GATE_INFRA0(CLK_INFRA_GCE, CLK_TOP_MUX_AXI, 9),
672 GATE_INFRA0(CLK_INFRA_THERM, CLK_TOP_MUX_AXI, 10),
673 GATE_INFRA0(CLK_INFRA_I2C0, CLK_TOP_MUX_I2C, 11),
674 GATE_INFRA0(CLK_INFRA_I2C1, CLK_TOP_MUX_I2C, 12),
675 GATE_INFRA0(CLK_INFRA_I2C2, CLK_TOP_MUX_I2C, 13),
676 GATE_INFRA0(CLK_INFRA_I2C3, CLK_TOP_MUX_I2C, 14),
677 GATE_INFRA0(CLK_INFRA_PWM_HCLK, CLK_TOP_MUX_AXI, 15),
678 GATE_INFRA0(CLK_INFRA_PWM1, CLK_TOP_MUX_I2C, 16),
679 GATE_INFRA0(CLK_INFRA_PWM2, CLK_TOP_MUX_I2C, 17),
680 GATE_INFRA0(CLK_INFRA_PWM3, CLK_TOP_MUX_I2C, 18),
681 GATE_INFRA0(CLK_INFRA_PWM4, CLK_TOP_MUX_I2C, 19),
682 GATE_INFRA0(CLK_INFRA_PWM, CLK_TOP_MUX_I2C, 21),
683 GATE_INFRA0(CLK_INFRA_UART0, CLK_TOP_MUX_UART, 22),
684 GATE_INFRA0(CLK_INFRA_UART1, CLK_TOP_MUX_UART, 23),
685 GATE_INFRA0(CLK_INFRA_UART2, CLK_TOP_MUX_UART, 24),
686 GATE_INFRA0(CLK_INFRA_UART3, CLK_TOP_MUX_UART, 25),
687 GATE_INFRA0(CLK_INFRA_GCE_26M, CLK_TOP_MUX_AXI, 27),
688 GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, CLK_TOP_MUX_AXI, 28),
689 GATE_INFRA0(CLK_INFRA_BTIF, CLK_TOP_MUX_AXI, 31),
690 /* INFRA1 */
691 GATE_INFRA1(CLK_INFRA_SPI0, CLK_TOP_MUX_SPI, 1),
692 GATE_INFRA1(CLK_INFRA_MSDC0, CLK_TOP_MUX_MSDC50_0_HCLK, 2),
693 GATE_INFRA1(CLK_INFRA_MSDC1, CLK_TOP_MUX_AXI, 4),
694 GATE_INFRA1(CLK_INFRA_MSDC2, CLK_TOP_MUX_AXI, 5),
695 GATE_INFRA1(CLK_INFRA_MSDC0_SCK, CLK_TOP_MUX_MSDC50_0, 6),
696 GATE_INFRA1(CLK_INFRA_DVFSRC, CLK_TOP_CLK26M, 7),
697 GATE_INFRA1(CLK_INFRA_GCPU, CLK_TOP_MUX_AXI, 8),
698 GATE_INFRA1(CLK_INFRA_TRNG, CLK_TOP_MUX_AXI, 9),
699 GATE_INFRA1(CLK_INFRA_AUXADC, CLK_TOP_CLK26M, 10),
700 GATE_INFRA1(CLK_INFRA_CPUM, CLK_TOP_MUX_AXI, 11),
701 GATE_INFRA1(CLK_INFRA_CCIF1_AP, CLK_TOP_MUX_AXI, 12),
702 GATE_INFRA1(CLK_INFRA_CCIF1_MD, CLK_TOP_MUX_AXI, 13),
703 GATE_INFRA1(CLK_INFRA_AUXADC_MD, CLK_TOP_CLK26M, 14),
704 GATE_INFRA1(CLK_INFRA_MSDC1_SCK, CLK_TOP_MUX_MSDC30_1, 16),
705 GATE_INFRA1(CLK_INFRA_MSDC2_SCK, CLK_TOP_MUX_MSDC30_2, 17),
706 GATE_INFRA1(CLK_INFRA_AP_DMA, CLK_TOP_MUX_AXI, 18),
707 GATE_INFRA1(CLK_INFRA_XIU, CLK_TOP_MUX_AXI, 19),
708 GATE_INFRA1(CLK_INFRA_DEVICE_APC, CLK_TOP_MUX_AXI, 20),
709 GATE_INFRA1(CLK_INFRA_CCIF_AP, CLK_TOP_MUX_AXI, 23),
710 GATE_INFRA1(CLK_INFRA_DEBUGSYS, CLK_TOP_MUX_AXI, 24),
711 GATE_INFRA1(CLK_INFRA_AUDIO, CLK_TOP_MUX_AXI, 25),
712 GATE_INFRA1(CLK_INFRA_CCIF_MD, CLK_TOP_MUX_AXI, 26),
713 GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, CLK_TOP_MUX_DXCC, 27),
714 GATE_INFRA1(CLK_INFRA_DXCC_AO, CLK_TOP_MUX_DXCC, 28),
715 GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, CLK_TOP_MUX_AXI, 30),
716 GATE_INFRA1(CLK_INFRA_DRAMC_F26M, CLK_TOP_CLK26M, 31),
717 /* INFRA2 */
718 GATE_INFRA2(CLK_INFRA_IRTX, CLK_TOP_CLK26M, 0),
719 GATE_INFRA2(CLK_INFRA_USB, CLK_TOP_MUX_USB_TOP, 1),
720 GATE_INFRA2(CLK_INFRA_DISP_PWM, CLK_TOP_MUX_AXI, 2),
721 GATE_INFRA2(CLK_INFRA_CLDMA_BCLK, CLK_TOP_MUX_AXI, 3),
722 GATE_INFRA2(CLK_INFRA_AUDIO_26M_BCLK, CLK_TOP_CLK26M, 4),
723 GATE_INFRA2(CLK_INFRA_SPI1, CLK_TOP_MUX_SPI, 6),
724 GATE_INFRA2(CLK_INFRA_I2C4, CLK_TOP_MUX_I2C, 7),
725 GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, CLK_TOP_CLK26M, 8),
726 GATE_INFRA2(CLK_INFRA_SPI2, CLK_TOP_MUX_SPI, 9),
727 GATE_INFRA2(CLK_INFRA_SPI3, CLK_TOP_MUX_SPI, 10),
728 GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, CLK_TOP_MUX_SSUSB_TOP_XHCI, 11),
729 GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, CLK_TOP_MUX_FUFS, 12),
730 GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, CLK_TOP_MUX_FUFS, 13),
731 GATE_INFRA2(CLK_INFRA_MD32_BCLK, CLK_TOP_MUX_AXI, 14),
732 GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, CLK_TOP_MUX_AXI, 16),
733 GATE_INFRA2(CLK_INFRA_I2C5, CLK_TOP_MUX_I2C, 18),
734 GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, CLK_TOP_MUX_I2C, 19),
735 GATE_INFRA2(CLK_INFRA_I2C5_IMM, CLK_TOP_MUX_I2C, 20),
736 GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, CLK_TOP_MUX_I2C, 21),
737 GATE_INFRA2(CLK_INFRA_I2C1_IMM, CLK_TOP_MUX_I2C, 22),
738 GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, CLK_TOP_MUX_I2C, 23),
739 GATE_INFRA2(CLK_INFRA_I2C2_IMM, CLK_TOP_MUX_I2C, 24),
740 GATE_INFRA2(CLK_INFRA_SPI4, CLK_TOP_MUX_SPI, 25),
741 GATE_INFRA2(CLK_INFRA_SPI5, CLK_TOP_MUX_SPI, 26),
742 GATE_INFRA2(CLK_INFRA_CQ_DMA, CLK_TOP_MUX_AXI, 27),
743 GATE_INFRA2(CLK_INFRA_UFS, CLK_TOP_MUX_FUFS, 28),
744 GATE_INFRA2(CLK_INFRA_AES_UFSFDE, CLK_TOP_MUX_FAES_UFSFDE, 29),
745 GATE_INFRA2(CLK_INFRA_UFS_TICK, CLK_TOP_MUX_FUFS, 30),
746 /* INFRA3 */
747 GATE_INFRA3(CLK_INFRA_MSDC0_SELF, CLK_TOP_MUX_MSDC50_0, 0),
748 GATE_INFRA3(CLK_INFRA_MSDC1_SELF, CLK_TOP_MUX_MSDC50_0, 1),
749 GATE_INFRA3(CLK_INFRA_MSDC2_SELF, CLK_TOP_MUX_MSDC50_0, 2),
750 GATE_INFRA3(CLK_INFRA_UFS_AXI, CLK_TOP_MUX_AXI, 5),
751 GATE_INFRA3(CLK_INFRA_I2C6, CLK_TOP_MUX_I2C, 6),
752 GATE_INFRA3(CLK_INFRA_AP_MSDC0, CLK_TOP_MUX_MSDC50_0_HCLK, 7),
753 GATE_INFRA3(CLK_INFRA_MD_MSDC0, CLK_TOP_MUX_MSDC50_0_HCLK, 8),
754 GATE_INFRA3(CLK_INFRA_CCIF2_AP, CLK_TOP_MUX_AXI, 16),
755 GATE_INFRA3(CLK_INFRA_CCIF2_MD, CLK_TOP_MUX_AXI, 17),
756 GATE_INFRA3(CLK_INFRA_CCIF3_AP, CLK_TOP_MUX_AXI, 18),
757 GATE_INFRA3(CLK_INFRA_CCIF3_MD, CLK_TOP_MUX_AXI, 19),
758 GATE_INFRA3(CLK_INFRA_SEJ_F13M, CLK_TOP_CLK26M, 20),
759 GATE_INFRA3(CLK_INFRA_AES_BCLK, CLK_TOP_MUX_AXI, 21),
760 GATE_INFRA3(CLK_INFRA_I2C7, CLK_TOP_MUX_I2C, 22),
761 GATE_INFRA3(CLK_INFRA_I2C8, CLK_TOP_MUX_I2C, 23),
762 GATE_INFRA3(CLK_INFRA_FBIST2FPC, CLK_TOP_MUX_MSDC50_0, 24),
763 };
764
mt8183_apmixedsys_probe(struct udevice * dev)765 static int mt8183_apmixedsys_probe(struct udevice *dev)
766 {
767 return mtk_common_clk_init(dev, &mt8183_clk_tree);
768 }
769
mt8183_topckgen_probe(struct udevice * dev)770 static int mt8183_topckgen_probe(struct udevice *dev)
771 {
772 return mtk_common_clk_init(dev, &mt8183_clk_tree);
773 }
774
mt8183_infracfg_probe(struct udevice * dev)775 static int mt8183_infracfg_probe(struct udevice *dev)
776 {
777 return mtk_common_clk_gate_init(dev, &mt8183_clk_tree, infra_clks);
778 }
779
780 static const struct udevice_id mt8183_apmixed_compat[] = {
781 { .compatible = "mediatek,mt8183-apmixedsys", },
782 { }
783 };
784
785 static const struct udevice_id mt8183_topckgen_compat[] = {
786 { .compatible = "mediatek,mt8183-topckgen", },
787 { }
788 };
789
790 static const struct udevice_id mt8183_infracfg_compat[] = {
791 { .compatible = "mediatek,mt8183-infracfg", },
792 { }
793 };
794
795 U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
796 .name = "mt8183-apmixedsys",
797 .id = UCLASS_CLK,
798 .of_match = mt8183_apmixed_compat,
799 .probe = mt8183_apmixedsys_probe,
800 .priv_auto = sizeof(struct mtk_clk_priv),
801 .ops = &mtk_clk_apmixedsys_ops,
802 .flags = DM_FLAG_PRE_RELOC,
803 };
804
805 U_BOOT_DRIVER(mtk_clk_topckgen) = {
806 .name = "mt8183-topckgen",
807 .id = UCLASS_CLK,
808 .of_match = mt8183_topckgen_compat,
809 .probe = mt8183_topckgen_probe,
810 .priv_auto = sizeof(struct mtk_clk_priv),
811 .ops = &mtk_clk_topckgen_ops,
812 .flags = DM_FLAG_PRE_RELOC,
813 };
814
815 U_BOOT_DRIVER(mtk_clk_infracfg) = {
816 .name = "mt8183-infracfg",
817 .id = UCLASS_CLK,
818 .of_match = mt8183_infracfg_compat,
819 .probe = mt8183_infracfg_probe,
820 .priv_auto = sizeof(struct mtk_clk_priv),
821 .ops = &mtk_clk_gate_ops,
822 .flags = DM_FLAG_PRE_RELOC,
823 };
824