1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Texas Instruments AM35x "glue layer"
4 *
5 * Copyright (c) 2010, by Texas Instruments
6 *
7 * Based on the DA8xx "glue layer" code.
8 * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
9 *
10 * This file is part of the Inventra Controller Driver for Linux.
11 *
12 */
13
14 #ifndef __UBOOT__
15 #include <dm/device_compat.h>
16 #include <dm/devres.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/io.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma-mapping.h>
24
25 #include <plat/usb.h>
26 #else
27 #include <common.h>
28 #include <asm/omap_musb.h>
29 #include <linux/bug.h>
30 #include <linux/delay.h>
31 #include "linux-compat.h"
32 #endif
33
34 #include "musb_core.h"
35
36 /*
37 * AM35x specific definitions
38 */
39 /* USB 2.0 OTG module registers */
40 #define USB_REVISION_REG 0x00
41 #define USB_CTRL_REG 0x04
42 #define USB_STAT_REG 0x08
43 #define USB_EMULATION_REG 0x0c
44 /* 0x10 Reserved */
45 #define USB_AUTOREQ_REG 0x14
46 #define USB_SRP_FIX_TIME_REG 0x18
47 #define USB_TEARDOWN_REG 0x1c
48 #define EP_INTR_SRC_REG 0x20
49 #define EP_INTR_SRC_SET_REG 0x24
50 #define EP_INTR_SRC_CLEAR_REG 0x28
51 #define EP_INTR_MASK_REG 0x2c
52 #define EP_INTR_MASK_SET_REG 0x30
53 #define EP_INTR_MASK_CLEAR_REG 0x34
54 #define EP_INTR_SRC_MASKED_REG 0x38
55 #define CORE_INTR_SRC_REG 0x40
56 #define CORE_INTR_SRC_SET_REG 0x44
57 #define CORE_INTR_SRC_CLEAR_REG 0x48
58 #define CORE_INTR_MASK_REG 0x4c
59 #define CORE_INTR_MASK_SET_REG 0x50
60 #define CORE_INTR_MASK_CLEAR_REG 0x54
61 #define CORE_INTR_SRC_MASKED_REG 0x58
62 /* 0x5c Reserved */
63 #define USB_END_OF_INTR_REG 0x60
64
65 /* Control register bits */
66 #define AM35X_SOFT_RESET_MASK 1
67
68 /* USB interrupt register bits */
69 #define AM35X_INTR_USB_SHIFT 16
70 #define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT)
71 #define AM35X_INTR_DRVVBUS 0x100
72 #define AM35X_INTR_RX_SHIFT 16
73 #define AM35X_INTR_TX_SHIFT 0
74 #define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */
75 #define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */
76 #define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
77 #define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
78
79 #define USB_MENTOR_CORE_OFFSET 0x400
80
81 struct am35x_glue {
82 struct device *dev;
83 struct platform_device *musb;
84 struct clk *phy_clk;
85 struct clk *clk;
86 };
87 #define glue_to_musb(g) platform_get_drvdata(g->musb)
88
89 /*
90 * am35x_musb_enable - enable interrupts
91 */
92 #ifndef __UBOOT__
am35x_musb_enable(struct musb * musb)93 static void am35x_musb_enable(struct musb *musb)
94 #else
95 static int am35x_musb_enable(struct musb *musb)
96 #endif
97 {
98 void __iomem *reg_base = musb->ctrl_base;
99 u32 epmask;
100
101 /* Workaround: setup IRQs through both register sets. */
102 epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
103 ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
104
105 musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
106 musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
107
108 /* Force the DRVVBUS IRQ so we can start polling for ID change. */
109 if (is_otg_enabled(musb))
110 musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
111 AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
112 #ifdef __UBOOT__
113 return 0;
114 #endif
115 }
116
117 /*
118 * am35x_musb_disable - disable HDRC and flush interrupts
119 */
am35x_musb_disable(struct musb * musb)120 static void am35x_musb_disable(struct musb *musb)
121 {
122 void __iomem *reg_base = musb->ctrl_base;
123
124 musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
125 musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
126 AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
127 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
128 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
129 }
130
131 #ifndef __UBOOT__
132 #define portstate(stmt) stmt
133
am35x_musb_set_vbus(struct musb * musb,int is_on)134 static void am35x_musb_set_vbus(struct musb *musb, int is_on)
135 {
136 WARN_ON(is_on && is_peripheral_active(musb));
137 }
138
139 #define POLL_SECONDS 2
140
141 static struct timer_list otg_workaround;
142
otg_timer(unsigned long _musb)143 static void otg_timer(unsigned long _musb)
144 {
145 struct musb *musb = (void *)_musb;
146 void __iomem *mregs = musb->mregs;
147 u8 devctl;
148 unsigned long flags;
149
150 /*
151 * We poll because AM35x's won't expose several OTG-critical
152 * status change events (from the transceiver) otherwise.
153 */
154 devctl = musb_readb(mregs, MUSB_DEVCTL);
155 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
156 otg_state_string(musb->xceiv->state));
157
158 spin_lock_irqsave(&musb->lock, flags);
159 switch (musb->xceiv->state) {
160 case OTG_STATE_A_WAIT_BCON:
161 devctl &= ~MUSB_DEVCTL_SESSION;
162 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
163
164 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
165 if (devctl & MUSB_DEVCTL_BDEVICE) {
166 musb->xceiv->state = OTG_STATE_B_IDLE;
167 MUSB_DEV_MODE(musb);
168 } else {
169 musb->xceiv->state = OTG_STATE_A_IDLE;
170 MUSB_HST_MODE(musb);
171 }
172 break;
173 case OTG_STATE_A_WAIT_VFALL:
174 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
175 musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
176 MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
177 break;
178 case OTG_STATE_B_IDLE:
179 if (!is_peripheral_enabled(musb))
180 break;
181
182 devctl = musb_readb(mregs, MUSB_DEVCTL);
183 if (devctl & MUSB_DEVCTL_BDEVICE)
184 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
185 else
186 musb->xceiv->state = OTG_STATE_A_IDLE;
187 break;
188 default:
189 break;
190 }
191 spin_unlock_irqrestore(&musb->lock, flags);
192 }
193
am35x_musb_try_idle(struct musb * musb,unsigned long timeout)194 static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
195 {
196 static unsigned long last_timer;
197
198 if (!is_otg_enabled(musb))
199 return;
200
201 if (timeout == 0)
202 timeout = jiffies + msecs_to_jiffies(3);
203
204 /* Never idle if active, or when VBUS timeout is not set as host */
205 if (musb->is_active || (musb->a_wait_bcon == 0 &&
206 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
207 dev_dbg(musb->controller, "%s active, deleting timer\n",
208 otg_state_string(musb->xceiv->state));
209 del_timer(&otg_workaround);
210 last_timer = jiffies;
211 return;
212 }
213
214 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
215 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
216 return;
217 }
218 last_timer = timeout;
219
220 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
221 otg_state_string(musb->xceiv->state),
222 jiffies_to_msecs(timeout - jiffies));
223 mod_timer(&otg_workaround, timeout);
224 }
225 #endif
226
am35x_musb_interrupt(int irq,void * hci)227 static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
228 {
229 struct musb *musb = hci;
230 void __iomem *reg_base = musb->ctrl_base;
231 #ifndef __UBOOT__
232 struct device *dev = musb->controller;
233 struct musb_hdrc_platform_data *plat = dev->platform_data;
234 struct omap_musb_board_data *data = plat->board_data;
235 struct usb_otg *otg = musb->xceiv->otg;
236 #else
237 struct omap_musb_board_data *data =
238 (struct omap_musb_board_data *)musb->controller;
239 #endif
240 unsigned long flags;
241 irqreturn_t ret = IRQ_NONE;
242 u32 epintr, usbintr;
243
244 #ifdef __UBOOT__
245 /*
246 * It seems that on AM35X interrupt registers can be updated
247 * before core registers. This confuses the code.
248 * As a workaround add a small delay here.
249 */
250 udelay(10);
251 #endif
252 spin_lock_irqsave(&musb->lock, flags);
253
254 /* Get endpoint interrupts */
255 epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
256
257 if (epintr) {
258 musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
259
260 musb->int_rx =
261 (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
262 musb->int_tx =
263 (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
264 }
265
266 /* Get usb core interrupts */
267 usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
268 if (!usbintr && !epintr)
269 goto eoi;
270
271 if (usbintr) {
272 musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
273
274 musb->int_usb =
275 (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
276 }
277 #ifndef __UBOOT__
278 /*
279 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
280 * AM35x's missing ID change IRQ. We need an ID change IRQ to
281 * switch appropriately between halves of the OTG state machine.
282 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
283 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
284 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
285 */
286 if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
287 int drvvbus = musb_readl(reg_base, USB_STAT_REG);
288 void __iomem *mregs = musb->mregs;
289 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
290 int err;
291
292 err = is_host_enabled(musb) && (musb->int_usb &
293 MUSB_INTR_VBUSERROR);
294 if (err) {
295 /*
296 * The Mentor core doesn't debounce VBUS as needed
297 * to cope with device connect current spikes. This
298 * means it's not uncommon for bus-powered devices
299 * to get VBUS errors during enumeration.
300 *
301 * This is a workaround, but newer RTL from Mentor
302 * seems to allow a better one: "re"-starting sessions
303 * without waiting for VBUS to stop registering in
304 * devctl.
305 */
306 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
307 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
308 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
309 WARNING("VBUS error workaround (delay coming)\n");
310 } else if (is_host_enabled(musb) && drvvbus) {
311 MUSB_HST_MODE(musb);
312 otg->default_a = 1;
313 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
314 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
315 del_timer(&otg_workaround);
316 } else {
317 musb->is_active = 0;
318 MUSB_DEV_MODE(musb);
319 otg->default_a = 0;
320 musb->xceiv->state = OTG_STATE_B_IDLE;
321 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
322 }
323
324 /* NOTE: this must complete power-on within 100 ms. */
325 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
326 drvvbus ? "on" : "off",
327 otg_state_string(musb->xceiv->state),
328 err ? " ERROR" : "",
329 devctl);
330 ret = IRQ_HANDLED;
331 }
332 #endif
333
334 if (musb->int_tx || musb->int_rx || musb->int_usb)
335 ret |= musb_interrupt(musb);
336
337 eoi:
338 /* EOI needs to be written for the IRQ to be re-asserted. */
339 if (ret == IRQ_HANDLED || epintr || usbintr) {
340 /* clear level interrupt */
341 if (data->clear_irq)
342 data->clear_irq(data->dev);
343 /* write EOI */
344 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
345 }
346
347 #ifndef __UBOOT__
348 /* Poll for ID change */
349 if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
350 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
351 #endif
352
353 spin_unlock_irqrestore(&musb->lock, flags);
354
355 return ret;
356 }
357
358 #ifndef __UBOOT__
am35x_musb_set_mode(struct musb * musb,u8 musb_mode)359 static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
360 {
361 struct device *dev = musb->controller;
362 struct musb_hdrc_platform_data *plat = dev->platform_data;
363 struct omap_musb_board_data *data = plat->board_data;
364 int retval = 0;
365
366 if (data->set_mode)
367 data->set_mode(musb_mode);
368 else
369 retval = -EIO;
370
371 return retval;
372 }
373 #endif
374
am35x_musb_init(struct musb * musb)375 static int am35x_musb_init(struct musb *musb)
376 {
377 #ifndef __UBOOT__
378 struct device *dev = musb->controller;
379 struct musb_hdrc_platform_data *plat = dev->platform_data;
380 struct omap_musb_board_data *data = plat->board_data;
381 #else
382 struct omap_musb_board_data *data =
383 (struct omap_musb_board_data *)musb->controller;
384 #endif
385 void __iomem *reg_base = musb->ctrl_base;
386 u32 rev;
387
388 musb->mregs += USB_MENTOR_CORE_OFFSET;
389
390 /* Returns zero if e.g. not clocked */
391 rev = musb_readl(reg_base, USB_REVISION_REG);
392 if (!rev)
393 return -ENODEV;
394
395 #ifndef __UBOOT__
396 usb_nop_xceiv_register();
397 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
398 if (IS_ERR_OR_NULL(musb->xceiv))
399 return -ENODEV;
400
401 if (is_host_enabled(musb))
402 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
403 #endif
404
405 /* Reset the musb */
406 if (data->reset)
407 data->reset(data->dev);
408
409 /* Reset the controller */
410 musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
411
412 /* Start the on-chip PHY and its PLL. */
413 if (data && data->set_phy_power)
414 data->set_phy_power(data->dev, 1);
415
416 msleep(5);
417
418 musb->isr = am35x_musb_interrupt;
419
420 /* clear level interrupt */
421 if (data->clear_irq)
422 data->clear_irq(data->dev);
423
424 return 0;
425 }
426
am35x_musb_exit(struct musb * musb)427 static int am35x_musb_exit(struct musb *musb)
428 {
429 #ifndef __UBOOT__
430 struct device *dev = musb->controller;
431 struct musb_hdrc_platform_data *plat = dev->platform_data;
432 struct omap_musb_board_data *data = plat->board_data;
433 #else
434 struct omap_musb_board_data *data =
435 (struct omap_musb_board_data *)musb->controller;
436 #endif
437
438 #ifndef __UBOOT__
439 if (is_host_enabled(musb))
440 del_timer_sync(&otg_workaround);
441 #endif
442
443 /* Shutdown the on-chip PHY and its PLL. */
444 if (data && data->set_phy_power)
445 data->set_phy_power(data->dev, 0);
446
447 #ifndef __UBOOT__
448 usb_put_phy(musb->xceiv);
449 usb_nop_xceiv_unregister();
450 #endif
451
452 return 0;
453 }
454
455 /* AM35x supports only 32bit read operation */
musb_read_fifo(struct musb_hw_ep * hw_ep,u16 len,u8 * dst)456 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
457 {
458 void __iomem *fifo = hw_ep->fifo;
459 u32 val;
460 int i;
461
462 /* Read for 32bit-aligned destination address */
463 if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
464 readsl(fifo, dst, len >> 2);
465 dst += len & ~0x03;
466 len &= 0x03;
467 }
468 /*
469 * Now read the remaining 1 to 3 byte or complete length if
470 * unaligned address.
471 */
472 if (len > 4) {
473 for (i = 0; i < (len >> 2); i++) {
474 *(u32 *) dst = musb_readl(fifo, 0);
475 dst += 4;
476 }
477 len &= 0x03;
478 }
479 if (len > 0) {
480 val = musb_readl(fifo, 0);
481 memcpy(dst, &val, len);
482 }
483 }
484
485 #ifndef __UBOOT__
486 static const struct musb_platform_ops am35x_ops = {
487 #else
488 const struct musb_platform_ops am35x_ops = {
489 #endif
490 .init = am35x_musb_init,
491 .exit = am35x_musb_exit,
492
493 .enable = am35x_musb_enable,
494 .disable = am35x_musb_disable,
495
496 #ifndef __UBOOT__
497 .set_mode = am35x_musb_set_mode,
498 .try_idle = am35x_musb_try_idle,
499
500 .set_vbus = am35x_musb_set_vbus,
501 #endif
502 };
503
504 #ifndef __UBOOT__
505 static u64 am35x_dmamask = DMA_BIT_MASK(32);
506
am35x_probe(struct platform_device * pdev)507 static int __devinit am35x_probe(struct platform_device *pdev)
508 {
509 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
510 struct platform_device *musb;
511 struct am35x_glue *glue;
512
513 struct clk *phy_clk;
514 struct clk *clk;
515
516 int ret = -ENOMEM;
517
518 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
519 if (!glue) {
520 dev_err(&pdev->dev, "failed to allocate glue context\n");
521 goto err0;
522 }
523
524 musb = platform_device_alloc("musb-hdrc", -1);
525 if (!musb) {
526 dev_err(&pdev->dev, "failed to allocate musb device\n");
527 goto err1;
528 }
529
530 phy_clk = clk_get(&pdev->dev, "fck");
531 if (IS_ERR(phy_clk)) {
532 dev_err(&pdev->dev, "failed to get PHY clock\n");
533 ret = PTR_ERR(phy_clk);
534 goto err2;
535 }
536
537 clk = clk_get(&pdev->dev, "ick");
538 if (IS_ERR(clk)) {
539 dev_err(&pdev->dev, "failed to get clock\n");
540 ret = PTR_ERR(clk);
541 goto err3;
542 }
543
544 ret = clk_enable(phy_clk);
545 if (ret) {
546 dev_err(&pdev->dev, "failed to enable PHY clock\n");
547 goto err4;
548 }
549
550 ret = clk_enable(clk);
551 if (ret) {
552 dev_err(&pdev->dev, "failed to enable clock\n");
553 goto err5;
554 }
555
556 musb->dev.parent = &pdev->dev;
557 musb->dev.dma_mask = &am35x_dmamask;
558 musb->dev.coherent_dma_mask = am35x_dmamask;
559
560 glue->dev = &pdev->dev;
561 glue->musb = musb;
562 glue->phy_clk = phy_clk;
563 glue->clk = clk;
564
565 pdata->platform_ops = &am35x_ops;
566
567 platform_set_drvdata(pdev, glue);
568
569 ret = platform_device_add_resources(musb, pdev->resource,
570 pdev->num_resources);
571 if (ret) {
572 dev_err(&pdev->dev, "failed to add resources\n");
573 goto err6;
574 }
575
576 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
577 if (ret) {
578 dev_err(&pdev->dev, "failed to add platform_data\n");
579 goto err6;
580 }
581
582 ret = platform_device_add(musb);
583 if (ret) {
584 dev_err(&pdev->dev, "failed to register musb device\n");
585 goto err6;
586 }
587
588 return 0;
589
590 err6:
591 clk_disable(clk);
592
593 err5:
594 clk_disable(phy_clk);
595
596 err4:
597 clk_put(clk);
598
599 err3:
600 clk_put(phy_clk);
601
602 err2:
603 platform_device_put(musb);
604
605 err1:
606 kfree(glue);
607
608 err0:
609 return ret;
610 }
611
am35x_remove(struct platform_device * pdev)612 static int __devexit am35x_remove(struct platform_device *pdev)
613 {
614 struct am35x_glue *glue = platform_get_drvdata(pdev);
615
616 platform_device_del(glue->musb);
617 platform_device_put(glue->musb);
618 clk_disable(glue->clk);
619 clk_disable(glue->phy_clk);
620 clk_put(glue->clk);
621 clk_put(glue->phy_clk);
622 kfree(glue);
623
624 return 0;
625 }
626
627 #ifdef CONFIG_PM
am35x_suspend(struct device * dev)628 static int am35x_suspend(struct device *dev)
629 {
630 struct am35x_glue *glue = dev_get_drvdata(dev);
631 struct musb_hdrc_platform_data *plat = dev->platform_data;
632 struct omap_musb_board_data *data = plat->board_data;
633
634 /* Shutdown the on-chip PHY and its PLL. */
635 if (data && data->set_phy_power)
636 data->set_phy_power(data->dev, 0);
637
638 clk_disable(glue->phy_clk);
639 clk_disable(glue->clk);
640
641 return 0;
642 }
643
am35x_resume(struct device * dev)644 static int am35x_resume(struct device *dev)
645 {
646 struct am35x_glue *glue = dev_get_drvdata(dev);
647 struct musb_hdrc_platform_data *plat = dev->platform_data;
648 struct omap_musb_board_data *data = plat->board_data;
649 int ret;
650
651 /* Start the on-chip PHY and its PLL. */
652 if (data && data->set_phy_power)
653 data->set_phy_power(data->dev, 1);
654
655 ret = clk_enable(glue->phy_clk);
656 if (ret) {
657 dev_err(dev, "failed to enable PHY clock\n");
658 return ret;
659 }
660
661 ret = clk_enable(glue->clk);
662 if (ret) {
663 dev_err(dev, "failed to enable clock\n");
664 return ret;
665 }
666
667 return 0;
668 }
669
670 static struct dev_pm_ops am35x_pm_ops = {
671 .suspend = am35x_suspend,
672 .resume = am35x_resume,
673 };
674
675 #define DEV_PM_OPS &am35x_pm_ops
676 #else
677 #define DEV_PM_OPS NULL
678 #endif
679
680 static struct platform_driver am35x_driver = {
681 .probe = am35x_probe,
682 .remove = __devexit_p(am35x_remove),
683 .driver = {
684 .name = "musb-am35x",
685 .pm = DEV_PM_OPS,
686 },
687 };
688
689 MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
690 MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
691 MODULE_LICENSE("GPL v2");
692
am35x_init(void)693 static int __init am35x_init(void)
694 {
695 return platform_driver_register(&am35x_driver);
696 }
697 module_init(am35x_init);
698
am35x_exit(void)699 static void __exit am35x_exit(void)
700 {
701 platform_driver_unregister(&am35x_driver);
702 }
703 module_exit(am35x_exit);
704 #endif
705