1 // SPDX-License-Identifier: GPL-2.0
2 /*-
3 * Copyright (c) 2007-2008, Juniper Networks, Inc.
4 * Copyright (c) 2008, Excito Elektronik i Skåne AB
5 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
6 *
7 * All rights reserved.
8 */
9 #include <common.h>
10 #include <cpu_func.h>
11 #include <dm.h>
12 #include <errno.h>
13 #include <log.h>
14 #include <asm/byteorder.h>
15 #include <asm/cache.h>
16 #include <asm/unaligned.h>
17 #include <usb.h>
18 #include <asm/io.h>
19 #include <malloc.h>
20 #include <memalign.h>
21 #include <watchdog.h>
22 #include <dm/device_compat.h>
23 #include <linux/compiler.h>
24 #include <linux/delay.h>
25
26 #include "ehci.h"
27
28 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
29 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
30 #endif
31
32 /*
33 * EHCI spec page 20 says that the HC may take up to 16 uFrames (= 4ms) to halt.
34 * Let's time out after 8 to have a little safety margin on top of that.
35 */
36 #define HCHALT_TIMEOUT (8 * 1000)
37
38 #if !CONFIG_IS_ENABLED(DM_USB)
39 static struct ehci_ctrl ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
40 #endif
41
42 #define ALIGN_END_ADDR(type, ptr, size) \
43 ((unsigned long)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
44
45 static struct descriptor {
46 struct usb_hub_descriptor hub;
47 struct usb_device_descriptor device;
48 struct usb_linux_config_descriptor config;
49 struct usb_linux_interface_descriptor interface;
50 struct usb_endpoint_descriptor endpoint;
51 } __attribute__ ((packed)) descriptor = {
52 {
53 0x8, /* bDescLength */
54 0x29, /* bDescriptorType: hub descriptor */
55 2, /* bNrPorts -- runtime modified */
56 0, /* wHubCharacteristics */
57 10, /* bPwrOn2PwrGood */
58 0, /* bHubCntrCurrent */
59 { /* Device removable */
60 } /* at most 7 ports! XXX */
61 },
62 {
63 0x12, /* bLength */
64 1, /* bDescriptorType: UDESC_DEVICE */
65 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
66 9, /* bDeviceClass: UDCLASS_HUB */
67 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
68 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */
69 64, /* bMaxPacketSize: 64 bytes */
70 0x0000, /* idVendor */
71 0x0000, /* idProduct */
72 cpu_to_le16(0x0100), /* bcdDevice */
73 1, /* iManufacturer */
74 2, /* iProduct */
75 0, /* iSerialNumber */
76 1 /* bNumConfigurations: 1 */
77 },
78 {
79 0x9,
80 2, /* bDescriptorType: UDESC_CONFIG */
81 cpu_to_le16(0x19),
82 1, /* bNumInterface */
83 1, /* bConfigurationValue */
84 0, /* iConfiguration */
85 0x40, /* bmAttributes: UC_SELF_POWER */
86 0 /* bMaxPower */
87 },
88 {
89 0x9, /* bLength */
90 4, /* bDescriptorType: UDESC_INTERFACE */
91 0, /* bInterfaceNumber */
92 0, /* bAlternateSetting */
93 1, /* bNumEndpoints */
94 9, /* bInterfaceClass: UICLASS_HUB */
95 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
96 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
97 0 /* iInterface */
98 },
99 {
100 0x7, /* bLength */
101 5, /* bDescriptorType: UDESC_ENDPOINT */
102 0x81, /* bEndpointAddress:
103 * UE_DIR_IN | EHCI_INTR_ENDPT
104 */
105 3, /* bmAttributes: UE_INTERRUPT */
106 8, /* wMaxPacketSize */
107 255 /* bInterval */
108 },
109 };
110
111 #if defined(CONFIG_EHCI_IS_TDI)
112 #define ehci_is_TDI() (1)
113 #else
114 #define ehci_is_TDI() (0)
115 #endif
116
ehci_get_ctrl(struct usb_device * udev)117 static struct ehci_ctrl *ehci_get_ctrl(struct usb_device *udev)
118 {
119 #if CONFIG_IS_ENABLED(DM_USB)
120 return dev_get_priv(usb_get_bus(udev->dev));
121 #else
122 return udev->controller;
123 #endif
124 }
125
ehci_get_port_speed(struct ehci_ctrl * ctrl,uint32_t reg)126 static int ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg)
127 {
128 return PORTSC_PSPD(reg);
129 }
130
ehci_set_usbmode(struct ehci_ctrl * ctrl)131 static void ehci_set_usbmode(struct ehci_ctrl *ctrl)
132 {
133 uint32_t tmp;
134 uint32_t *reg_ptr;
135
136 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + USBMODE);
137 tmp = ehci_readl(reg_ptr);
138 tmp |= USBMODE_CM_HC;
139 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
140 tmp |= USBMODE_BE;
141 #else
142 tmp &= ~USBMODE_BE;
143 #endif
144 ehci_writel(reg_ptr, tmp);
145 }
146
ehci_powerup_fixup(struct ehci_ctrl * ctrl,uint32_t * status_reg,uint32_t * reg)147 static void ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
148 uint32_t *reg)
149 {
150 mdelay(50);
151 }
152
ehci_get_portsc_register(struct ehci_ctrl * ctrl,int port)153 static uint32_t *ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port)
154 {
155 int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams));
156
157 if (port < 0 || port >= max_ports) {
158 /* Printing the message would cause a scan failure! */
159 debug("The request port(%u) exceeds maximum port number\n",
160 port);
161 return NULL;
162 }
163
164 return (uint32_t *)&ctrl->hcor->or_portsc[port];
165 }
166
handshake(uint32_t * ptr,uint32_t mask,uint32_t done,int usec)167 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
168 {
169 uint32_t result;
170 do {
171 result = ehci_readl(ptr);
172 udelay(5);
173 if (result == ~(uint32_t)0)
174 return -1;
175 result &= mask;
176 if (result == done)
177 return 0;
178 usec--;
179 } while (usec > 0);
180 return -1;
181 }
182
ehci_reset(struct ehci_ctrl * ctrl)183 static int ehci_reset(struct ehci_ctrl *ctrl)
184 {
185 uint32_t cmd;
186 int ret = 0;
187
188 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
189 cmd = (cmd & ~CMD_RUN) | CMD_RESET;
190 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
191 ret = handshake((uint32_t *)&ctrl->hcor->or_usbcmd,
192 CMD_RESET, 0, 250 * 1000);
193 if (ret < 0) {
194 printf("EHCI fail to reset\n");
195 goto out;
196 }
197
198 if (ehci_is_TDI())
199 ctrl->ops.set_usb_mode(ctrl);
200
201 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
202 cmd = ehci_readl(&ctrl->hcor->or_txfilltuning);
203 cmd &= ~TXFIFO_THRESH_MASK;
204 cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
205 ehci_writel(&ctrl->hcor->or_txfilltuning, cmd);
206 #endif
207 out:
208 return ret;
209 }
210
ehci_shutdown(struct ehci_ctrl * ctrl)211 static int ehci_shutdown(struct ehci_ctrl *ctrl)
212 {
213 int i, ret = 0;
214 uint32_t cmd, reg;
215 int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams));
216
217 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
218 /* If not run, directly return */
219 if (!(cmd & CMD_RUN))
220 return 0;
221 cmd &= ~(CMD_PSE | CMD_ASE);
222 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
223 ret = handshake(&ctrl->hcor->or_usbsts, STS_ASS | STS_PSS, 0,
224 100 * 1000);
225
226 if (!ret) {
227 for (i = 0; i < max_ports; i++) {
228 reg = ehci_readl(&ctrl->hcor->or_portsc[i]);
229 reg |= EHCI_PS_SUSP;
230 ehci_writel(&ctrl->hcor->or_portsc[i], reg);
231 }
232
233 cmd &= ~CMD_RUN;
234 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
235 ret = handshake(&ctrl->hcor->or_usbsts, STS_HALT, STS_HALT,
236 HCHALT_TIMEOUT);
237 }
238
239 if (ret)
240 puts("EHCI failed to shut down host controller.\n");
241
242 return ret;
243 }
244
ehci_td_buffer(struct qTD * td,void * buf,size_t sz)245 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
246 {
247 uint32_t delta, next;
248 unsigned long addr = (unsigned long)buf;
249 int idx;
250
251 if (addr != ALIGN(addr, ARCH_DMA_MINALIGN))
252 debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf);
253
254 flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN));
255
256 idx = 0;
257 while (idx < QT_BUFFER_CNT) {
258 td->qt_buffer[idx] = cpu_to_hc32(virt_to_phys((void *)addr));
259 td->qt_buffer_hi[idx] = 0;
260 next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1);
261 delta = next - addr;
262 if (delta >= sz)
263 break;
264 sz -= delta;
265 addr = next;
266 idx++;
267 }
268
269 if (idx == QT_BUFFER_CNT) {
270 printf("out of buffer pointers (%zu bytes left)\n", sz);
271 return -1;
272 }
273
274 return 0;
275 }
276
ehci_encode_speed(enum usb_device_speed speed)277 static inline u8 ehci_encode_speed(enum usb_device_speed speed)
278 {
279 #define QH_HIGH_SPEED 2
280 #define QH_FULL_SPEED 0
281 #define QH_LOW_SPEED 1
282 if (speed == USB_SPEED_HIGH)
283 return QH_HIGH_SPEED;
284 if (speed == USB_SPEED_LOW)
285 return QH_LOW_SPEED;
286 return QH_FULL_SPEED;
287 }
288
ehci_update_endpt2_dev_n_port(struct usb_device * udev,struct QH * qh)289 static void ehci_update_endpt2_dev_n_port(struct usb_device *udev,
290 struct QH *qh)
291 {
292 uint8_t portnr = 0;
293 uint8_t hubaddr = 0;
294
295 if (udev->speed != USB_SPEED_LOW && udev->speed != USB_SPEED_FULL)
296 return;
297
298 usb_find_usb2_hub_address_port(udev, &hubaddr, &portnr);
299
300 qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(portnr) |
301 QH_ENDPT2_HUBADDR(hubaddr));
302 }
303
ehci_enable_async(struct ehci_ctrl * ctrl)304 static int ehci_enable_async(struct ehci_ctrl *ctrl)
305 {
306 u32 cmd;
307 int ret;
308
309 /* Enable async. schedule. */
310 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
311 if (cmd & CMD_ASE)
312 return 0;
313
314 cmd |= CMD_ASE;
315 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
316
317 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS,
318 100 * 1000);
319 if (ret < 0)
320 printf("EHCI fail timeout STS_ASS set\n");
321
322 return ret;
323 }
324
ehci_disable_async(struct ehci_ctrl * ctrl)325 static int ehci_disable_async(struct ehci_ctrl *ctrl)
326 {
327 u32 cmd;
328 int ret;
329
330 if (ctrl->async_locked)
331 return 0;
332
333 /* Disable async schedule. */
334 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
335 if (!(cmd & CMD_ASE))
336 return 0;
337
338 cmd &= ~CMD_ASE;
339 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
340
341 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0,
342 100 * 1000);
343 if (ret < 0)
344 printf("EHCI fail timeout STS_ASS reset\n");
345
346 return ret;
347 }
348
ehci_iaa_cycle(struct ehci_ctrl * ctrl)349 static int ehci_iaa_cycle(struct ehci_ctrl *ctrl)
350 {
351 u32 cmd, status;
352 int ret;
353
354 /* Enable Interrupt on Async Advance Doorbell. */
355 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
356 cmd |= CMD_IAAD;
357 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
358
359 ret = handshake(&ctrl->hcor->or_usbsts, STS_IAA, STS_IAA,
360 10 * 1000); /* 10ms timeout */
361 if (ret < 0)
362 printf("EHCI fail timeout STS_IAA set\n");
363
364 status = ehci_readl(&ctrl->hcor->or_usbsts);
365 if (status & STS_IAA)
366 ehci_writel(&ctrl->hcor->or_usbsts, STS_IAA);
367
368 return ret;
369 }
370
371 static int
ehci_submit_async(struct usb_device * dev,unsigned long pipe,void * buffer,int length,struct devrequest * req)372 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
373 int length, struct devrequest *req)
374 {
375 ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
376 struct qTD *qtd;
377 int qtd_count = 0;
378 int qtd_counter = 0;
379 volatile struct qTD *vtd;
380 unsigned long ts;
381 uint32_t *tdp;
382 uint32_t endpt, maxpacket, token, usbsts, qhtoken;
383 uint32_t c, toggle;
384 int timeout;
385 int ret = 0;
386 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
387
388 debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
389 buffer, length, req);
390 if (req != NULL)
391 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
392 req->request, req->request,
393 req->requesttype, req->requesttype,
394 le16_to_cpu(req->value), le16_to_cpu(req->value),
395 le16_to_cpu(req->index));
396
397 #define PKT_ALIGN 512
398 /*
399 * The USB transfer is split into qTD transfers. Eeach qTD transfer is
400 * described by a transfer descriptor (the qTD). The qTDs form a linked
401 * list with a queue head (QH).
402 *
403 * Each qTD transfer starts with a new USB packet, i.e. a packet cannot
404 * have its beginning in a qTD transfer and its end in the following
405 * one, so the qTD transfer lengths have to be chosen accordingly.
406 *
407 * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to
408 * single pages. The first data buffer can start at any offset within a
409 * page (not considering the cache-line alignment issues), while the
410 * following buffers must be page-aligned. There is no alignment
411 * constraint on the size of a qTD transfer.
412 */
413 if (req != NULL)
414 /* 1 qTD will be needed for SETUP, and 1 for ACK. */
415 qtd_count += 1 + 1;
416 if (length > 0 || req == NULL) {
417 /*
418 * Determine the qTD transfer size that will be used for the
419 * data payload (not considering the first qTD transfer, which
420 * may be longer or shorter, and the final one, which may be
421 * shorter).
422 *
423 * In order to keep each packet within a qTD transfer, the qTD
424 * transfer size is aligned to PKT_ALIGN, which is a multiple of
425 * wMaxPacketSize (except in some cases for interrupt transfers,
426 * see comment in submit_int_msg()).
427 *
428 * By default, i.e. if the input buffer is aligned to PKT_ALIGN,
429 * QT_BUFFER_CNT full pages will be used.
430 */
431 int xfr_sz = QT_BUFFER_CNT;
432 /*
433 * However, if the input buffer is not aligned to PKT_ALIGN, the
434 * qTD transfer size will be one page shorter, and the first qTD
435 * data buffer of each transfer will be page-unaligned.
436 */
437 if ((unsigned long)buffer & (PKT_ALIGN - 1))
438 xfr_sz--;
439 /* Convert the qTD transfer size to bytes. */
440 xfr_sz *= EHCI_PAGE_SIZE;
441 /*
442 * Approximate by excess the number of qTDs that will be
443 * required for the data payload. The exact formula is way more
444 * complicated and saves at most 2 qTDs, i.e. a total of 128
445 * bytes.
446 */
447 qtd_count += 2 + length / xfr_sz;
448 }
449 /*
450 * Threshold value based on the worst-case total size of the allocated qTDs for
451 * a mass-storage transfer of 65535 blocks of 512 bytes.
452 */
453 #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024
454 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI
455 #endif
456 qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD));
457 if (qtd == NULL) {
458 printf("unable to allocate TDs\n");
459 return -1;
460 }
461
462 memset(qh, 0, sizeof(struct QH));
463 memset(qtd, 0, qtd_count * sizeof(*qtd));
464
465 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
466
467 /*
468 * Setup QH (3.6 in ehci-r10.pdf)
469 *
470 * qh_link ................. 03-00 H
471 * qh_endpt1 ............... 07-04 H
472 * qh_endpt2 ............... 0B-08 H
473 * - qh_curtd
474 * qh_overlay.qt_next ...... 13-10 H
475 * - qh_overlay.qt_altnext
476 */
477 qh->qh_link = cpu_to_hc32(virt_to_phys(&ctrl->qh_list) | QH_LINK_TYPE_QH);
478 c = (dev->speed != USB_SPEED_HIGH) && !usb_pipeendpoint(pipe);
479 maxpacket = usb_maxpacket(dev, pipe);
480 endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
481 QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) |
482 QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) |
483 QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
484 QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
485
486 /* Force FS for fsl HS quirk */
487 if (!ctrl->has_fsl_erratum_a005275)
488 endpt |= QH_ENDPT1_EPS(ehci_encode_speed(dev->speed));
489 else
490 endpt |= QH_ENDPT1_EPS(ehci_encode_speed(QH_FULL_SPEED));
491
492 qh->qh_endpt1 = cpu_to_hc32(endpt);
493 endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
494 qh->qh_endpt2 = cpu_to_hc32(endpt);
495 ehci_update_endpt2_dev_n_port(dev, qh);
496 qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
497 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
498
499 tdp = &qh->qh_overlay.qt_next;
500 if (req != NULL) {
501 /*
502 * Setup request qTD (3.5 in ehci-r10.pdf)
503 *
504 * qt_next ................ 03-00 H
505 * qt_altnext ............. 07-04 H
506 * qt_token ............... 0B-08 H
507 *
508 * [ buffer, buffer_hi ] loaded with "req".
509 */
510 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
511 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
512 token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) |
513 QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
514 QT_TOKEN_PID(QT_TOKEN_PID_SETUP) |
515 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
516 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
517 if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) {
518 printf("unable to construct SETUP TD\n");
519 goto fail;
520 }
521 /* Update previous qTD! */
522 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
523 tdp = &qtd[qtd_counter++].qt_next;
524 toggle = 1;
525 }
526
527 if (length > 0 || req == NULL) {
528 uint8_t *buf_ptr = buffer;
529 int left_length = length;
530
531 do {
532 /*
533 * Determine the size of this qTD transfer. By default,
534 * QT_BUFFER_CNT full pages can be used.
535 */
536 int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE;
537 /*
538 * However, if the input buffer is not page-aligned, the
539 * portion of the first page before the buffer start
540 * offset within that page is unusable.
541 */
542 xfr_bytes -= (unsigned long)buf_ptr & (EHCI_PAGE_SIZE - 1);
543 /*
544 * In order to keep each packet within a qTD transfer,
545 * align the qTD transfer size to PKT_ALIGN.
546 */
547 xfr_bytes &= ~(PKT_ALIGN - 1);
548 /*
549 * This transfer may be shorter than the available qTD
550 * transfer size that has just been computed.
551 */
552 xfr_bytes = min(xfr_bytes, left_length);
553
554 /*
555 * Setup request qTD (3.5 in ehci-r10.pdf)
556 *
557 * qt_next ................ 03-00 H
558 * qt_altnext ............. 07-04 H
559 * qt_token ............... 0B-08 H
560 *
561 * [ buffer, buffer_hi ] loaded with "buffer".
562 */
563 qtd[qtd_counter].qt_next =
564 cpu_to_hc32(QT_NEXT_TERMINATE);
565 qtd[qtd_counter].qt_altnext =
566 cpu_to_hc32(QT_NEXT_TERMINATE);
567 token = QT_TOKEN_DT(toggle) |
568 QT_TOKEN_TOTALBYTES(xfr_bytes) |
569 QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) |
570 QT_TOKEN_CERR(3) |
571 QT_TOKEN_PID(usb_pipein(pipe) ?
572 QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) |
573 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
574 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
575 if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr,
576 xfr_bytes)) {
577 printf("unable to construct DATA TD\n");
578 goto fail;
579 }
580 /* Update previous qTD! */
581 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
582 tdp = &qtd[qtd_counter++].qt_next;
583 /*
584 * Data toggle has to be adjusted since the qTD transfer
585 * size is not always an even multiple of
586 * wMaxPacketSize.
587 */
588 if ((xfr_bytes / maxpacket) & 1)
589 toggle ^= 1;
590 buf_ptr += xfr_bytes;
591 left_length -= xfr_bytes;
592 } while (left_length > 0);
593 }
594
595 if (req != NULL) {
596 /*
597 * Setup request qTD (3.5 in ehci-r10.pdf)
598 *
599 * qt_next ................ 03-00 H
600 * qt_altnext ............. 07-04 H
601 * qt_token ............... 0B-08 H
602 */
603 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
604 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
605 token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) |
606 QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
607 QT_TOKEN_PID(usb_pipein(pipe) ?
608 QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) |
609 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
610 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
611 /* Update previous qTD! */
612 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
613 tdp = &qtd[qtd_counter++].qt_next;
614 }
615
616 ctrl->qh_list.qh_link = cpu_to_hc32(virt_to_phys(qh) | QH_LINK_TYPE_QH);
617
618 /* Flush dcache */
619 flush_dcache_range((unsigned long)&ctrl->qh_list,
620 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
621 flush_dcache_range((unsigned long)qh, ALIGN_END_ADDR(struct QH, qh, 1));
622 flush_dcache_range((unsigned long)qtd,
623 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
624
625 usbsts = ehci_readl(&ctrl->hcor->or_usbsts);
626 ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f));
627
628 ret = ehci_enable_async(ctrl);
629 if (ret)
630 goto fail;
631
632 /* Wait for TDs to be processed. */
633 ts = get_timer(0);
634 vtd = &qtd[qtd_counter - 1];
635 timeout = USB_TIMEOUT_MS(pipe);
636 do {
637 /* Invalidate dcache */
638 invalidate_dcache_range((unsigned long)&ctrl->qh_list,
639 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
640 invalidate_dcache_range((unsigned long)qh,
641 ALIGN_END_ADDR(struct QH, qh, 1));
642 invalidate_dcache_range((unsigned long)qtd,
643 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
644
645 token = hc32_to_cpu(vtd->qt_token);
646 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
647 break;
648 WATCHDOG_RESET();
649 } while (get_timer(ts) < timeout);
650 qhtoken = hc32_to_cpu(qh->qh_overlay.qt_token);
651
652 ctrl->qh_list.qh_link = cpu_to_hc32(virt_to_phys(&ctrl->qh_list) | QH_LINK_TYPE_QH);
653 flush_dcache_range((unsigned long)&ctrl->qh_list,
654 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
655
656 /* Set IAAD, poll IAA */
657 ret = ehci_iaa_cycle(ctrl);
658 if (ret)
659 goto fail;
660
661 /*
662 * Invalidate the memory area occupied by buffer
663 * Don't try to fix the buffer alignment, if it isn't properly
664 * aligned it's upper layer's fault so let invalidate_dcache_range()
665 * vow about it. But we have to fix the length as it's actual
666 * transfer length and can be unaligned. This is potentially
667 * dangerous operation, it's responsibility of the calling
668 * code to make sure enough space is reserved.
669 */
670 if (buffer != NULL && length > 0)
671 invalidate_dcache_range((unsigned long)buffer,
672 ALIGN((unsigned long)buffer + length, ARCH_DMA_MINALIGN));
673
674 /* Check that the TD processing happened */
675 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
676 printf("EHCI timed out on TD - token=%#x\n", token);
677
678 ret = ehci_disable_async(ctrl);
679 if (ret)
680 goto fail;
681
682 if (!(QT_TOKEN_GET_STATUS(qhtoken) & QT_TOKEN_STATUS_ACTIVE)) {
683 debug("TOKEN=%#x\n", qhtoken);
684 switch (QT_TOKEN_GET_STATUS(qhtoken) &
685 ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) {
686 case 0:
687 toggle = QT_TOKEN_GET_DT(qhtoken);
688 usb_settoggle(dev, usb_pipeendpoint(pipe),
689 usb_pipeout(pipe), toggle);
690 dev->status = 0;
691 break;
692 case QT_TOKEN_STATUS_HALTED:
693 dev->status = USB_ST_STALLED;
694 break;
695 case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR:
696 case QT_TOKEN_STATUS_DATBUFERR:
697 dev->status = USB_ST_BUF_ERR;
698 break;
699 case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET:
700 case QT_TOKEN_STATUS_BABBLEDET:
701 dev->status = USB_ST_BABBLE_DET;
702 break;
703 default:
704 dev->status = USB_ST_CRC_ERR;
705 if (QT_TOKEN_GET_STATUS(qhtoken) & QT_TOKEN_STATUS_HALTED)
706 dev->status |= USB_ST_STALLED;
707 break;
708 }
709 dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(qhtoken);
710 } else {
711 dev->act_len = 0;
712 #ifndef CONFIG_USB_EHCI_FARADAY
713 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
714 dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts),
715 ehci_readl(&ctrl->hcor->or_portsc[0]),
716 ehci_readl(&ctrl->hcor->or_portsc[1]));
717 #endif
718 }
719
720 free(qtd);
721 return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
722
723 fail:
724 free(qtd);
725 return -1;
726 }
727
ehci_submit_root(struct usb_device * dev,unsigned long pipe,void * buffer,int length,struct devrequest * req)728 static int ehci_submit_root(struct usb_device *dev, unsigned long pipe,
729 void *buffer, int length, struct devrequest *req)
730 {
731 uint8_t tmpbuf[4];
732 u16 typeReq;
733 void *srcptr = NULL;
734 int len, srclen;
735 uint32_t reg;
736 uint32_t *status_reg;
737 int port = le16_to_cpu(req->index) & 0xff;
738 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
739
740 srclen = 0;
741
742 debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
743 req->request, req->request,
744 req->requesttype, req->requesttype,
745 le16_to_cpu(req->value), le16_to_cpu(req->index));
746
747 typeReq = req->request | req->requesttype << 8;
748
749 switch (typeReq) {
750 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
751 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
752 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
753 status_reg = ctrl->ops.get_portsc_register(ctrl, port - 1);
754 if (!status_reg)
755 return -1;
756 break;
757 default:
758 status_reg = NULL;
759 break;
760 }
761
762 switch (typeReq) {
763 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
764 switch (le16_to_cpu(req->value) >> 8) {
765 case USB_DT_DEVICE:
766 debug("USB_DT_DEVICE request\n");
767 srcptr = &descriptor.device;
768 srclen = descriptor.device.bLength;
769 break;
770 case USB_DT_CONFIG:
771 debug("USB_DT_CONFIG config\n");
772 srcptr = &descriptor.config;
773 srclen = descriptor.config.bLength +
774 descriptor.interface.bLength +
775 descriptor.endpoint.bLength;
776 break;
777 case USB_DT_STRING:
778 debug("USB_DT_STRING config\n");
779 switch (le16_to_cpu(req->value) & 0xff) {
780 case 0: /* Language */
781 srcptr = "\4\3\1\0";
782 srclen = 4;
783 break;
784 case 1: /* Vendor */
785 srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
786 srclen = 14;
787 break;
788 case 2: /* Product */
789 srcptr = "\52\3E\0H\0C\0I\0 "
790 "\0H\0o\0s\0t\0 "
791 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
792 srclen = 42;
793 break;
794 default:
795 debug("unknown value DT_STRING %x\n",
796 le16_to_cpu(req->value));
797 goto unknown;
798 }
799 break;
800 default:
801 debug("unknown value %x\n", le16_to_cpu(req->value));
802 goto unknown;
803 }
804 break;
805 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
806 switch (le16_to_cpu(req->value) >> 8) {
807 case USB_DT_HUB:
808 debug("USB_DT_HUB config\n");
809 srcptr = &descriptor.hub;
810 srclen = descriptor.hub.bLength;
811 break;
812 default:
813 debug("unknown value %x\n", le16_to_cpu(req->value));
814 goto unknown;
815 }
816 break;
817 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
818 debug("USB_REQ_SET_ADDRESS\n");
819 ctrl->rootdev = le16_to_cpu(req->value);
820 break;
821 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
822 debug("USB_REQ_SET_CONFIGURATION\n");
823 /* Nothing to do */
824 break;
825 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
826 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
827 tmpbuf[1] = 0;
828 srcptr = tmpbuf;
829 srclen = 2;
830 break;
831 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
832 memset(tmpbuf, 0, 4);
833 reg = ehci_readl(status_reg);
834 if (reg & EHCI_PS_CS)
835 tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
836 if (reg & EHCI_PS_PE)
837 tmpbuf[0] |= USB_PORT_STAT_ENABLE;
838 if (reg & EHCI_PS_SUSP)
839 tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
840 if (reg & EHCI_PS_OCA)
841 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
842 if (reg & EHCI_PS_PR)
843 tmpbuf[0] |= USB_PORT_STAT_RESET;
844 if (reg & EHCI_PS_PP)
845 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
846
847 if (ehci_is_TDI()) {
848 switch (ctrl->ops.get_port_speed(ctrl, reg)) {
849 case PORTSC_PSPD_FS:
850 break;
851 case PORTSC_PSPD_LS:
852 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
853 break;
854 case PORTSC_PSPD_HS:
855 default:
856 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
857 break;
858 }
859 } else {
860 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
861 }
862
863 if (reg & EHCI_PS_CSC)
864 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
865 if (reg & EHCI_PS_PEC)
866 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
867 if (reg & EHCI_PS_OCC)
868 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
869 if (ctrl->portreset & (1 << port))
870 tmpbuf[2] |= USB_PORT_STAT_C_RESET;
871
872 srcptr = tmpbuf;
873 srclen = 4;
874 break;
875 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
876 reg = ehci_readl(status_reg);
877 reg &= ~EHCI_PS_CLEAR;
878 switch (le16_to_cpu(req->value)) {
879 case USB_PORT_FEAT_ENABLE:
880 reg |= EHCI_PS_PE;
881 ehci_writel(status_reg, reg);
882 break;
883 case USB_PORT_FEAT_POWER:
884 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) {
885 reg |= EHCI_PS_PP;
886 ehci_writel(status_reg, reg);
887 }
888 break;
889 case USB_PORT_FEAT_RESET:
890 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
891 !ehci_is_TDI() &&
892 EHCI_PS_IS_LOWSPEED(reg)) {
893 /* Low speed device, give up ownership. */
894 debug("port %d low speed --> companion\n",
895 port - 1);
896 reg |= EHCI_PS_PO;
897 ehci_writel(status_reg, reg);
898 return -ENXIO;
899 } else {
900 int ret;
901
902 /* Disable chirp for HS erratum */
903 if (ctrl->has_fsl_erratum_a005275)
904 reg |= PORTSC_FSL_PFSC;
905
906 reg |= EHCI_PS_PR;
907 reg &= ~EHCI_PS_PE;
908 ehci_writel(status_reg, reg);
909 /*
910 * caller must wait, then call GetPortStatus
911 * usb 2.0 specification say 50 ms resets on
912 * root
913 */
914 ctrl->ops.powerup_fixup(ctrl, status_reg, ®);
915
916 ehci_writel(status_reg, reg & ~EHCI_PS_PR);
917 /*
918 * A host controller must terminate the reset
919 * and stabilize the state of the port within
920 * 2 milliseconds
921 */
922 ret = handshake(status_reg, EHCI_PS_PR, 0,
923 2 * 1000);
924 if (!ret) {
925 reg = ehci_readl(status_reg);
926 if ((reg & (EHCI_PS_PE | EHCI_PS_CS))
927 == EHCI_PS_CS && !ehci_is_TDI()) {
928 debug("port %d full speed --> companion\n", port - 1);
929 reg &= ~EHCI_PS_CLEAR;
930 reg |= EHCI_PS_PO;
931 ehci_writel(status_reg, reg);
932 return -ENXIO;
933 } else {
934 ctrl->portreset |= 1 << port;
935 }
936 } else {
937 printf("port(%d) reset error\n",
938 port - 1);
939 }
940 }
941 break;
942 case USB_PORT_FEAT_TEST:
943 ehci_shutdown(ctrl);
944 reg &= ~(0xf << 16);
945 reg |= ((le16_to_cpu(req->index) >> 8) & 0xf) << 16;
946 ehci_writel(status_reg, reg);
947 break;
948 default:
949 debug("unknown feature %x\n", le16_to_cpu(req->value));
950 goto unknown;
951 }
952 /* unblock posted writes */
953 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
954 break;
955 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
956 reg = ehci_readl(status_reg);
957 reg &= ~EHCI_PS_CLEAR;
958 switch (le16_to_cpu(req->value)) {
959 case USB_PORT_FEAT_ENABLE:
960 reg &= ~EHCI_PS_PE;
961 break;
962 case USB_PORT_FEAT_C_ENABLE:
963 reg |= EHCI_PS_PE;
964 break;
965 case USB_PORT_FEAT_POWER:
966 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams)))
967 reg &= ~EHCI_PS_PP;
968 break;
969 case USB_PORT_FEAT_C_CONNECTION:
970 reg |= EHCI_PS_CSC;
971 break;
972 case USB_PORT_FEAT_OVER_CURRENT:
973 reg |= EHCI_PS_OCC;
974 break;
975 case USB_PORT_FEAT_C_RESET:
976 ctrl->portreset &= ~(1 << port);
977 break;
978 default:
979 debug("unknown feature %x\n", le16_to_cpu(req->value));
980 goto unknown;
981 }
982 ehci_writel(status_reg, reg);
983 /* unblock posted write */
984 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
985 break;
986 default:
987 debug("Unknown request\n");
988 goto unknown;
989 }
990
991 mdelay(1);
992 len = min3(srclen, (int)le16_to_cpu(req->length), length);
993 if (srcptr != NULL && len > 0)
994 memcpy(buffer, srcptr, len);
995 else
996 debug("Len is 0\n");
997
998 dev->act_len = len;
999 dev->status = 0;
1000 return 0;
1001
1002 unknown:
1003 debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
1004 req->requesttype, req->request, le16_to_cpu(req->value),
1005 le16_to_cpu(req->index), le16_to_cpu(req->length));
1006
1007 dev->act_len = 0;
1008 dev->status = USB_ST_STALLED;
1009 return -1;
1010 }
1011
1012 static const struct ehci_ops default_ehci_ops = {
1013 .set_usb_mode = ehci_set_usbmode,
1014 .get_port_speed = ehci_get_port_speed,
1015 .powerup_fixup = ehci_powerup_fixup,
1016 .get_portsc_register = ehci_get_portsc_register,
1017 };
1018
ehci_setup_ops(struct ehci_ctrl * ctrl,const struct ehci_ops * ops)1019 static void ehci_setup_ops(struct ehci_ctrl *ctrl, const struct ehci_ops *ops)
1020 {
1021 if (!ops) {
1022 ctrl->ops = default_ehci_ops;
1023 } else {
1024 ctrl->ops = *ops;
1025 if (!ctrl->ops.set_usb_mode)
1026 ctrl->ops.set_usb_mode = ehci_set_usbmode;
1027 if (!ctrl->ops.get_port_speed)
1028 ctrl->ops.get_port_speed = ehci_get_port_speed;
1029 if (!ctrl->ops.powerup_fixup)
1030 ctrl->ops.powerup_fixup = ehci_powerup_fixup;
1031 if (!ctrl->ops.get_portsc_register)
1032 ctrl->ops.get_portsc_register =
1033 ehci_get_portsc_register;
1034 }
1035 }
1036
1037 #if !CONFIG_IS_ENABLED(DM_USB)
ehci_set_controller_priv(int index,void * priv,const struct ehci_ops * ops)1038 void ehci_set_controller_priv(int index, void *priv, const struct ehci_ops *ops)
1039 {
1040 struct ehci_ctrl *ctrl = &ehcic[index];
1041
1042 ctrl->priv = priv;
1043 ehci_setup_ops(ctrl, ops);
1044 }
1045
ehci_get_controller_priv(int index)1046 void *ehci_get_controller_priv(int index)
1047 {
1048 return ehcic[index].priv;
1049 }
1050 #endif
1051
ehci_common_init(struct ehci_ctrl * ctrl,uint tweaks)1052 static int ehci_common_init(struct ehci_ctrl *ctrl, uint tweaks)
1053 {
1054 struct QH *qh_list;
1055 struct QH *periodic;
1056 uint32_t reg;
1057 uint32_t cmd;
1058 int i;
1059
1060 /* Set the high address word (aka segment) for 64-bit controller */
1061 if (ehci_readl(&ctrl->hccr->cr_hccparams) & 1)
1062 ehci_writel(&ctrl->hcor->or_ctrldssegment, 0);
1063
1064 qh_list = &ctrl->qh_list;
1065
1066 /* Set head of reclaim list */
1067 memset(qh_list, 0, sizeof(*qh_list));
1068 qh_list->qh_link = cpu_to_hc32(virt_to_phys(qh_list) | QH_LINK_TYPE_QH);
1069 qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
1070 QH_ENDPT1_EPS(USB_SPEED_HIGH));
1071 qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1072 qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1073 qh_list->qh_overlay.qt_token =
1074 cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
1075
1076 flush_dcache_range((unsigned long)qh_list,
1077 ALIGN_END_ADDR(struct QH, qh_list, 1));
1078
1079 /* Set async. queue head pointer. */
1080 ehci_writel(&ctrl->hcor->or_asynclistaddr, virt_to_phys(qh_list));
1081
1082 /*
1083 * Set up periodic list
1084 * Step 1: Parent QH for all periodic transfers.
1085 */
1086 ctrl->periodic_schedules = 0;
1087 periodic = &ctrl->periodic_queue;
1088 memset(periodic, 0, sizeof(*periodic));
1089 periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
1090 periodic->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1091 periodic->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1092
1093 flush_dcache_range((unsigned long)periodic,
1094 ALIGN_END_ADDR(struct QH, periodic, 1));
1095
1096 /*
1097 * Step 2: Setup frame-list: Every microframe, USB tries the same list.
1098 * In particular, device specifications on polling frequency
1099 * are disregarded. Keyboards seem to send NAK/NYet reliably
1100 * when polled with an empty buffer.
1101 *
1102 * Split Transactions will be spread across microframes using
1103 * S-mask and C-mask.
1104 */
1105 if (ctrl->periodic_list == NULL)
1106 ctrl->periodic_list = memalign(4096, 1024 * 4);
1107
1108 if (!ctrl->periodic_list)
1109 return -ENOMEM;
1110 for (i = 0; i < 1024; i++) {
1111 ctrl->periodic_list[i] = cpu_to_hc32((unsigned long)periodic
1112 | QH_LINK_TYPE_QH);
1113 }
1114
1115 flush_dcache_range((unsigned long)ctrl->periodic_list,
1116 ALIGN_END_ADDR(uint32_t, ctrl->periodic_list,
1117 1024));
1118
1119 /* Set periodic list base address */
1120 ehci_writel(&ctrl->hcor->or_periodiclistbase,
1121 (unsigned long)ctrl->periodic_list);
1122
1123 reg = ehci_readl(&ctrl->hccr->cr_hcsparams);
1124 descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
1125 debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
1126 /* Port Indicators */
1127 if (HCS_INDICATOR(reg))
1128 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1129 | 0x80, &descriptor.hub.wHubCharacteristics);
1130 /* Port Power Control */
1131 if (HCS_PPC(reg))
1132 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1133 | 0x01, &descriptor.hub.wHubCharacteristics);
1134
1135 /* Start the host controller. */
1136 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
1137 /*
1138 * Philips, Intel, and maybe others need CMD_RUN before the
1139 * root hub will detect new devices (why?); NEC doesn't
1140 */
1141 cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
1142 cmd |= CMD_RUN;
1143 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
1144
1145 if (!(tweaks & EHCI_TWEAK_NO_INIT_CF)) {
1146 /* take control over the ports */
1147 cmd = ehci_readl(&ctrl->hcor->or_configflag);
1148 cmd |= FLAG_CF;
1149 ehci_writel(&ctrl->hcor->or_configflag, cmd);
1150 }
1151
1152 /* unblock posted write */
1153 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
1154 mdelay(5);
1155 reg = HC_VERSION(ehci_readl(&ctrl->hccr->cr_capbase));
1156 printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
1157
1158 return 0;
1159 }
1160
1161 #if !CONFIG_IS_ENABLED(DM_USB)
usb_lowlevel_stop(int index)1162 int usb_lowlevel_stop(int index)
1163 {
1164 ehci_shutdown(&ehcic[index]);
1165 return ehci_hcd_stop(index);
1166 }
1167
usb_lowlevel_init(int index,enum usb_init_type init,void ** controller)1168 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1169 {
1170 struct ehci_ctrl *ctrl = &ehcic[index];
1171 uint tweaks = 0;
1172 int rc;
1173
1174 /**
1175 * Set ops to default_ehci_ops, ehci_hcd_init should call
1176 * ehci_set_controller_priv to change any of these function pointers.
1177 */
1178 ctrl->ops = default_ehci_ops;
1179
1180 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
1181 if (rc)
1182 return rc;
1183 if (!ctrl->hccr || !ctrl->hcor)
1184 return -1;
1185 if (init == USB_INIT_DEVICE)
1186 goto done;
1187
1188 /* EHCI spec section 4.1 */
1189 if (ehci_reset(ctrl))
1190 return -1;
1191
1192 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
1193 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
1194 if (rc)
1195 return rc;
1196 #endif
1197 #ifdef CONFIG_USB_EHCI_FARADAY
1198 tweaks |= EHCI_TWEAK_NO_INIT_CF;
1199 #endif
1200 rc = ehci_common_init(ctrl, tweaks);
1201 if (rc)
1202 return rc;
1203
1204 ctrl->rootdev = 0;
1205 done:
1206 *controller = &ehcic[index];
1207 return 0;
1208 }
1209 #endif
1210
_ehci_submit_bulk_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int length)1211 static int _ehci_submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
1212 void *buffer, int length)
1213 {
1214
1215 if (usb_pipetype(pipe) != PIPE_BULK) {
1216 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
1217 return -1;
1218 }
1219 return ehci_submit_async(dev, pipe, buffer, length, NULL);
1220 }
1221
_ehci_submit_control_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int length,struct devrequest * setup)1222 static int _ehci_submit_control_msg(struct usb_device *dev, unsigned long pipe,
1223 void *buffer, int length,
1224 struct devrequest *setup)
1225 {
1226 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1227
1228 if (usb_pipetype(pipe) != PIPE_CONTROL) {
1229 debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
1230 return -1;
1231 }
1232
1233 if (usb_pipedevice(pipe) == ctrl->rootdev) {
1234 if (!ctrl->rootdev)
1235 dev->speed = USB_SPEED_HIGH;
1236 return ehci_submit_root(dev, pipe, buffer, length, setup);
1237 }
1238 return ehci_submit_async(dev, pipe, buffer, length, setup);
1239 }
1240
1241 struct int_queue {
1242 int elementsize;
1243 unsigned long pipe;
1244 struct QH *first;
1245 struct QH *current;
1246 struct QH *last;
1247 struct qTD *tds;
1248 };
1249
1250 #define NEXT_QH(qh) (struct QH *)((unsigned long)hc32_to_cpu((qh)->qh_link) & ~0x1f)
1251
1252 static int
enable_periodic(struct ehci_ctrl * ctrl)1253 enable_periodic(struct ehci_ctrl *ctrl)
1254 {
1255 uint32_t cmd;
1256 struct ehci_hcor *hcor = ctrl->hcor;
1257 int ret;
1258
1259 cmd = ehci_readl(&hcor->or_usbcmd);
1260 cmd |= CMD_PSE;
1261 ehci_writel(&hcor->or_usbcmd, cmd);
1262
1263 ret = handshake((uint32_t *)&hcor->or_usbsts,
1264 STS_PSS, STS_PSS, 100 * 1000);
1265 if (ret < 0) {
1266 printf("EHCI failed: timeout when enabling periodic list\n");
1267 return -ETIMEDOUT;
1268 }
1269 udelay(1000);
1270 return 0;
1271 }
1272
1273 static int
disable_periodic(struct ehci_ctrl * ctrl)1274 disable_periodic(struct ehci_ctrl *ctrl)
1275 {
1276 uint32_t cmd;
1277 struct ehci_hcor *hcor = ctrl->hcor;
1278 int ret;
1279
1280 cmd = ehci_readl(&hcor->or_usbcmd);
1281 cmd &= ~CMD_PSE;
1282 ehci_writel(&hcor->or_usbcmd, cmd);
1283
1284 ret = handshake((uint32_t *)&hcor->or_usbsts,
1285 STS_PSS, 0, 100 * 1000);
1286 if (ret < 0) {
1287 printf("EHCI failed: timeout when disabling periodic list\n");
1288 return -ETIMEDOUT;
1289 }
1290 return 0;
1291 }
1292
_ehci_create_int_queue(struct usb_device * dev,unsigned long pipe,int queuesize,int elementsize,void * buffer,int interval)1293 static struct int_queue *_ehci_create_int_queue(struct usb_device *dev,
1294 unsigned long pipe, int queuesize, int elementsize,
1295 void *buffer, int interval)
1296 {
1297 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1298 struct int_queue *result = NULL;
1299 uint32_t i, toggle;
1300
1301 /*
1302 * Interrupt transfers requiring several transactions are not supported
1303 * because bInterval is ignored.
1304 *
1305 * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
1306 * <= PKT_ALIGN if several qTDs are required, while the USB
1307 * specification does not constrain this for interrupt transfers. That
1308 * means that ehci_submit_async() would support interrupt transfers
1309 * requiring several transactions only as long as the transfer size does
1310 * not require more than a single qTD.
1311 */
1312 if (elementsize > usb_maxpacket(dev, pipe)) {
1313 printf("%s: xfers requiring several transactions are not supported.\n",
1314 __func__);
1315 return NULL;
1316 }
1317
1318 debug("Enter create_int_queue\n");
1319 if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
1320 debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
1321 return NULL;
1322 }
1323
1324 /* limit to 4 full pages worth of data -
1325 * we can safely fit them in a single TD,
1326 * no matter the alignment
1327 */
1328 if (elementsize >= 16384) {
1329 debug("too large elements for interrupt transfers\n");
1330 return NULL;
1331 }
1332
1333 result = malloc(sizeof(*result));
1334 if (!result) {
1335 debug("ehci intr queue: out of memory\n");
1336 goto fail1;
1337 }
1338 result->elementsize = elementsize;
1339 result->pipe = pipe;
1340 result->first = memalign(USB_DMA_MINALIGN,
1341 sizeof(struct QH) * queuesize);
1342 if (!result->first) {
1343 debug("ehci intr queue: out of memory\n");
1344 goto fail2;
1345 }
1346 result->current = result->first;
1347 result->last = result->first + queuesize - 1;
1348 result->tds = memalign(USB_DMA_MINALIGN,
1349 sizeof(struct qTD) * queuesize);
1350 if (!result->tds) {
1351 debug("ehci intr queue: out of memory\n");
1352 goto fail3;
1353 }
1354 memset(result->first, 0, sizeof(struct QH) * queuesize);
1355 memset(result->tds, 0, sizeof(struct qTD) * queuesize);
1356
1357 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
1358
1359 for (i = 0; i < queuesize; i++) {
1360 struct QH *qh = result->first + i;
1361 struct qTD *td = result->tds + i;
1362 void **buf = &qh->buffer;
1363
1364 qh->qh_link = cpu_to_hc32((unsigned long)(qh+1) | QH_LINK_TYPE_QH);
1365 if (i == queuesize - 1)
1366 qh->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
1367
1368 qh->qh_overlay.qt_next = cpu_to_hc32((unsigned long)td);
1369 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1370 qh->qh_endpt1 =
1371 cpu_to_hc32((0 << 28) | /* No NAK reload (ehci 4.9) */
1372 (usb_maxpacket(dev, pipe) << 16) | /* MPS */
1373 (1 << 14) |
1374 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
1375 (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */
1376 (usb_pipedevice(pipe) << 0));
1377 qh->qh_endpt2 = cpu_to_hc32((1 << 30) | /* 1 Tx per mframe */
1378 (1 << 0)); /* S-mask: microframe 0 */
1379 if (dev->speed == USB_SPEED_LOW ||
1380 dev->speed == USB_SPEED_FULL) {
1381 /* C-mask: microframes 2-4 */
1382 qh->qh_endpt2 |= cpu_to_hc32((0x1c << 8));
1383 }
1384 ehci_update_endpt2_dev_n_port(dev, qh);
1385
1386 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1387 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1388 debug("communication direction is '%s'\n",
1389 usb_pipein(pipe) ? "in" : "out");
1390 td->qt_token = cpu_to_hc32(
1391 QT_TOKEN_DT(toggle) |
1392 (elementsize << 16) |
1393 ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */
1394 0x80); /* active */
1395 td->qt_buffer[0] =
1396 cpu_to_hc32((unsigned long)buffer + i * elementsize);
1397 td->qt_buffer[1] =
1398 cpu_to_hc32((td->qt_buffer[0] + 0x1000) & ~0xfff);
1399 td->qt_buffer[2] =
1400 cpu_to_hc32((td->qt_buffer[0] + 0x2000) & ~0xfff);
1401 td->qt_buffer[3] =
1402 cpu_to_hc32((td->qt_buffer[0] + 0x3000) & ~0xfff);
1403 td->qt_buffer[4] =
1404 cpu_to_hc32((td->qt_buffer[0] + 0x4000) & ~0xfff);
1405
1406 *buf = buffer + i * elementsize;
1407 toggle ^= 1;
1408 }
1409
1410 flush_dcache_range((unsigned long)buffer,
1411 ALIGN_END_ADDR(char, buffer,
1412 queuesize * elementsize));
1413 flush_dcache_range((unsigned long)result->first,
1414 ALIGN_END_ADDR(struct QH, result->first,
1415 queuesize));
1416 flush_dcache_range((unsigned long)result->tds,
1417 ALIGN_END_ADDR(struct qTD, result->tds,
1418 queuesize));
1419
1420 if (ctrl->periodic_schedules > 0) {
1421 if (disable_periodic(ctrl) < 0) {
1422 debug("FATAL: periodic should never fail, but did");
1423 goto fail3;
1424 }
1425 }
1426
1427 /* hook up to periodic list */
1428 struct QH *list = &ctrl->periodic_queue;
1429 result->last->qh_link = list->qh_link;
1430 list->qh_link = cpu_to_hc32((unsigned long)result->first | QH_LINK_TYPE_QH);
1431
1432 flush_dcache_range((unsigned long)result->last,
1433 ALIGN_END_ADDR(struct QH, result->last, 1));
1434 flush_dcache_range((unsigned long)list,
1435 ALIGN_END_ADDR(struct QH, list, 1));
1436
1437 if (enable_periodic(ctrl) < 0) {
1438 debug("FATAL: periodic should never fail, but did");
1439 goto fail3;
1440 }
1441 ctrl->periodic_schedules++;
1442
1443 debug("Exit create_int_queue\n");
1444 return result;
1445 fail3:
1446 free(result->tds);
1447 fail2:
1448 free(result->first);
1449 free(result);
1450 fail1:
1451 return NULL;
1452 }
1453
_ehci_poll_int_queue(struct usb_device * dev,struct int_queue * queue)1454 static void *_ehci_poll_int_queue(struct usb_device *dev,
1455 struct int_queue *queue)
1456 {
1457 struct QH *cur = queue->current;
1458 struct qTD *cur_td;
1459 uint32_t token, toggle;
1460 unsigned long pipe = queue->pipe;
1461
1462 /* depleted queue */
1463 if (cur == NULL) {
1464 debug("Exit poll_int_queue with completed queue\n");
1465 return NULL;
1466 }
1467 /* still active */
1468 cur_td = &queue->tds[queue->current - queue->first];
1469 invalidate_dcache_range((unsigned long)cur_td,
1470 ALIGN_END_ADDR(struct qTD, cur_td, 1));
1471 token = hc32_to_cpu(cur_td->qt_token);
1472 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE) {
1473 debug("Exit poll_int_queue with no completed intr transfer. token is %x\n", token);
1474 return NULL;
1475 }
1476
1477 toggle = QT_TOKEN_GET_DT(token);
1478 usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), toggle);
1479
1480 if (!(cur->qh_link & QH_LINK_TERMINATE))
1481 queue->current++;
1482 else
1483 queue->current = NULL;
1484
1485 invalidate_dcache_range((unsigned long)cur->buffer,
1486 ALIGN_END_ADDR(char, cur->buffer,
1487 queue->elementsize));
1488
1489 debug("Exit poll_int_queue with completed intr transfer. token is %x at %p (first at %p)\n",
1490 token, cur, queue->first);
1491 return cur->buffer;
1492 }
1493
1494 /* Do not free buffers associated with QHs, they're owned by someone else */
_ehci_destroy_int_queue(struct usb_device * dev,struct int_queue * queue)1495 static int _ehci_destroy_int_queue(struct usb_device *dev,
1496 struct int_queue *queue)
1497 {
1498 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1499 int result = -1;
1500 unsigned long timeout;
1501
1502 if (disable_periodic(ctrl) < 0) {
1503 debug("FATAL: periodic should never fail, but did");
1504 goto out;
1505 }
1506 ctrl->periodic_schedules--;
1507
1508 struct QH *cur = &ctrl->periodic_queue;
1509 timeout = get_timer(0) + 500; /* abort after 500ms */
1510 while (!(cur->qh_link & cpu_to_hc32(QH_LINK_TERMINATE))) {
1511 debug("considering %p, with qh_link %x\n", cur, cur->qh_link);
1512 if (NEXT_QH(cur) == queue->first) {
1513 debug("found candidate. removing from chain\n");
1514 cur->qh_link = queue->last->qh_link;
1515 flush_dcache_range((unsigned long)cur,
1516 ALIGN_END_ADDR(struct QH, cur, 1));
1517 result = 0;
1518 break;
1519 }
1520 cur = NEXT_QH(cur);
1521 if (get_timer(0) > timeout) {
1522 printf("Timeout destroying interrupt endpoint queue\n");
1523 result = -1;
1524 goto out;
1525 }
1526 }
1527
1528 if (ctrl->periodic_schedules > 0) {
1529 result = enable_periodic(ctrl);
1530 if (result < 0)
1531 debug("FATAL: periodic should never fail, but did");
1532 }
1533
1534 out:
1535 free(queue->tds);
1536 free(queue->first);
1537 free(queue);
1538
1539 return result;
1540 }
1541
_ehci_submit_int_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int length,int interval,bool nonblock)1542 static int _ehci_submit_int_msg(struct usb_device *dev, unsigned long pipe,
1543 void *buffer, int length, int interval,
1544 bool nonblock)
1545 {
1546 void *backbuffer;
1547 struct int_queue *queue;
1548 unsigned long timeout;
1549 int result = 0, ret;
1550
1551 debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
1552 dev, pipe, buffer, length, interval);
1553
1554 queue = _ehci_create_int_queue(dev, pipe, 1, length, buffer, interval);
1555 if (!queue)
1556 return -1;
1557
1558 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1559 while ((backbuffer = _ehci_poll_int_queue(dev, queue)) == NULL)
1560 if (get_timer(0) > timeout) {
1561 printf("Timeout poll on interrupt endpoint\n");
1562 result = -ETIMEDOUT;
1563 break;
1564 }
1565
1566 if (backbuffer != buffer) {
1567 debug("got wrong buffer back (%p instead of %p)\n",
1568 backbuffer, buffer);
1569 return -EINVAL;
1570 }
1571
1572 ret = _ehci_destroy_int_queue(dev, queue);
1573 if (ret < 0)
1574 return ret;
1575
1576 /* everything worked out fine */
1577 return result;
1578 }
1579
_ehci_lock_async(struct ehci_ctrl * ctrl,int lock)1580 static int _ehci_lock_async(struct ehci_ctrl *ctrl, int lock)
1581 {
1582 ctrl->async_locked = lock;
1583
1584 if (lock)
1585 return 0;
1586
1587 return ehci_disable_async(ctrl);
1588 }
1589
1590 #if !CONFIG_IS_ENABLED(DM_USB)
submit_bulk_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int length)1591 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
1592 void *buffer, int length)
1593 {
1594 return _ehci_submit_bulk_msg(dev, pipe, buffer, length);
1595 }
1596
submit_control_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int length,struct devrequest * setup)1597 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1598 int length, struct devrequest *setup)
1599 {
1600 return _ehci_submit_control_msg(dev, pipe, buffer, length, setup);
1601 }
1602
submit_int_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int length,int interval,bool nonblock)1603 int submit_int_msg(struct usb_device *dev, unsigned long pipe,
1604 void *buffer, int length, int interval, bool nonblock)
1605 {
1606 return _ehci_submit_int_msg(dev, pipe, buffer, length, interval,
1607 nonblock);
1608 }
1609
create_int_queue(struct usb_device * dev,unsigned long pipe,int queuesize,int elementsize,void * buffer,int interval)1610 struct int_queue *create_int_queue(struct usb_device *dev,
1611 unsigned long pipe, int queuesize, int elementsize,
1612 void *buffer, int interval)
1613 {
1614 return _ehci_create_int_queue(dev, pipe, queuesize, elementsize,
1615 buffer, interval);
1616 }
1617
poll_int_queue(struct usb_device * dev,struct int_queue * queue)1618 void *poll_int_queue(struct usb_device *dev, struct int_queue *queue)
1619 {
1620 return _ehci_poll_int_queue(dev, queue);
1621 }
1622
destroy_int_queue(struct usb_device * dev,struct int_queue * queue)1623 int destroy_int_queue(struct usb_device *dev, struct int_queue *queue)
1624 {
1625 return _ehci_destroy_int_queue(dev, queue);
1626 }
1627
usb_lock_async(struct usb_device * dev,int lock)1628 int usb_lock_async(struct usb_device *dev, int lock)
1629 {
1630 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1631
1632 return _ehci_lock_async(ctrl, lock);
1633 }
1634 #endif
1635
1636 #if CONFIG_IS_ENABLED(DM_USB)
ehci_submit_control_msg(struct udevice * dev,struct usb_device * udev,unsigned long pipe,void * buffer,int length,struct devrequest * setup)1637 static int ehci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1638 unsigned long pipe, void *buffer, int length,
1639 struct devrequest *setup)
1640 {
1641 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1642 dev->name, udev, udev->dev->name, udev->portnr);
1643
1644 return _ehci_submit_control_msg(udev, pipe, buffer, length, setup);
1645 }
1646
ehci_submit_bulk_msg(struct udevice * dev,struct usb_device * udev,unsigned long pipe,void * buffer,int length)1647 static int ehci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1648 unsigned long pipe, void *buffer, int length)
1649 {
1650 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1651 return _ehci_submit_bulk_msg(udev, pipe, buffer, length);
1652 }
1653
ehci_submit_int_msg(struct udevice * dev,struct usb_device * udev,unsigned long pipe,void * buffer,int length,int interval,bool nonblock)1654 static int ehci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1655 unsigned long pipe, void *buffer, int length,
1656 int interval, bool nonblock)
1657 {
1658 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1659 return _ehci_submit_int_msg(udev, pipe, buffer, length, interval,
1660 nonblock);
1661 }
1662
ehci_create_int_queue(struct udevice * dev,struct usb_device * udev,unsigned long pipe,int queuesize,int elementsize,void * buffer,int interval)1663 static struct int_queue *ehci_create_int_queue(struct udevice *dev,
1664 struct usb_device *udev, unsigned long pipe, int queuesize,
1665 int elementsize, void *buffer, int interval)
1666 {
1667 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1668 return _ehci_create_int_queue(udev, pipe, queuesize, elementsize,
1669 buffer, interval);
1670 }
1671
ehci_poll_int_queue(struct udevice * dev,struct usb_device * udev,struct int_queue * queue)1672 static void *ehci_poll_int_queue(struct udevice *dev, struct usb_device *udev,
1673 struct int_queue *queue)
1674 {
1675 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1676 return _ehci_poll_int_queue(udev, queue);
1677 }
1678
ehci_destroy_int_queue(struct udevice * dev,struct usb_device * udev,struct int_queue * queue)1679 static int ehci_destroy_int_queue(struct udevice *dev, struct usb_device *udev,
1680 struct int_queue *queue)
1681 {
1682 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1683 return _ehci_destroy_int_queue(udev, queue);
1684 }
1685
ehci_get_max_xfer_size(struct udevice * dev,size_t * size)1686 static int ehci_get_max_xfer_size(struct udevice *dev, size_t *size)
1687 {
1688 /*
1689 * EHCD can handle any transfer length as long as there is enough
1690 * free heap space left, hence set the theoretical max number here.
1691 */
1692 *size = SIZE_MAX;
1693
1694 return 0;
1695 }
1696
ehci_lock_async(struct udevice * dev,int lock)1697 static int ehci_lock_async(struct udevice *dev, int lock)
1698 {
1699 struct ehci_ctrl *ctrl = dev_get_priv(dev);
1700
1701 return _ehci_lock_async(ctrl, lock);
1702 }
1703
ehci_register(struct udevice * dev,struct ehci_hccr * hccr,struct ehci_hcor * hcor,const struct ehci_ops * ops,uint tweaks,enum usb_init_type init)1704 int ehci_register(struct udevice *dev, struct ehci_hccr *hccr,
1705 struct ehci_hcor *hcor, const struct ehci_ops *ops,
1706 uint tweaks, enum usb_init_type init)
1707 {
1708 struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
1709 struct ehci_ctrl *ctrl = dev_get_priv(dev);
1710 int ret = -1;
1711
1712 debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p, init=%d\n", __func__,
1713 dev->name, ctrl, hccr, hcor, init);
1714
1715 if (!ctrl || !hccr || !hcor)
1716 goto err;
1717
1718 priv->desc_before_addr = true;
1719
1720 ehci_setup_ops(ctrl, ops);
1721 ctrl->hccr = hccr;
1722 ctrl->hcor = hcor;
1723 ctrl->priv = ctrl;
1724
1725 ctrl->init = init;
1726 if (ctrl->init == USB_INIT_DEVICE)
1727 goto done;
1728
1729 ret = ehci_reset(ctrl);
1730 if (ret)
1731 goto err;
1732
1733 if (ctrl->ops.init_after_reset) {
1734 ret = ctrl->ops.init_after_reset(ctrl);
1735 if (ret)
1736 goto err;
1737 }
1738
1739 ret = ehci_common_init(ctrl, tweaks);
1740 if (ret)
1741 goto err;
1742 done:
1743 return 0;
1744 err:
1745 free(ctrl);
1746 debug("%s: failed, ret=%d\n", __func__, ret);
1747 return ret;
1748 }
1749
ehci_deregister(struct udevice * dev)1750 int ehci_deregister(struct udevice *dev)
1751 {
1752 struct ehci_ctrl *ctrl = dev_get_priv(dev);
1753
1754 if (ctrl->init == USB_INIT_DEVICE)
1755 return 0;
1756
1757 ehci_shutdown(ctrl);
1758
1759 return 0;
1760 }
1761
1762 struct dm_usb_ops ehci_usb_ops = {
1763 .control = ehci_submit_control_msg,
1764 .bulk = ehci_submit_bulk_msg,
1765 .interrupt = ehci_submit_int_msg,
1766 .create_int_queue = ehci_create_int_queue,
1767 .poll_int_queue = ehci_poll_int_queue,
1768 .destroy_int_queue = ehci_destroy_int_queue,
1769 .get_max_xfer_size = ehci_get_max_xfer_size,
1770 .lock_async = ehci_lock_async,
1771 };
1772
1773 #endif
1774
1775 #ifdef CONFIG_PHY
ehci_setup_phy(struct udevice * dev,struct phy * phy,int index)1776 int ehci_setup_phy(struct udevice *dev, struct phy *phy, int index)
1777 {
1778 int ret;
1779
1780 if (!phy)
1781 return 0;
1782
1783 ret = generic_phy_get_by_index(dev, index, phy);
1784 if (ret) {
1785 if (ret != -ENOENT) {
1786 dev_err(dev, "failed to get usb phy\n");
1787 return ret;
1788 }
1789 } else {
1790 ret = generic_phy_init(phy);
1791 if (ret) {
1792 dev_dbg(dev, "failed to init usb phy\n");
1793 return ret;
1794 }
1795
1796 ret = generic_phy_power_on(phy);
1797 if (ret) {
1798 dev_dbg(dev, "failed to power on usb phy\n");
1799 return generic_phy_exit(phy);
1800 }
1801 }
1802
1803 return 0;
1804 }
1805
ehci_shutdown_phy(struct udevice * dev,struct phy * phy)1806 int ehci_shutdown_phy(struct udevice *dev, struct phy *phy)
1807 {
1808 int ret = 0;
1809
1810 if (!phy)
1811 return 0;
1812
1813 if (generic_phy_valid(phy)) {
1814 ret = generic_phy_power_off(phy);
1815 if (ret) {
1816 dev_dbg(dev, "failed to power off usb phy\n");
1817 return ret;
1818 }
1819
1820 ret = generic_phy_exit(phy);
1821 if (ret) {
1822 dev_dbg(dev, "failed to power off usb phy\n");
1823 return ret;
1824 }
1825 }
1826
1827 return 0;
1828 }
1829 #else
ehci_setup_phy(struct udevice * dev,struct phy * phy,int index)1830 int ehci_setup_phy(struct udevice *dev, struct phy *phy, int index)
1831 {
1832 return 0;
1833 }
1834
ehci_shutdown_phy(struct udevice * dev,struct phy * phy)1835 int ehci_shutdown_phy(struct udevice *dev, struct phy *phy)
1836 {
1837 return 0;
1838 }
1839 #endif
1840