1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2019 NXP
4 * Copyright 2020 Linaro
5 */
6
7 #include <common.h>
8 #include <command.h>
9 #include <cpu_func.h>
10 #include <hang.h>
11 #include <image.h>
12 #include <init.h>
13 #include <log.h>
14 #include <spl.h>
15 #include <asm/io.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/imx8mm_pins.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/mach-imx/boot_mode.h>
21 #include <asm/mach-imx/mxc_i2c.h>
22 #include <asm/mach-imx/gpio.h>
23 #include <asm/arch/ddr.h>
24
25 #include <dm/uclass.h>
26 #include <dm/device.h>
27 #include <dm/uclass-internal.h>
28 #include <dm/device-internal.h>
29
30 #include <power/pmic.h>
31 #include <power/bd71837.h>
32
33 #include "ddr/ddr.h"
34
35 DECLARE_GLOBAL_DATA_PTR;
36
spl_board_boot_device(enum boot_device boot_dev_spl)37 int spl_board_boot_device(enum boot_device boot_dev_spl)
38 {
39 switch (boot_dev_spl) {
40 case SD2_BOOT:
41 case MMC2_BOOT:
42 return BOOT_DEVICE_MMC1;
43 case SD3_BOOT:
44 case MMC3_BOOT:
45 return BOOT_DEVICE_MMC2;
46 default:
47 return BOOT_DEVICE_NONE;
48 }
49 }
50
51 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
52 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
53 struct i2c_pads_info i2c_pad_info1 = {
54 .scl = {
55 .i2c_mode = IMX8MM_PAD_I2C2_SCL_I2C2_SCL | PC,
56 .gpio_mode = IMX8MM_PAD_I2C2_SCL_GPIO5_IO16 | PC,
57 .gp = IMX_GPIO_NR(5, 16),
58 },
59 .sda = {
60 .i2c_mode = IMX8MM_PAD_I2C2_SDA_I2C2_SDA | PC,
61 .gpio_mode = IMX8MM_PAD_I2C2_SDA_GPIO5_IO17 | PC,
62 .gp = IMX_GPIO_NR(5, 17),
63 },
64 };
65
spl_dram_init(void)66 static void spl_dram_init(void)
67 {
68 spl_dram_init_compulab();
69 }
70
spl_board_init(void)71 void spl_board_init(void)
72 {
73 puts("Normal Boot\n");
74 }
75
76 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)77 int board_fit_config_name_match(const char *name)
78 {
79 /* Just empty function now - can't decide what to choose */
80 debug("%s: %s\n", __func__, name);
81
82 return 0;
83 }
84 #endif
85
86 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
87 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
88
89 static iomux_v3_cfg_t const uart_pads[] = {
90 IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
91 IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
92 };
93
94 static iomux_v3_cfg_t const wdog_pads[] = {
95 IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
96 };
97
board_early_init_f(void)98 int board_early_init_f(void)
99 {
100 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
101
102 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
103
104 set_wdog_reset(wdog);
105
106 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
107
108 return 0;
109 }
110
power_init_board(void)111 static int power_init_board(void)
112 {
113 struct udevice *dev;
114 int ret;
115
116 ret = pmic_get("pmic@4b", &dev);
117 if (ret == -ENODEV) {
118 puts("No pmic\n");
119 return 0;
120 }
121 if (ret != 0)
122 return ret;
123
124 /* decrease RESET key long push time from the default 10s to 10ms */
125 pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
126
127 /* unlock the PMIC regs */
128 pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
129
130 /* increase VDD_SOC to typical value 0.85v before first DRAM access */
131 pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
132
133 /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
134 pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
135
136 /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
137 pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
138
139 /* lock the PMIC regs */
140 pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
141
142 return 0;
143 }
144
board_init_f(ulong dummy)145 void board_init_f(ulong dummy)
146 {
147 struct udevice *dev;
148 int ret;
149
150 arch_cpu_init();
151
152 board_early_init_f();
153
154 init_uart_clk(2);
155
156 timer_init();
157
158 preloader_console_init();
159
160 /* Clear the BSS. */
161 memset(__bss_start, 0, __bss_end - __bss_start);
162
163 ret = spl_early_init();
164 if (ret) {
165 debug("spl_early_init() failed: %d\n", ret);
166 hang();
167 }
168
169 ret = uclass_get_device_by_name(UCLASS_CLK,
170 "clock-controller@30380000",
171 &dev);
172 if (ret < 0) {
173 printf("Failed to find clock node. Check device tree\n");
174 hang();
175 }
176
177 enable_tzc380();
178
179 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
180
181 power_init_board();
182
183 /* DDR initialization */
184 spl_dram_init();
185
186 board_init_r(NULL, 0);
187 }
188