1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Configuation settings for the Freescale MCF54451 EVB board.
4  *
5  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7  */
8 
9 /*
10  * board/config.h - configuration options, board specific
11  */
12 
13 #ifndef _M54451EVB_H
14 #define _M54451EVB_H
15 
16 #include <linux/stringify.h>
17 
18 /*
19  * High Level Configuration Options
20  * (easy to change)
21  */
22 #define CONFIG_M54451EVB	/* M54451EVB board */
23 
24 #define CONFIG_MCFUART
25 #define CONFIG_SYS_UART_PORT		(0)
26 
27 #define LDS_BOARD_TEXT                  board/freescale/m54451evb/sbf_dram_init.o (.text*)
28 
29 #undef CONFIG_WATCHDOG
30 
31 #define CONFIG_TIMESTAMP	/* Print image info with timestamp */
32 
33 /*
34  * BOOTP options
35  */
36 #define CONFIG_BOOTP_BOOTFILESIZE
37 
38 /* Network configuration */
39 #ifdef CONFIG_MCFFEC
40 #	define CONFIG_MII_INIT		1
41 #	define CONFIG_SYS_DISCOVER_PHY
42 #	define CONFIG_SYS_RX_ETH_BUFFER	8
43 #	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
44 #	define CONFIG_ETHPRIME		"FEC0"
45 #	define CONFIG_IPADDR		192.162.1.2
46 #	define CONFIG_NETMASK		255.255.255.0
47 #	define CONFIG_SERVERIP		192.162.1.1
48 #	define CONFIG_GATEWAYIP		192.162.1.1
49 
50 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
51 #	ifndef CONFIG_SYS_DISCOVER_PHY
52 #		define FECDUPLEX	FULL
53 #		define FECSPEED		_100BASET
54 #	else
55 #		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
56 #			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
57 #		endif
58 #	endif			/* CONFIG_SYS_DISCOVER_PHY */
59 #endif
60 
61 #define CONFIG_HOSTNAME		"M54451EVB"
62 #ifdef CONFIG_SYS_STMICRO_BOOT
63 /* ST Micro serial flash */
64 #define	CONFIG_SYS_LOAD_ADDR2		0x40010007
65 #define CONFIG_EXTRA_ENV_SETTINGS		\
66 	"netdev=eth0\0"				\
67 	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
68 	"loadaddr=0x40010000\0"			\
69 	"sbfhdr=sbfhdr.bin\0"			\
70 	"uboot=u-boot.bin\0"			\
71 	"load=tftp ${loadaddr} ${sbfhdr};"	\
72 	"tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"	\
73 	"upd=run load; run prog\0"		\
74 	"prog=sf probe 0:1 1000000 3;"		\
75 	"sf erase 0 30000;"			\
76 	"sf write ${loadaddr} 0 30000;"		\
77 	"save\0"				\
78 	""
79 #else
80 #define CONFIG_SYS_UBOOT_END	0x3FFFF
81 #define CONFIG_EXTRA_ENV_SETTINGS		\
82 	"netdev=eth0\0"				\
83 	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
84 	"loadaddr=40010000\0"			\
85 	"u-boot=u-boot.bin\0"			\
86 	"load=tftp ${loadaddr) ${u-boot}\0"	\
87 	"upd=run load; run prog\0"		\
88 	"prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END)	\
89 	"; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;"	\
90 	"cp.b ${loadaddr} 0 ${filesize};"	\
91 	"save\0"				\
92 	""
93 #endif
94 
95 /* Realtime clock */
96 #define CONFIG_MCFRTC
97 #undef RTC_DEBUG
98 #define CONFIG_SYS_RTC_OSCILLATOR	(32 * CONFIG_SYS_HZ)
99 
100 /* Timer */
101 #define CONFIG_MCFTMR
102 
103 /* I2c */
104 #define CONFIG_SYS_I2C
105 #define CONFIG_SYS_I2C_FSL
106 #define CONFIG_SYS_FSL_I2C_SPEED	80000
107 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
108 #define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
109 #define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR
110 
111 /* DSPI and Serial Flash */
112 #define CONFIG_CF_DSPI
113 #define CONFIG_SERIAL_FLASH
114 #define CONFIG_SYS_SBFHDR_SIZE		0x7
115 
116 /* Input, PCI, Flexbus, and VCO */
117 #define CONFIG_EXTRA_CLOCK
118 
119 #define CONFIG_PRAM			2048	/* 2048 KB */
120 
121 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
122 
123 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x10000)
124 
125 #define CONFIG_SYS_MBAR			0xFC000000
126 
127 /*
128  * Low Level Configuration Settings
129  * (address mappings, register initial values, etc.)
130  * You should know what you are doing if you make changes here.
131  */
132 
133 /*-----------------------------------------------------------------------
134  * Definitions for initial stack pointer and data area (in DPRAM)
135  */
136 #define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
137 #define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* Size of used area in internal SRAM */
138 #define CONFIG_SYS_INIT_RAM_CTRL	0x221
139 #define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
140 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
141 #define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)
142 
143 /*-----------------------------------------------------------------------
144  * Start addresses for the final memory configuration
145  * (Set up by the startup code)
146  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
147  */
148 #define CONFIG_SYS_SDRAM_BASE		0x40000000
149 #define CONFIG_SYS_SDRAM_SIZE		128	/* SDRAM size in MB */
150 #define CONFIG_SYS_SDRAM_CFG1		0x33633F30
151 #define CONFIG_SYS_SDRAM_CFG2		0x57670000
152 #define CONFIG_SYS_SDRAM_CTRL		0xE20D2C00
153 #define CONFIG_SYS_SDRAM_EMOD		0x80810000
154 #define CONFIG_SYS_SDRAM_MODE		0x008D0000
155 #define CONFIG_SYS_SDRAM_DRV_STRENGTH	0x44
156 
157 #ifdef CONFIG_CF_SBF
158 #	define CONFIG_SERIAL_BOOT
159 #	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE + 0x400)
160 #else
161 #	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
162 #endif
163 #define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
164 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
165 
166 /* Reserve 256 kB for malloc() */
167 #define CONFIG_SYS_MALLOC_LEN		(256 << 10)
168 /*
169  * For booting Linux, the board info and command line data
170  * have to be in the first 8 MB of memory, since this is
171  * the maximum mapped by the Linux kernel during initialization ??
172  */
173 /* Initial Memory map for Linux */
174 #define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
175 
176 /* Configuration for environment
177  * Environment is not embedded in u-boot. First time runing may have env
178  * crc error warning if there is no correct environment on the flash.
179  */
180 
181 /* FLASH organization */
182 #define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
183 
184 #ifdef CONFIG_SYS_FLASH_CFI
185 
186 #	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
187 #	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
188 #	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
189 #	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
190 #	define CONFIG_SYS_FLASH_CHECKSUM
191 #	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE }
192 
193 #endif
194 
195 /*
196  * This is setting for JFFS2 support in u-boot.
197  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
198  */
199 #ifdef CONFIG_CMD_JFFS2
200 #	define CONFIG_JFFS2_DEV		"nor0"
201 #	define CONFIG_JFFS2_PART_SIZE	0x01000000
202 #	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH0_BASE + 0x500000)
203 #endif
204 
205 /* Cache Configuration */
206 #define CONFIG_SYS_CACHELINE_SIZE		16
207 
208 #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
209 					 CONFIG_SYS_INIT_RAM_SIZE - 8)
210 #define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
211 					 CONFIG_SYS_INIT_RAM_SIZE - 4)
212 #define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
213 #define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
214 #define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
215 					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
216 					 CF_ACR_EN | CF_ACR_SM_ALL)
217 #define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_IEC | \
218 					 CF_CACR_ICINVA | CF_CACR_EUSP)
219 #define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
220 					 CF_CACR_DEC | CF_CACR_DDCM_P | \
221 					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
222 
223 /*-----------------------------------------------------------------------
224  * Memory bank definitions
225  */
226 /*
227  * CS0 - NOR Flash 16MB
228  * CS1 - Available
229  * CS2 - Available
230  * CS3 - Available
231  * CS4 - Available
232  * CS5 - Available
233  */
234 
235  /* Flash */
236 #define CONFIG_SYS_CS0_BASE		0x00000000
237 #define CONFIG_SYS_CS0_MASK		0x00FF0001
238 #define CONFIG_SYS_CS0_CTRL		0x00004D80
239 
240 #define CONFIG_SYS_SPANSION_BASE	CONFIG_SYS_CS0_BASE
241 
242 #endif				/* _M54451EVB_H */
243