1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Config file for Compulab CM-T335 board 4 * 5 * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/ 6 * 7 * Author: Ilya Ledvich <ilya@compulab.co.il> 8 */ 9 10 #ifndef __CONFIG_CM_T335_H 11 #define __CONFIG_CM_T335_H 12 13 #define CONFIG_CM_T335 14 15 #include <configs/ti_am335x_common.h> 16 17 #undef CONFIG_MAX_RAM_BANK_SIZE 18 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 512MB */ 19 20 #define CONFIG_MACH_TYPE MACH_TYPE_CM_T335 21 22 /* Clock Defines */ 23 #define V_OSCK 25000000 /* Clock output from T2 */ 24 #define V_SCLK (V_OSCK) 25 26 #ifndef CONFIG_SPL_BUILD 27 #define MMCARGS \ 28 "mmcdev=0\0" \ 29 "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ 30 "mmcrootfstype=ext4\0" \ 31 "mmcargs=setenv bootargs console=${console} " \ 32 "root=${mmcroot} " \ 33 "rootfstype=${mmcrootfstype}\0" \ 34 "mmcboot=echo Booting from mmc ...; " \ 35 "run mmcargs; " \ 36 "bootm ${loadaddr}\0" 37 38 #define NANDARGS \ 39 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ 40 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 41 "nandroot=ubi0:rootfs rw\0" \ 42 "nandrootfstype=ubifs\0" \ 43 "nandargs=setenv bootargs console=${console} " \ 44 "root=${nandroot} " \ 45 "rootfstype=${nandrootfstype} " \ 46 "ubi.mtd=${rootfs_name}\0" \ 47 "nandboot=echo Booting from nand ...; " \ 48 "run nandargs; " \ 49 "nboot ${loadaddr} nand0 900000; " \ 50 "bootm ${loadaddr}\0" 51 52 #define CONFIG_EXTRA_ENV_SETTINGS \ 53 "loadaddr=82000000\0" \ 54 "console=ttyO0,115200n8\0" \ 55 "rootfs_name=rootfs\0" \ 56 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 57 "bootscript=echo Running bootscript from mmc ...; " \ 58 "source ${loadaddr}\0" \ 59 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 60 MMCARGS \ 61 NANDARGS 62 63 #define CONFIG_BOOTCOMMAND \ 64 "mmc dev ${mmcdev}; if mmc rescan; then " \ 65 "if run loadbootscript; then " \ 66 "run bootscript; " \ 67 "else " \ 68 "if run loaduimage; then " \ 69 "run mmcboot; " \ 70 "else run nandboot; " \ 71 "fi; " \ 72 "fi; " \ 73 "else run nandboot; fi" 74 #endif /* CONFIG_SPL_BUILD */ 75 76 #define CONFIG_TIMESTAMP 77 #define CONFIG_SYS_AUTOLOAD "no" 78 79 /* Serial console configuration */ 80 81 /* NS16550 Configuration */ 82 #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ 83 #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ 84 85 /* I2C Configuration */ 86 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ 87 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 88 #define CONFIG_SYS_I2C_EEPROM_BUS 0 89 90 /* SPL */ 91 92 /* Network. */ 93 94 /* NAND support */ 95 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 96 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ 97 CONFIG_SYS_NAND_PAGE_SIZE) 98 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 99 #define CONFIG_SYS_NAND_OOBSIZE 64 100 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 101 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 102 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 103 10, 11, 12, 13, 14, 15, 16, 17, \ 104 18, 19, 20, 21, 22, 23, 24, 25, \ 105 26, 27, 28, 29, 30, 31, 32, 33, \ 106 34, 35, 36, 37, 38, 39, 40, 41, \ 107 42, 43, 44, 45, 46, 47, 48, 49, \ 108 50, 51, 52, 53, 54, 55, 56, 57, } 109 110 #define CONFIG_SYS_NAND_ECCSIZE 512 111 #define CONFIG_SYS_NAND_ECCBYTES 14 112 113 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 114 115 #undef CONFIG_SYS_NAND_U_BOOT_OFFS 116 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 117 118 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 119 #define CONFIG_SYS_NAND_ONFI_DETECTION 120 #ifdef CONFIG_SPL_OS_BOOT 121 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x500000 122 #endif 123 124 /* GPIO pin + bank to pin ID mapping */ 125 #define GPIO_PIN(_bank, _pin) ((_bank << 5) + _pin) 126 127 /* Status LED */ 128 /* Status LED polarity is inversed, so init it in the "off" state */ 129 130 /* EEPROM */ 131 #define CONFIG_ENV_EEPROM_IS_ON_I2C 132 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 133 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 134 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 135 #define CONFIG_SYS_EEPROM_SIZE 256 136 137 #ifndef CONFIG_SPL_BUILD 138 /* 139 * Enable PCA9555 at I2C0-0x26. 140 * First select the I2C0 bus with "i2c dev 0", then use "pca953x" command. 141 */ 142 #define CONFIG_PCA953X 143 #define CONFIG_SYS_I2C_PCA953X_ADDR 0x26 144 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x26, 16} } 145 #endif /* CONFIG_SPL_BUILD */ 146 147 #endif /* __CONFIG_CM_T335_H */ 148 149