1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef __CONFIG_RK3308_COMMON_H 7 #define __CONFIG_RK3308_COMMON_H 8 9 #include "rockchip-common.h" 10 11 #define CONFIG_SYS_CBSIZE 1024 12 #define CONFIG_SKIP_LOWLEVEL_INIT 13 #define CONFIG_SYS_MAX_NAND_DEVICE 1 14 #define CONFIG_SYS_NAND_ONFI_DETECTION 15 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 16 #define CONFIG_SYS_NAND_PAGE_COUNT 64 17 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 18 #define CONFIG_SPL_MAX_SIZE 0x20000 19 #define CONFIG_SPL_BSS_START_ADDR 0x00400000 20 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 21 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 22 23 #define CONFIG_SYS_NS16550_MEM32 24 25 #define CONFIG_ROCKCHIP_STIMER_BASE 0xff1b00a0 26 #define CONFIG_IRAM_BASE 0xfff80000 27 #define CONFIG_SYS_INIT_SP_ADDR 0x00800000 28 #define CONFIG_SYS_LOAD_ADDR 0x00C00800 29 #define CONFIG_SPL_STACK 0x00400000 30 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 31 32 #define COUNTER_FREQUENCY 24000000 33 34 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 35 36 #define CONFIG_SYS_SDRAM_BASE 0 37 #define SDRAM_MAX_SIZE 0xff000000 38 #define SDRAM_BANK_SIZE (2UL << 30) 39 40 #ifndef CONFIG_SPL_BUILD 41 42 #define ENV_MEM_LAYOUT_SETTINGS \ 43 "scriptaddr=0x00500000\0" \ 44 "pxefile_addr_r=0x00600000\0" \ 45 "fdt_addr_r=0x02800000\0" \ 46 "kernel_addr_r=0x00680000\0" \ 47 "ramdisk_addr_r=0x04000000\0" 48 49 #include <config_distro_bootcmd.h> 50 #define CONFIG_EXTRA_ENV_SETTINGS \ 51 ENV_MEM_LAYOUT_SETTINGS \ 52 "partitions=" PARTS_DEFAULT \ 53 ROCKCHIP_DEVICE_SETTINGS \ 54 BOOTENV 55 56 #endif 57 58 #endif 59