1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2020 NXP 4 */ 5 6 #ifndef __LX2160_H 7 #define __LX2160_H 8 9 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) 10 /* SYSCLK */ 11 #define QIXIS_SYSCLK_100 0x0 12 #define QIXIS_SYSCLK_125 0x1 13 #define QIXIS_SYSCLK_133 0x2 14 15 /* DDRCLK */ 16 #define QIXIS_DDRCLK_100 0x0 17 #define QIXIS_DDRCLK_125 0x1 18 #define QIXIS_DDRCLK_133 0x2 19 20 #define BRDCFG4_EMI1SEL_MASK 0xF8 21 #define BRDCFG4_EMI1SEL_SHIFT 3 22 #define BRDCFG4_EMI2SEL_MASK 0x07 23 #define BRDCFG4_EMI2SEL_SHIFT 0 24 #endif 25 26 #define QIXIS_XMAP_SHIFT 5 27 28 /* RTC */ 29 #define I2C_MUX_CH_RTC 0xB 30 31 /* MAC/PHY configuration */ 32 #if defined(CONFIG_FSL_MC_ENET) 33 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) 34 #define AQ_PHY_ADDR1 0x00 35 #define AQ_PHY_ADDR2 0x01 36 #define AQ_PHY_ADDR3 0x02 37 #define AQ_PHY_ADDR4 0x03 38 #endif 39 40 #ifdef CONFIG_TARGET_LX2160ARDB 41 #define AQR107_PHY_ADDR1 0x04 42 #define AQR107_PHY_ADDR2 0x05 43 #define AQR107_IRQ_MASK 0x0C 44 #endif 45 46 #define CORTINA_PHY_ADDR1 0x0 47 #define INPHI_PHY_ADDR1 0x0 48 49 #define RGMII_PHY_ADDR1 0x01 50 #define RGMII_PHY_ADDR2 0x02 51 52 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) 53 #define INPHI_PHY_ADDR2 0x1 54 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 55 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 56 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 57 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 58 #endif 59 #endif 60 61 #endif /* __LX2160_H */ 62