1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2011 Freescale Semiconductor, Inc. 4 * Copyright 2019 NXP 5 * Author: Tang Yuantian <b29983@freescale.com> 6 */ 7 8 #ifndef SATA_SIL3132_H 9 #define SATA_SIL3132_H 10 11 #define READ_CMD 0 12 #define WRITE_CMD 1 13 14 /* 15 * SATA device driver struct for each dev 16 */ 17 struct sil_sata { 18 char name[12]; 19 void *port; /* the port base address */ 20 int lba48; 21 u16 pio; 22 u16 mwdma; 23 u16 udma; 24 #ifdef CONFIG_DM_PCI 25 struct udevice *devno; 26 #else 27 pci_dev_t devno; 28 #endif 29 int wcache; 30 int flush; 31 int flush_ext; 32 int id; 33 }; 34 35 /* sata info for each controller */ 36 struct sata_info { 37 ulong iobase[3]; 38 pci_dev_t devno; 39 int portbase; 40 int maxport; 41 }; 42 43 /* 44 * Scatter gather entry (SGE),MUST 8 bytes aligned 45 */ 46 struct sil_sge { 47 __le64 addr; 48 __le32 cnt; 49 __le32 flags; 50 } __attribute__ ((aligned(8), packed)); 51 52 /* 53 * Port request block, MUST 8 bytes aligned 54 */ 55 struct sil_prb { 56 __le16 ctrl; 57 __le16 prot; 58 __le32 rx_cnt; 59 struct sata_fis_h2d fis; 60 } __attribute__ ((aligned(8), packed)); 61 62 struct sil_cmd_block { 63 struct sil_prb prb; 64 struct sil_sge sge; 65 }; 66 67 enum { 68 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */ 69 HOST_CTRL = 0x40, 70 HOST_IRQ_STAT = 0x44, 71 HOST_PHY_CFG = 0x48, 72 HOST_BIST_CTRL = 0x50, 73 HOST_BIST_PTRN = 0x54, 74 HOST_BIST_STAT = 0x58, 75 HOST_MEM_BIST_STAT = 0x5c, 76 HOST_FLASH_CMD = 0x70, 77 /* 8 bit regs */ 78 HOST_FLASH_DATA = 0x74, 79 HOST_TRANSITION_DETECT = 0x75, 80 HOST_GPIO_CTRL = 0x76, 81 HOST_I2C_ADDR = 0x78, /* 32 bit */ 82 HOST_I2C_DATA = 0x7c, 83 HOST_I2C_XFER_CNT = 0x7e, 84 HOST_I2C_CTRL = 0x7f, 85 86 /* HOST_SLOT_STAT bits */ 87 HOST_SSTAT_ATTN = (1 << 31), 88 89 /* HOST_CTRL bits */ 90 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */ 91 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */ 92 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */ 93 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */ 94 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */ 95 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */ 96 97 /* 98 * Port registers 99 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2) 100 */ 101 PORT_REGS_SIZE = 0x2000, 102 103 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */ 104 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */ 105 106 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */ 107 PORT_PMP_STATUS = 0x0000, /* port device status offset */ 108 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */ 109 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */ 110 111 /* 32 bit regs */ 112 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */ 113 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */ 114 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */ 115 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */ 116 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */ 117 PORT_ACTIVATE_UPPER_ADDR = 0x101c, 118 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */ 119 PORT_CMD_ERR = 0x1024, /* command error number */ 120 PORT_FIS_CFG = 0x1028, 121 PORT_FIFO_THRES = 0x102c, 122 123 /* 16 bit regs */ 124 PORT_DECODE_ERR_CNT = 0x1040, 125 PORT_DECODE_ERR_THRESH = 0x1042, 126 PORT_CRC_ERR_CNT = 0x1044, 127 PORT_CRC_ERR_THRESH = 0x1046, 128 PORT_HSHK_ERR_CNT = 0x1048, 129 PORT_HSHK_ERR_THRESH = 0x104a, 130 131 /* 32 bit regs */ 132 PORT_PHY_CFG = 0x1050, 133 PORT_SLOT_STAT = 0x1800, 134 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 */ 135 PORT_CONTEXT = 0x1e04, 136 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 */ 137 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 */ 138 PORT_SCONTROL = 0x1f00, 139 PORT_SSTATUS = 0x1f04, 140 PORT_SERROR = 0x1f08, 141 PORT_SACTIVE = 0x1f0c, 142 143 /* PORT_CTRL_STAT bits */ 144 PORT_CS_PORT_RST = (1 << 0), /* port reset */ 145 PORT_CS_DEV_RST = (1 << 1), /* device reset */ 146 PORT_CS_INIT = (1 << 2), /* port initialize */ 147 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */ 148 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */ 149 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */ 150 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */ 151 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */ 152 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */ 153 154 /* PORT_IRQ_STAT/ENABLE_SET/CLR */ 155 /* bits[11:0] are masked */ 156 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */ 157 PORT_IRQ_ERROR = (1 << 1), /* command execution error */ 158 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */ 159 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */ 160 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */ 161 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */ 162 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */ 163 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */ 164 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */ 165 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */ 166 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */ 167 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */ 168 169 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | 170 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG | 171 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY, 172 173 /* bits[27:16] are unmasked (raw) */ 174 PORT_IRQ_RAW_SHIFT = 16, 175 PORT_IRQ_MASKED_MASK = 0x7ff, 176 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT), 177 178 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */ 179 PORT_IRQ_STEER_SHIFT = 30, 180 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT), 181 182 /* PORT_CMD_ERR constants */ 183 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */ 184 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */ 185 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */ 186 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */ 187 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */ 188 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */ 189 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */ 190 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */ 191 192 /* bits of PRB control field */ 193 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */ 194 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */ 195 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */ 196 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */ 197 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */ 198 199 /* PRB protocol field */ 200 PRB_PROT_PACKET = (1 << 0), 201 PRB_PROT_TCQ = (1 << 1), 202 PRB_PROT_NCQ = (1 << 2), 203 PRB_PROT_READ = (1 << 3), 204 PRB_PROT_WRITE = (1 << 4), 205 PRB_PROT_TRANSPARENT = (1 << 5), 206 207 /* 208 * Other constants 209 */ 210 SGE_TRM = (1 << 31), /* Last SGE in chain */ 211 SGE_LNK = (1 << 30), /* linked list 212 Points to SGT, not SGE */ 213 SGE_DRD = (1 << 29), /* discard data read (/dev/null) 214 data address ignored */ 215 216 CMD_ERR = 0x21, 217 }; 218 219 #if CONFIG_IS_ENABLED(BLK) 220 #define ATA_MAX_PORTS 32 221 struct sil_sata_priv { 222 int port_num; 223 struct sil_sata *sil_sata_desc[ATA_MAX_PORTS]; 224 }; 225 #endif 226 227 #endif 228