1 /*
2 * Synopsys HSDK SDP Generic PLL clock driver
3 *
4 * Copyright (C) 2017 Synopsys
5 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12 #include <log.h>
13 #include <asm-generic/gpio.h>
14 #include <asm/io.h>
15 #include <common.h>
16 #include <dm.h>
17 #include <errno.h>
18 #include <linux/bitops.h>
19 #include <linux/printk.h>
20
21 #define DRV_NAME "gpio_creg"
22
23 struct hsdk_creg_gpio {
24 u32 *regs;
25 u8 shift;
26 u8 activate;
27 u8 deactivate;
28 u8 bit_per_gpio;
29 };
30
hsdk_creg_gpio_set_value(struct udevice * dev,unsigned oft,int val)31 static int hsdk_creg_gpio_set_value(struct udevice *dev, unsigned oft, int val)
32 {
33 struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
34 u8 reg_shift = oft * hcg->bit_per_gpio + hcg->shift;
35 u32 reg = readl(hcg->regs);
36
37 reg &= ~(GENMASK(hcg->bit_per_gpio - 1, 0) << reg_shift);
38 reg |= ((val ? hcg->deactivate : hcg->activate) << reg_shift);
39
40 writel(reg, hcg->regs);
41
42 return 0;
43 }
44
hsdk_creg_gpio_direction_output(struct udevice * dev,unsigned oft,int val)45 static int hsdk_creg_gpio_direction_output(struct udevice *dev, unsigned oft,
46 int val)
47 {
48 hsdk_creg_gpio_set_value(dev, oft, val);
49
50 return 0;
51 }
52
hsdk_creg_gpio_direction_input(struct udevice * dev,unsigned oft)53 static int hsdk_creg_gpio_direction_input(struct udevice *dev, unsigned oft)
54 {
55 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
56
57 pr_err("%s can't be used as input!\n", uc_priv->bank_name);
58
59 return -ENOTSUPP;
60 }
61
hsdk_creg_gpio_get_value(struct udevice * dev,unsigned int oft)62 static int hsdk_creg_gpio_get_value(struct udevice *dev, unsigned int oft)
63 {
64 struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
65 u32 val = readl(hcg->regs);
66
67 val >>= oft * hcg->bit_per_gpio + hcg->shift;
68 val &= GENMASK(hcg->bit_per_gpio - 1, 0);
69 return (val == hcg->deactivate) ? 1 : 0;
70 }
71
72 static const struct dm_gpio_ops hsdk_creg_gpio_ops = {
73 .direction_output = hsdk_creg_gpio_direction_output,
74 .direction_input = hsdk_creg_gpio_direction_input,
75 .set_value = hsdk_creg_gpio_set_value,
76 .get_value = hsdk_creg_gpio_get_value,
77 };
78
hsdk_creg_gpio_probe(struct udevice * dev)79 static int hsdk_creg_gpio_probe(struct udevice *dev)
80 {
81 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
82 struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
83 u32 shift, bit_per_gpio, activate, deactivate, gpio_count;
84 const u8 *defaults;
85
86 hcg->regs = dev_read_addr_ptr(dev);
87 gpio_count = dev_read_u32_default(dev, "gpio-count", 1);
88 shift = dev_read_u32_default(dev, "gpio-first-shift", 0);
89 bit_per_gpio = dev_read_u32_default(dev, "gpio-bit-per-line", 1);
90 activate = dev_read_u32_default(dev, "gpio-activate-val", 1);
91 deactivate = dev_read_u32_default(dev, "gpio-deactivate-val", 0);
92 defaults = dev_read_u8_array_ptr(dev, "gpio-default-val", gpio_count);
93
94 uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name");
95 if (!uc_priv->bank_name)
96 uc_priv->bank_name = dev_read_name(dev);
97
98 if (!bit_per_gpio) {
99 pr_err("%s: 'gpio-bit-per-line' can't be 0\n",
100 uc_priv->bank_name);
101
102 return -EINVAL;
103 }
104
105 if (!gpio_count) {
106 pr_err("%s: 'gpio-count' can't be 0\n",
107 uc_priv->bank_name);
108
109 return -EINVAL;
110 }
111
112 if ((gpio_count * bit_per_gpio + shift) > 32) {
113 pr_err("%s: u32 io register overflow: try to use %u bits\n",
114 uc_priv->bank_name, gpio_count * bit_per_gpio + shift);
115
116 return -EINVAL;
117 }
118
119 if (GENMASK(31, bit_per_gpio) & activate) {
120 pr_err("%s: 'gpio-activate-val' can't be more than %lu\n",
121 uc_priv->bank_name, GENMASK(bit_per_gpio - 1, 0));
122
123 return -EINVAL;
124 }
125
126 if (GENMASK(31, bit_per_gpio) & deactivate) {
127 pr_err("%s: 'gpio-deactivate-val' can't be more than %lu\n",
128 uc_priv->bank_name, GENMASK(bit_per_gpio - 1, 0));
129
130 return -EINVAL;
131 }
132
133 if (activate == deactivate) {
134 pr_err("%s: 'gpio-deactivate-val' and 'gpio-activate-val' can't be equal\n",
135 uc_priv->bank_name);
136
137 return -EINVAL;
138 }
139
140 hcg->shift = (u8)shift;
141 hcg->bit_per_gpio = (u8)bit_per_gpio;
142 hcg->activate = (u8)activate;
143 hcg->deactivate = (u8)deactivate;
144 uc_priv->gpio_count = gpio_count;
145
146 /* Setup default GPIO value if we have "gpio-default-val" array */
147 if (defaults)
148 for (u8 i = 0; i < gpio_count; i++)
149 hsdk_creg_gpio_set_value(dev, i, defaults[i]);
150
151 pr_debug("%s GPIO [0x%p] controller with %d gpios probed\n",
152 uc_priv->bank_name, hcg->regs, uc_priv->gpio_count);
153
154 return 0;
155 }
156
157 static const struct udevice_id hsdk_creg_gpio_ids[] = {
158 { .compatible = "snps,creg-gpio" },
159 { }
160 };
161
162 U_BOOT_DRIVER(gpio_hsdk_creg) = {
163 .name = DRV_NAME,
164 .id = UCLASS_GPIO,
165 .ops = &hsdk_creg_gpio_ops,
166 .probe = hsdk_creg_gpio_probe,
167 .of_match = hsdk_creg_gpio_ids,
168 .plat_auto = sizeof(struct hsdk_creg_gpio),
169 };
170