1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2009-2012 Freescale Semiconductor, Inc.
4 * Copyright 2020 NXP
5 * Dave Liu <daveliu@freescale.com>
6 */
7 #include <common.h>
8 #include <log.h>
9 #include <part.h>
10 #include <asm/io.h>
11 #ifdef CONFIG_DM_ETH
12 #include <dm.h>
13 #include <dm/ofnode.h>
14 #include <linux/compat.h>
15 #include <phy_interface.h>
16 #endif
17 #include <malloc.h>
18 #include <net.h>
19 #include <hwconfig.h>
20 #include <fm_eth.h>
21 #include <fsl_mdio.h>
22 #include <miiphy.h>
23 #include <phy.h>
24 #include <fsl_dtsec.h>
25 #include <fsl_tgec.h>
26 #include <fsl_memac.h>
27 #include <linux/delay.h>
28
29 #include "fm.h"
30
31 #ifndef CONFIG_DM_ETH
32 static struct eth_device *devlist[NUM_FM_PORTS];
33 static int num_controllers;
34 #endif
35
36 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
37
38 #define TBIANA_SETTINGS (TBIANA_ASYMMETRIC_PAUSE | TBIANA_SYMMETRIC_PAUSE | \
39 TBIANA_FULL_DUPLEX)
40
41 #define TBIANA_SGMII_ACK 0x4001
42
43 #define TBICR_SETTINGS (TBICR_ANEG_ENABLE | TBICR_RESTART_ANEG | \
44 TBICR_FULL_DUPLEX | TBICR_SPEED1_SET)
45
46 /* Configure the TBI for SGMII operation */
dtsec_configure_serdes(struct fm_eth * priv)47 static void dtsec_configure_serdes(struct fm_eth *priv)
48 {
49 #ifdef CONFIG_SYS_FMAN_V3
50 u32 value;
51 struct mii_dev bus;
52 bool sgmii_2500 = (priv->enet_if ==
53 PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
54 int i = 0, j;
55
56 #ifndef CONFIG_DM_ETH
57 bus.priv = priv->mac->phyregs;
58 #else
59 bus.priv = priv->pcs_mdio;
60 bus.read = memac_mdio_read;
61 bus.write = memac_mdio_write;
62 bus.reset = memac_mdio_reset;
63 #endif
64
65 qsgmii_loop:
66 /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
67 if (sgmii_2500)
68 value = PHY_SGMII_CR_PHY_RESET |
69 PHY_SGMII_IF_SPEED_GIGABIT |
70 PHY_SGMII_IF_MODE_SGMII;
71 else
72 value = PHY_SGMII_IF_MODE_SGMII | PHY_SGMII_IF_MODE_AN;
73
74 for (j = 0; j <= 3; j++)
75 debug("dump PCS reg %#x: %#x\n", j,
76 memac_mdio_read(&bus, i, MDIO_DEVAD_NONE, j));
77
78 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x14, value);
79
80 /* Dev ability according to SGMII specification */
81 value = PHY_SGMII_DEV_ABILITY_SGMII;
82 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x4, value);
83
84 if (sgmii_2500) {
85 /* Adjust link timer for 2.5G SGMII,
86 * 1.6 ms in units of 3.2 ns:
87 * 1.6ms / 3.2ns = 5 * 10^5 = 0x7a120.
88 */
89 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0007);
90 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xa120);
91 } else {
92 /* Adjust link timer for SGMII,
93 * 1.6 ms in units of 8 ns:
94 * 1.6ms / 8ns = 2 * 10^5 = 0x30d40.
95 */
96 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0003);
97 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0x0d40);
98 }
99
100 /* Restart AN */
101 value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN;
102 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0, value);
103
104 if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) {
105 i++;
106 goto qsgmii_loop;
107 }
108 #else
109 struct dtsec *regs = priv->mac->base;
110 struct tsec_mii_mng *phyregs = priv->mac->phyregs;
111
112 /*
113 * Access TBI PHY registers at given TSEC register offset as
114 * opposed to the register offset used for external PHY accesses
115 */
116 tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0, TBI_TBICON,
117 TBICON_CLK_SELECT);
118 tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0, TBI_ANA,
119 TBIANA_SGMII_ACK);
120 tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0,
121 TBI_CR, TBICR_SETTINGS);
122 #endif
123 }
124
dtsec_init_phy(struct fm_eth * fm_eth)125 static void dtsec_init_phy(struct fm_eth *fm_eth)
126 {
127 #ifndef CONFIG_SYS_FMAN_V3
128 struct dtsec *regs = (struct dtsec *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
129
130 /* Assign a Physical address to the TBI */
131 out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
132 #endif
133
134 if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
135 fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII ||
136 fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
137 dtsec_configure_serdes(fm_eth);
138 }
139
140 #ifndef CONFIG_DM_ETH
141 #ifdef CONFIG_PHYLIB
tgec_is_fibre(struct fm_eth * fm)142 static int tgec_is_fibre(struct fm_eth *fm)
143 {
144 char phyopt[20];
145
146 sprintf(phyopt, "fsl_fm%d_xaui_phy", fm->fm_index + 1);
147
148 return hwconfig_arg_cmp(phyopt, "xfi");
149 }
150 #endif
151 #endif /* CONFIG_DM_ETH */
152 #endif
153
muram_readw(u16 * addr)154 static u16 muram_readw(u16 *addr)
155 {
156 ulong base = (ulong)addr & ~0x3UL;
157 u32 val32 = in_be32((void *)base);
158 int byte_pos;
159 u16 ret;
160
161 byte_pos = (ulong)addr & 0x3UL;
162 if (byte_pos)
163 ret = (u16)(val32 & 0x0000ffff);
164 else
165 ret = (u16)((val32 & 0xffff0000) >> 16);
166
167 return ret;
168 }
169
muram_writew(u16 * addr,u16 val)170 static void muram_writew(u16 *addr, u16 val)
171 {
172 ulong base = (ulong)addr & ~0x3UL;
173 u32 org32 = in_be32((void *)base);
174 u32 val32;
175 int byte_pos;
176
177 byte_pos = (ulong)addr & 0x3UL;
178 if (byte_pos)
179 val32 = (org32 & 0xffff0000) | val;
180 else
181 val32 = (org32 & 0x0000ffff) | ((u32)val << 16);
182
183 out_be32((void *)base, val32);
184 }
185
bmi_rx_port_disable(struct fm_bmi_rx_port * rx_port)186 static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port)
187 {
188 int timeout = 1000000;
189
190 clrbits_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_EN);
191
192 /* wait until the rx port is not busy */
193 while ((in_be32(&rx_port->fmbm_rst) & FMBM_RST_BSY) && timeout--)
194 ;
195 if (!timeout)
196 printf("%s - timeout\n", __func__);
197 }
198
bmi_rx_port_init(struct fm_bmi_rx_port * rx_port)199 static void bmi_rx_port_init(struct fm_bmi_rx_port *rx_port)
200 {
201 /* set BMI to independent mode, Rx port disable */
202 out_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_IM);
203 /* clear FOF in IM case */
204 out_be32(&rx_port->fmbm_rim, 0);
205 /* Rx frame next engine -RISC */
206 out_be32(&rx_port->fmbm_rfne, NIA_ENG_RISC | NIA_RISC_AC_IM_RX);
207 /* Rx command attribute - no order, MR[3] = 1 */
208 clrbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_ORDER | FMBM_RFCA_MR_MASK);
209 setbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_MR(4));
210 /* enable Rx statistic counters */
211 out_be32(&rx_port->fmbm_rstc, FMBM_RSTC_EN);
212 /* disable Rx performance counters */
213 out_be32(&rx_port->fmbm_rpc, 0);
214 }
215
bmi_tx_port_disable(struct fm_bmi_tx_port * tx_port)216 static void bmi_tx_port_disable(struct fm_bmi_tx_port *tx_port)
217 {
218 int timeout = 1000000;
219
220 clrbits_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_EN);
221
222 /* wait until the tx port is not busy */
223 while ((in_be32(&tx_port->fmbm_tst) & FMBM_TST_BSY) && timeout--)
224 ;
225 if (!timeout)
226 printf("%s - timeout\n", __func__);
227 }
228
bmi_tx_port_init(struct fm_bmi_tx_port * tx_port)229 static void bmi_tx_port_init(struct fm_bmi_tx_port *tx_port)
230 {
231 /* set BMI to independent mode, Tx port disable */
232 out_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_IM);
233 /* Tx frame next engine -RISC */
234 out_be32(&tx_port->fmbm_tfne, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
235 out_be32(&tx_port->fmbm_tfene, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
236 /* Tx command attribute - no order, MR[3] = 1 */
237 clrbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_ORDER | FMBM_TFCA_MR_MASK);
238 setbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_MR(4));
239 /* enable Tx statistic counters */
240 out_be32(&tx_port->fmbm_tstc, FMBM_TSTC_EN);
241 /* disable Tx performance counters */
242 out_be32(&tx_port->fmbm_tpc, 0);
243 }
244
fm_eth_rx_port_parameter_init(struct fm_eth * fm_eth)245 static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
246 {
247 struct fm_port_global_pram *pram;
248 u32 pram_page_offset;
249 void *rx_bd_ring_base;
250 void *rx_buf_pool;
251 u32 bd_ring_base_lo, bd_ring_base_hi;
252 u32 buf_lo, buf_hi;
253 struct fm_port_bd *rxbd;
254 struct fm_port_qd *rxqd;
255 struct fm_bmi_rx_port *bmi_rx_port = fm_eth->rx_port;
256 int i;
257
258 /* alloc global parameter ram at MURAM */
259 pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
260 FM_PRAM_SIZE, FM_PRAM_ALIGN);
261 if (!pram) {
262 printf("%s: No muram for Rx global parameter\n", __func__);
263 return -ENOMEM;
264 }
265
266 fm_eth->rx_pram = pram;
267
268 /* parameter page offset to MURAM */
269 pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
270
271 /* enable global mode- snooping data buffers and BDs */
272 out_be32(&pram->mode, PRAM_MODE_GLOBAL);
273
274 /* init the Rx queue descriptor pionter */
275 out_be32(&pram->rxqd_ptr, pram_page_offset + 0x20);
276
277 /* set the max receive buffer length, power of 2 */
278 muram_writew(&pram->mrblr, MAX_RXBUF_LOG2);
279
280 /* alloc Rx buffer descriptors from main memory */
281 rx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
282 * RX_BD_RING_SIZE);
283 if (!rx_bd_ring_base)
284 return -ENOMEM;
285
286 memset(rx_bd_ring_base, 0, sizeof(struct fm_port_bd)
287 * RX_BD_RING_SIZE);
288
289 /* alloc Rx buffer from main memory */
290 rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE);
291 if (!rx_buf_pool) {
292 free(rx_bd_ring_base);
293 return -ENOMEM;
294 }
295
296 memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
297 debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool);
298
299 /* save them to fm_eth */
300 fm_eth->rx_bd_ring = rx_bd_ring_base;
301 fm_eth->cur_rxbd = rx_bd_ring_base;
302 fm_eth->rx_buf = rx_buf_pool;
303
304 /* init Rx BDs ring */
305 rxbd = (struct fm_port_bd *)rx_bd_ring_base;
306 for (i = 0; i < RX_BD_RING_SIZE; i++) {
307 muram_writew(&rxbd->status, RxBD_EMPTY);
308 muram_writew(&rxbd->len, 0);
309 buf_hi = upper_32_bits(virt_to_phys(rx_buf_pool +
310 i * MAX_RXBUF_LEN));
311 buf_lo = lower_32_bits(virt_to_phys(rx_buf_pool +
312 i * MAX_RXBUF_LEN));
313 muram_writew(&rxbd->buf_ptr_hi, (u16)buf_hi);
314 out_be32(&rxbd->buf_ptr_lo, buf_lo);
315 rxbd++;
316 }
317
318 /* set the Rx queue descriptor */
319 rxqd = &pram->rxqd;
320 muram_writew(&rxqd->gen, 0);
321 bd_ring_base_hi = upper_32_bits(virt_to_phys(rx_bd_ring_base));
322 bd_ring_base_lo = lower_32_bits(virt_to_phys(rx_bd_ring_base));
323 muram_writew(&rxqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
324 out_be32(&rxqd->bd_ring_base_lo, bd_ring_base_lo);
325 muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd)
326 * RX_BD_RING_SIZE);
327 muram_writew(&rxqd->offset_in, 0);
328 muram_writew(&rxqd->offset_out, 0);
329
330 /* set IM parameter ram pointer to Rx Frame Queue ID */
331 out_be32(&bmi_rx_port->fmbm_rfqid, pram_page_offset);
332
333 return 0;
334 }
335
fm_eth_tx_port_parameter_init(struct fm_eth * fm_eth)336 static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
337 {
338 struct fm_port_global_pram *pram;
339 u32 pram_page_offset;
340 void *tx_bd_ring_base;
341 u32 bd_ring_base_lo, bd_ring_base_hi;
342 struct fm_port_bd *txbd;
343 struct fm_port_qd *txqd;
344 struct fm_bmi_tx_port *bmi_tx_port = fm_eth->tx_port;
345 int i;
346
347 /* alloc global parameter ram at MURAM */
348 pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
349 FM_PRAM_SIZE, FM_PRAM_ALIGN);
350 if (!pram) {
351 printf("%s: No muram for Tx global parameter\n", __func__);
352 return -ENOMEM;
353 }
354 fm_eth->tx_pram = pram;
355
356 /* parameter page offset to MURAM */
357 pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
358
359 /* enable global mode- snooping data buffers and BDs */
360 out_be32(&pram->mode, PRAM_MODE_GLOBAL);
361
362 /* init the Tx queue descriptor pionter */
363 out_be32(&pram->txqd_ptr, pram_page_offset + 0x40);
364
365 /* alloc Tx buffer descriptors from main memory */
366 tx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
367 * TX_BD_RING_SIZE);
368 if (!tx_bd_ring_base)
369 return -ENOMEM;
370
371 memset(tx_bd_ring_base, 0, sizeof(struct fm_port_bd)
372 * TX_BD_RING_SIZE);
373 /* save it to fm_eth */
374 fm_eth->tx_bd_ring = tx_bd_ring_base;
375 fm_eth->cur_txbd = tx_bd_ring_base;
376
377 /* init Tx BDs ring */
378 txbd = (struct fm_port_bd *)tx_bd_ring_base;
379 for (i = 0; i < TX_BD_RING_SIZE; i++) {
380 muram_writew(&txbd->status, TxBD_LAST);
381 muram_writew(&txbd->len, 0);
382 muram_writew(&txbd->buf_ptr_hi, 0);
383 out_be32(&txbd->buf_ptr_lo, 0);
384 txbd++;
385 }
386
387 /* set the Tx queue decriptor */
388 txqd = &pram->txqd;
389 bd_ring_base_hi = upper_32_bits(virt_to_phys(tx_bd_ring_base));
390 bd_ring_base_lo = lower_32_bits(virt_to_phys(tx_bd_ring_base));
391 muram_writew(&txqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
392 out_be32(&txqd->bd_ring_base_lo, bd_ring_base_lo);
393 muram_writew(&txqd->bd_ring_size, sizeof(struct fm_port_bd)
394 * TX_BD_RING_SIZE);
395 muram_writew(&txqd->offset_in, 0);
396 muram_writew(&txqd->offset_out, 0);
397
398 /* set IM parameter ram pointer to Tx Confirmation Frame Queue ID */
399 out_be32(&bmi_tx_port->fmbm_tcfqid, pram_page_offset);
400
401 return 0;
402 }
403
fm_eth_init(struct fm_eth * fm_eth)404 static int fm_eth_init(struct fm_eth *fm_eth)
405 {
406 int ret;
407
408 ret = fm_eth_rx_port_parameter_init(fm_eth);
409 if (ret)
410 return ret;
411
412 ret = fm_eth_tx_port_parameter_init(fm_eth);
413 if (ret)
414 return ret;
415
416 return 0;
417 }
418
fm_eth_startup(struct fm_eth * fm_eth)419 static int fm_eth_startup(struct fm_eth *fm_eth)
420 {
421 struct fsl_enet_mac *mac;
422 int ret;
423
424 mac = fm_eth->mac;
425
426 /* Rx/TxBDs, Rx/TxQDs, Rx buff and parameter ram init */
427 ret = fm_eth_init(fm_eth);
428 if (ret)
429 return ret;
430 /* setup the MAC controller */
431 mac->init_mac(mac);
432
433 /* For some reason we need to set SPEED_100 */
434 if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) ||
435 (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) ||
436 (fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) &&
437 mac->set_if_mode)
438 mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100);
439
440 /* init bmi rx port, IM mode and disable */
441 bmi_rx_port_init(fm_eth->rx_port);
442 /* init bmi tx port, IM mode and disable */
443 bmi_tx_port_init(fm_eth->tx_port);
444
445 return 0;
446 }
447
fmc_tx_port_graceful_stop_enable(struct fm_eth * fm_eth)448 static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth)
449 {
450 struct fm_port_global_pram *pram;
451
452 pram = fm_eth->tx_pram;
453 /* graceful stop transmission of frames */
454 setbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
455 sync();
456 }
457
fmc_tx_port_graceful_stop_disable(struct fm_eth * fm_eth)458 static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
459 {
460 struct fm_port_global_pram *pram;
461
462 pram = fm_eth->tx_pram;
463 /* re-enable transmission of frames */
464 clrbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
465 sync();
466 }
467
468 #ifndef CONFIG_DM_ETH
fm_eth_open(struct eth_device * dev,struct bd_info * bd)469 static int fm_eth_open(struct eth_device *dev, struct bd_info *bd)
470 #else
471 static int fm_eth_open(struct udevice *dev)
472 #endif
473 {
474 #ifndef CONFIG_DM_ETH
475 struct fm_eth *fm_eth = dev->priv;
476 #else
477 struct eth_pdata *pdata = dev_get_plat(dev);
478 struct fm_eth *fm_eth = dev_get_priv(dev);
479 #endif
480 unsigned char *enetaddr;
481 struct fsl_enet_mac *mac;
482 #ifdef CONFIG_PHYLIB
483 int ret;
484 #endif
485
486 mac = fm_eth->mac;
487
488 #ifndef CONFIG_DM_ETH
489 enetaddr = &dev->enetaddr[0];
490 #else
491 enetaddr = pdata->enetaddr;
492 #endif
493
494 /* setup the MAC address */
495 if (enetaddr[0] & 0x01) {
496 printf("%s: MacAddress is multicast address\n", __func__);
497 enetaddr[0] = 0;
498 enetaddr[5] = fm_eth->num;
499 }
500 mac->set_mac_addr(mac, enetaddr);
501
502 /* enable bmi Rx port */
503 setbits_be32(&fm_eth->rx_port->fmbm_rcfg, FMBM_RCFG_EN);
504 /* enable MAC rx/tx port */
505 mac->enable_mac(mac);
506 /* enable bmi Tx port */
507 setbits_be32(&fm_eth->tx_port->fmbm_tcfg, FMBM_TCFG_EN);
508 /* re-enable transmission of frame */
509 fmc_tx_port_graceful_stop_disable(fm_eth);
510
511 #ifdef CONFIG_PHYLIB
512 if (fm_eth->phydev) {
513 ret = phy_startup(fm_eth->phydev);
514 if (ret) {
515 #ifndef CONFIG_DM_ETH
516 printf("%s: Could not initialize\n",
517 fm_eth->phydev->dev->name);
518 #else
519 printf("%s: Could not initialize\n", dev->name);
520 #endif
521 return ret;
522 }
523 } else {
524 return 0;
525 }
526 #else
527 fm_eth->phydev->speed = SPEED_1000;
528 fm_eth->phydev->link = 1;
529 fm_eth->phydev->duplex = DUPLEX_FULL;
530 #endif
531
532 /* set the MAC-PHY mode */
533 mac->set_if_mode(mac, fm_eth->enet_if, fm_eth->phydev->speed);
534 debug("MAC IF mode %d, speed %d, link %d\n", fm_eth->enet_if,
535 fm_eth->phydev->speed, fm_eth->phydev->link);
536
537 if (!fm_eth->phydev->link)
538 printf("%s: No link.\n", fm_eth->phydev->dev->name);
539
540 return fm_eth->phydev->link ? 0 : -1;
541 }
542
543 #ifndef CONFIG_DM_ETH
fm_eth_halt(struct eth_device * dev)544 static void fm_eth_halt(struct eth_device *dev)
545 #else
546 static void fm_eth_halt(struct udevice *dev)
547 #endif
548 {
549 struct fm_eth *fm_eth;
550 struct fsl_enet_mac *mac;
551
552 #ifndef CONFIG_DM_ETH
553 fm_eth = (struct fm_eth *)dev->priv;
554 #else
555 fm_eth = dev_get_priv(dev);
556 #endif
557 mac = fm_eth->mac;
558
559 /* graceful stop the transmission of frames */
560 fmc_tx_port_graceful_stop_enable(fm_eth);
561 /* disable bmi Tx port */
562 bmi_tx_port_disable(fm_eth->tx_port);
563 /* disable MAC rx/tx port */
564 mac->disable_mac(mac);
565 /* disable bmi Rx port */
566 bmi_rx_port_disable(fm_eth->rx_port);
567
568 #ifdef CONFIG_PHYLIB
569 if (fm_eth->phydev)
570 phy_shutdown(fm_eth->phydev);
571 #endif
572 }
573
574 #ifndef CONFIG_DM_ETH
fm_eth_send(struct eth_device * dev,void * buf,int len)575 static int fm_eth_send(struct eth_device *dev, void *buf, int len)
576 #else
577 static int fm_eth_send(struct udevice *dev, void *buf, int len)
578 #endif
579 {
580 struct fm_eth *fm_eth;
581 struct fm_port_global_pram *pram;
582 struct fm_port_bd *txbd, *txbd_base;
583 u16 offset_in;
584 int i;
585
586 #ifndef CONFIG_DM_ETH
587 fm_eth = (struct fm_eth *)dev->priv;
588 #else
589 fm_eth = dev_get_priv(dev);
590 #endif
591 pram = fm_eth->tx_pram;
592 txbd = fm_eth->cur_txbd;
593
594 /* find one empty TxBD */
595 for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
596 udelay(100);
597 if (i > 0x1000) {
598 printf("%s: Tx buffer not ready, txbd->status = 0x%x\n",
599 dev->name, muram_readw(&txbd->status));
600 return 0;
601 }
602 }
603 /* setup TxBD */
604 muram_writew(&txbd->buf_ptr_hi, (u16)upper_32_bits(virt_to_phys(buf)));
605 out_be32(&txbd->buf_ptr_lo, lower_32_bits(virt_to_phys(buf)));
606 muram_writew(&txbd->len, len);
607 sync();
608 muram_writew(&txbd->status, TxBD_READY | TxBD_LAST);
609 sync();
610
611 /* update TxQD, let RISC to send the packet */
612 offset_in = muram_readw(&pram->txqd.offset_in);
613 offset_in += sizeof(struct fm_port_bd);
614 if (offset_in >= muram_readw(&pram->txqd.bd_ring_size))
615 offset_in = 0;
616 muram_writew(&pram->txqd.offset_in, offset_in);
617 sync();
618
619 /* wait for buffer to be transmitted */
620 for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
621 udelay(100);
622 if (i > 0x10000) {
623 printf("%s: Tx error, txbd->status = 0x%x\n",
624 dev->name, muram_readw(&txbd->status));
625 return 0;
626 }
627 }
628
629 /* advance the TxBD */
630 txbd++;
631 txbd_base = (struct fm_port_bd *)fm_eth->tx_bd_ring;
632 if (txbd >= (txbd_base + TX_BD_RING_SIZE))
633 txbd = txbd_base;
634 /* update current txbd */
635 fm_eth->cur_txbd = (void *)txbd;
636
637 return 1;
638 }
639
fm_eth_free_one(struct fm_eth * fm_eth,struct fm_port_bd * rxbd)640 static struct fm_port_bd *fm_eth_free_one(struct fm_eth *fm_eth,
641 struct fm_port_bd *rxbd)
642 {
643 struct fm_port_global_pram *pram;
644 struct fm_port_bd *rxbd_base;
645 u16 offset_out;
646
647 pram = fm_eth->rx_pram;
648
649 /* clear the RxBDs */
650 muram_writew(&rxbd->status, RxBD_EMPTY);
651 muram_writew(&rxbd->len, 0);
652 sync();
653
654 /* advance RxBD */
655 rxbd++;
656 rxbd_base = (struct fm_port_bd *)fm_eth->rx_bd_ring;
657 if (rxbd >= (rxbd_base + RX_BD_RING_SIZE))
658 rxbd = rxbd_base;
659
660 /* update RxQD */
661 offset_out = muram_readw(&pram->rxqd.offset_out);
662 offset_out += sizeof(struct fm_port_bd);
663 if (offset_out >= muram_readw(&pram->rxqd.bd_ring_size))
664 offset_out = 0;
665 muram_writew(&pram->rxqd.offset_out, offset_out);
666 sync();
667
668 return rxbd;
669 }
670
671 #ifndef CONFIG_DM_ETH
fm_eth_recv(struct eth_device * dev)672 static int fm_eth_recv(struct eth_device *dev)
673 #else
674 static int fm_eth_recv(struct udevice *dev, int flags, uchar **packetp)
675 #endif
676 {
677 struct fm_eth *fm_eth;
678 struct fm_port_bd *rxbd;
679 u32 buf_lo, buf_hi;
680 u16 status, len;
681 int ret = -1;
682 u8 *data;
683
684 #ifndef CONFIG_DM_ETH
685 fm_eth = (struct fm_eth *)dev->priv;
686 #else
687 fm_eth = dev_get_priv(dev);
688 #endif
689 rxbd = fm_eth->cur_rxbd;
690 status = muram_readw(&rxbd->status);
691
692 while (!(status & RxBD_EMPTY)) {
693 if (!(status & RxBD_ERROR)) {
694 buf_hi = muram_readw(&rxbd->buf_ptr_hi);
695 buf_lo = in_be32(&rxbd->buf_ptr_lo);
696 data = (u8 *)((ulong)(buf_hi << 16) << 16 | buf_lo);
697 len = muram_readw(&rxbd->len);
698 #ifndef CONFIG_DM_ETH
699 net_process_received_packet(data, len);
700 #else
701 *packetp = data;
702 return len;
703 #endif
704 } else {
705 printf("%s: Rx error\n", dev->name);
706 ret = 0;
707 }
708
709 /* free current bd, advance to next one */
710 rxbd = fm_eth_free_one(fm_eth, rxbd);
711
712 /* read next status */
713 status = muram_readw(&rxbd->status);
714 }
715 fm_eth->cur_rxbd = (void *)rxbd;
716
717 return ret;
718 }
719
720 #ifdef CONFIG_DM_ETH
fm_eth_free_pkt(struct udevice * dev,uchar * packet,int length)721 static int fm_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
722 {
723 struct fm_eth *fm_eth = (struct fm_eth *)dev_get_priv(dev);
724
725 fm_eth->cur_rxbd = fm_eth_free_one(fm_eth, fm_eth->cur_rxbd);
726
727 return 0;
728 }
729 #endif /* CONFIG_DM_ETH */
730
731 #ifndef CONFIG_DM_ETH
fm_eth_init_mac(struct fm_eth * fm_eth,struct ccsr_fman * reg)732 static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
733 {
734 struct fsl_enet_mac *mac;
735 int num;
736 void *base, *phyregs = NULL;
737
738 num = fm_eth->num;
739
740 #ifdef CONFIG_SYS_FMAN_V3
741 #ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
742 if (fm_eth->type == FM_ETH_10G_E) {
743 /* 10GEC1/10GEC2 use mEMAC9/mEMAC10 on T2080/T4240.
744 * 10GEC3/10GEC4 use mEMAC1/mEMAC2 on T2080.
745 * 10GEC1 uses mEMAC1 on T1024.
746 * so it needs to change the num.
747 */
748 if (fm_eth->num >= 2)
749 num -= 2;
750 else
751 num += 8;
752 }
753 #endif
754 base = ®->memac[num].fm_memac;
755 phyregs = ®->memac[num].fm_memac_mdio;
756 #else
757 /* Get the mac registers base address */
758 if (fm_eth->type == FM_ETH_1G_E) {
759 base = ®->mac_1g[num].fm_dtesc;
760 phyregs = ®->mac_1g[num].fm_mdio.miimcfg;
761 } else {
762 base = ®->mac_10g[num].fm_10gec;
763 phyregs = ®->mac_10g[num].fm_10gec_mdio;
764 }
765 #endif
766
767 /* alloc mac controller */
768 mac = malloc(sizeof(struct fsl_enet_mac));
769 if (!mac)
770 return -ENOMEM;
771 memset(mac, 0, sizeof(struct fsl_enet_mac));
772
773 /* save the mac to fm_eth struct */
774 fm_eth->mac = mac;
775
776 #ifdef CONFIG_SYS_FMAN_V3
777 init_memac(mac, base, phyregs, MAX_RXBUF_LEN);
778 #else
779 if (fm_eth->type == FM_ETH_1G_E)
780 init_dtsec(mac, base, phyregs, MAX_RXBUF_LEN);
781 else
782 init_tgec(mac, base, phyregs, MAX_RXBUF_LEN);
783 #endif
784
785 return 0;
786 }
787 #else /* CONFIG_DM_ETH */
fm_eth_init_mac(struct fm_eth * fm_eth,void * reg)788 static int fm_eth_init_mac(struct fm_eth *fm_eth, void *reg)
789 {
790 #ifndef CONFIG_SYS_FMAN_V3
791 void *mdio;
792 #endif
793
794 fm_eth->mac = kzalloc(sizeof(*fm_eth->mac), GFP_KERNEL);
795 if (!fm_eth->mac)
796 return -ENOMEM;
797
798 #ifndef CONFIG_SYS_FMAN_V3
799 mdio = fman_mdio(fm_eth->dev->parent, fm_eth->mac_type, fm_eth->num);
800 debug("MDIO %d @ %p\n", fm_eth->num, mdio);
801 #endif
802
803 switch (fm_eth->mac_type) {
804 #ifdef CONFIG_SYS_FMAN_V3
805 case FM_MEMAC:
806 init_memac(fm_eth->mac, reg, NULL, MAX_RXBUF_LEN);
807 break;
808 #else
809 case FM_DTSEC:
810 init_dtsec(fm_eth->mac, reg, mdio, MAX_RXBUF_LEN);
811 break;
812 case FM_TGEC:
813 init_tgec(fm_eth->mac, reg, mdio, MAX_RXBUF_LEN);
814 break;
815 #endif
816 }
817
818 return 0;
819 }
820 #endif /* CONFIG_DM_ETH */
821
init_phy(struct fm_eth * fm_eth)822 static int init_phy(struct fm_eth *fm_eth)
823 {
824 #ifdef CONFIG_PHYLIB
825 u32 supported = PHY_GBIT_FEATURES;
826 #ifndef CONFIG_DM_ETH
827 struct phy_device *phydev = NULL;
828 #endif
829
830 if (fm_eth->type == FM_ETH_10G_E)
831 supported = PHY_10G_FEATURES;
832 if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
833 supported |= SUPPORTED_2500baseX_Full;
834 #endif
835
836 if (fm_eth->type == FM_ETH_1G_E)
837 dtsec_init_phy(fm_eth);
838
839 #ifdef CONFIG_DM_ETH
840 #ifdef CONFIG_PHYLIB
841 #ifdef CONFIG_DM_MDIO
842 fm_eth->phydev = dm_eth_phy_connect(fm_eth->dev);
843 if (!fm_eth->phydev)
844 return -ENODEV;
845 #endif
846 fm_eth->phydev->advertising &= supported;
847 fm_eth->phydev->supported &= supported;
848
849 phy_config(fm_eth->phydev);
850 #endif
851 #else /* CONFIG_DM_ETH */
852 #ifdef CONFIG_PHYLIB
853 if (fm_eth->bus) {
854 phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, fm_eth->dev,
855 fm_eth->enet_if);
856 if (!phydev) {
857 printf("Failed to connect\n");
858 return -1;
859 }
860 } else {
861 return 0;
862 }
863
864 if (fm_eth->type == FM_ETH_1G_E) {
865 supported = (SUPPORTED_10baseT_Half |
866 SUPPORTED_10baseT_Full |
867 SUPPORTED_100baseT_Half |
868 SUPPORTED_100baseT_Full |
869 SUPPORTED_1000baseT_Full);
870 } else {
871 supported = SUPPORTED_10000baseT_Full;
872
873 if (tgec_is_fibre(fm_eth))
874 phydev->port = PORT_FIBRE;
875 }
876
877 phydev->supported &= supported;
878 phydev->advertising = phydev->supported;
879
880 fm_eth->phydev = phydev;
881
882 phy_config(phydev);
883 #endif
884 #endif /* CONFIG_DM_ETH */
885 return 0;
886 }
887
888 #ifndef CONFIG_DM_ETH
fm_eth_initialize(struct ccsr_fman * reg,struct fm_eth_info * info)889 int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
890 {
891 struct eth_device *dev;
892 struct fm_eth *fm_eth;
893 int i, num = info->num;
894 int ret;
895
896 /* alloc eth device */
897 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
898 if (!dev)
899 return -ENOMEM;
900 memset(dev, 0, sizeof(struct eth_device));
901
902 /* alloc the FMan ethernet private struct */
903 fm_eth = (struct fm_eth *)malloc(sizeof(struct fm_eth));
904 if (!fm_eth)
905 return -ENOMEM;
906 memset(fm_eth, 0, sizeof(struct fm_eth));
907
908 /* save off some things we need from the info struct */
909 fm_eth->fm_index = info->index - 1; /* keep as 0 based for muram */
910 fm_eth->num = num;
911 fm_eth->type = info->type;
912
913 fm_eth->rx_port = (void *)®->port[info->rx_port_id - 1].fm_bmi;
914 fm_eth->tx_port = (void *)®->port[info->tx_port_id - 1].fm_bmi;
915
916 /* set the ethernet max receive length */
917 fm_eth->max_rx_len = MAX_RXBUF_LEN;
918
919 /* init global mac structure */
920 ret = fm_eth_init_mac(fm_eth, reg);
921 if (ret)
922 return ret;
923
924 /* keep same as the manual, we call FMAN1, FMAN2, DTSEC1, DTSEC2, etc */
925 if (fm_eth->type == FM_ETH_1G_E)
926 sprintf(dev->name, "FM%d@DTSEC%d", info->index, num + 1);
927 else
928 sprintf(dev->name, "FM%d@TGEC%d", info->index, num + 1);
929
930 devlist[num_controllers++] = dev;
931 dev->iobase = 0;
932 dev->priv = (void *)fm_eth;
933 dev->init = fm_eth_open;
934 dev->halt = fm_eth_halt;
935 dev->send = fm_eth_send;
936 dev->recv = fm_eth_recv;
937 fm_eth->dev = dev;
938 fm_eth->bus = info->bus;
939 fm_eth->phyaddr = info->phy_addr;
940 fm_eth->enet_if = info->enet_if;
941
942 /* startup the FM im */
943 ret = fm_eth_startup(fm_eth);
944 if (ret)
945 return ret;
946
947 init_phy(fm_eth);
948
949 /* clear the ethernet address */
950 for (i = 0; i < 6; i++)
951 dev->enetaddr[i] = 0;
952 eth_register(dev);
953
954 return 0;
955 }
956 #else /* CONFIG_DM_ETH */
957 #ifdef CONFIG_PHYLIB
fman_read_sys_if(struct udevice * dev)958 phy_interface_t fman_read_sys_if(struct udevice *dev)
959 {
960 const char *if_str;
961
962 if_str = ofnode_read_string(dev_ofnode(dev), "phy-connection-type");
963 debug("MAC system interface mode %s\n", if_str);
964
965 return phy_get_interface_by_name(if_str);
966 }
967 #endif
968
fm_eth_bind(struct udevice * dev)969 static int fm_eth_bind(struct udevice *dev)
970 {
971 char mac_name[11];
972 u32 fm, num;
973
974 if (ofnode_read_u32(ofnode_get_parent(dev_ofnode(dev)), "cell-index", &fm)) {
975 printf("FMan node property cell-index missing\n");
976 return -EINVAL;
977 }
978
979 if (dev && dev_read_u32(dev, "cell-index", &num)) {
980 printf("FMan MAC node property cell-index missing\n");
981 return -EINVAL;
982 }
983
984 sprintf(mac_name, "fm%d-mac%d", fm + 1, num + 1);
985 device_set_name(dev, mac_name);
986
987 debug("%s - binding %s\n", __func__, mac_name);
988
989 return 0;
990 }
991
fm_get_internal_mdio(struct udevice * dev)992 static struct udevice *fm_get_internal_mdio(struct udevice *dev)
993 {
994 struct ofnode_phandle_args phandle = {.node = ofnode_null()};
995 struct udevice *mdiodev;
996
997 if (dev_read_phandle_with_args(dev, "pcsphy-handle", NULL,
998 0, 0, &phandle) ||
999 !ofnode_valid(phandle.node)) {
1000 if (dev_read_phandle_with_args(dev, "tbi-handle", NULL,
1001 0, 0, &phandle) ||
1002 !ofnode_valid(phandle.node)) {
1003 printf("Issue reading pcsphy-handle/tbi-handle for MAC %s\n",
1004 dev->name);
1005 return NULL;
1006 }
1007 }
1008
1009 if (uclass_get_device_by_ofnode(UCLASS_MDIO,
1010 ofnode_get_parent(phandle.node),
1011 &mdiodev)) {
1012 printf("can't find MDIO bus for node %s\n",
1013 ofnode_get_name(ofnode_get_parent(phandle.node)));
1014 return NULL;
1015 }
1016 debug("Found internal MDIO bus %p\n", mdiodev);
1017
1018 return mdiodev;
1019 }
1020
fm_eth_probe(struct udevice * dev)1021 static int fm_eth_probe(struct udevice *dev)
1022 {
1023 struct fm_eth *fm_eth = (struct fm_eth *)dev_get_priv(dev);
1024 struct ofnode_phandle_args args;
1025 void *reg;
1026 int ret, index;
1027
1028 debug("%s enter for dev %p fm_eth %p - %s\n", __func__, dev, fm_eth,
1029 (dev) ? dev->name : "-");
1030
1031 if (fm_eth->dev) {
1032 printf("%s already probed, exit\n", (dev) ? dev->name : "-");
1033 return 0;
1034 }
1035
1036 fm_eth->dev = dev;
1037 fm_eth->fm_index = fman_id(dev->parent);
1038 reg = (void *)(uintptr_t)dev_read_addr(dev);
1039 fm_eth->mac_type = dev_get_driver_data(dev);
1040 #ifdef CONFIG_PHYLIB
1041 fm_eth->enet_if = fman_read_sys_if(dev);
1042 #else
1043 fm_eth->enet_if = PHY_INTERFACE_MODE_SGMII;
1044 printf("%s: warning - unable to determine interface type\n", __func__);
1045 #endif
1046 switch (fm_eth->mac_type) {
1047 #ifndef CONFIG_SYS_FMAN_V3
1048 case FM_TGEC:
1049 fm_eth->type = FM_ETH_10G_E;
1050 break;
1051 case FM_DTSEC:
1052 #else
1053 case FM_MEMAC:
1054 /* default to 1G, 10G is indicated by port property in dts */
1055 #endif
1056 fm_eth->type = FM_ETH_1G_E;
1057 break;
1058 }
1059
1060 if (dev_read_u32(dev, "cell-index", &fm_eth->num)) {
1061 printf("FMan MAC node property cell-index missing\n");
1062 return -EINVAL;
1063 }
1064
1065 if (dev_read_phandle_with_args(dev, "fsl,fman-ports", NULL,
1066 0, 0, &args))
1067 goto ports_ref_failure;
1068 index = ofnode_read_u32_default(args.node, "cell-index", 0);
1069 if (index <= 0)
1070 goto ports_ref_failure;
1071 fm_eth->rx_port = fman_port(dev->parent, index);
1072
1073 if (ofnode_read_bool(args.node, "fsl,fman-10g-port"))
1074 fm_eth->type = FM_ETH_10G_E;
1075
1076 if (dev_read_phandle_with_args(dev, "fsl,fman-ports", NULL,
1077 0, 1, &args))
1078 goto ports_ref_failure;
1079 index = ofnode_read_u32_default(args.node, "cell-index", 0);
1080 if (index <= 0)
1081 goto ports_ref_failure;
1082 fm_eth->tx_port = fman_port(dev->parent, index);
1083
1084 /* set the ethernet max receive length */
1085 fm_eth->max_rx_len = MAX_RXBUF_LEN;
1086
1087 switch (fm_eth->enet_if) {
1088 case PHY_INTERFACE_MODE_QSGMII:
1089 /* all PCS blocks are accessed on one controller */
1090 if (fm_eth->num != 0)
1091 break;
1092 case PHY_INTERFACE_MODE_SGMII:
1093 case PHY_INTERFACE_MODE_SGMII_2500:
1094 fm_eth->pcs_mdio = fm_get_internal_mdio(dev);
1095 break;
1096 default:
1097 break;
1098 }
1099
1100 /* init global mac structure */
1101 ret = fm_eth_init_mac(fm_eth, reg);
1102 if (ret)
1103 return ret;
1104
1105 /* startup the FM im */
1106 ret = fm_eth_startup(fm_eth);
1107
1108 if (!ret)
1109 ret = init_phy(fm_eth);
1110
1111 return ret;
1112
1113 ports_ref_failure:
1114 printf("Issue reading fsl,fman-ports for MAC %s\n", dev->name);
1115 return -ENOENT;
1116 }
1117
fm_eth_remove(struct udevice * dev)1118 static int fm_eth_remove(struct udevice *dev)
1119 {
1120 return 0;
1121 }
1122
1123 static const struct eth_ops fm_eth_ops = {
1124 .start = fm_eth_open,
1125 .send = fm_eth_send,
1126 .recv = fm_eth_recv,
1127 .free_pkt = fm_eth_free_pkt,
1128 .stop = fm_eth_halt,
1129 };
1130
1131 static const struct udevice_id fm_eth_ids[] = {
1132 #ifdef CONFIG_SYS_FMAN_V3
1133 { .compatible = "fsl,fman-memac", .data = FM_MEMAC },
1134 #else
1135 { .compatible = "fsl,fman-dtsec", .data = FM_DTSEC },
1136 { .compatible = "fsl,fman-xgec", .data = FM_TGEC },
1137 #endif
1138 {}
1139 };
1140
1141 U_BOOT_DRIVER(eth_fman) = {
1142 .name = "eth_fman",
1143 .id = UCLASS_ETH,
1144 .of_match = fm_eth_ids,
1145 .bind = fm_eth_bind,
1146 .probe = fm_eth_probe,
1147 .remove = fm_eth_remove,
1148 .ops = &fm_eth_ops,
1149 .priv_auto = sizeof(struct fm_eth),
1150 .plat_auto = sizeof(struct eth_pdata),
1151 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1152 };
1153 #endif /* CONFIG_DM_ETH */
1154