1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2016 Freescale Semiconductor, Inc. 4 * Copyright 2021 NXP 5 */ 6 7 #ifndef __LS1012AQDS_H__ 8 #define __LS1012AQDS_H__ 9 10 #include "ls1012a_common.h" 11 12 /* DDR */ 13 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 14 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 15 #define CONFIG_SYS_SDRAM_SIZE 0x40000000 16 17 /* 18 * QIXIS Definitions 19 */ 20 #define CONFIG_FSL_QIXIS 21 22 #ifdef CONFIG_FSL_QIXIS 23 #define CONFIG_QIXIS_I2C_ACCESS 24 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 25 #define QIXIS_LBMAP_BRDCFG_REG 0x04 26 #define QIXIS_LBMAP_SWITCH 6 27 #define QIXIS_LBMAP_MASK 0x08 28 #define QIXIS_LBMAP_SHIFT 0 29 #define QIXIS_LBMAP_DFLTBANK 0x00 30 #define QIXIS_LBMAP_ALTBANK 0x08 31 #define QIXIS_RST_CTL_RESET 0x31 32 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 33 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 34 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 35 #endif 36 37 /* 38 * I2C bus multiplexer 39 */ 40 #define I2C_MUX_PCA_ADDR_PRI 0x77 41 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 42 #define I2C_RETIMER_ADDR 0x18 43 #define I2C_MUX_CH_DEFAULT 0x8 44 #define I2C_MUX_CH_CH7301 0xC 45 #define I2C_MUX_CH5 0xD 46 #define I2C_MUX_CH7 0xF 47 48 #define I2C_MUX_CH_VOL_MONITOR 0xa 49 50 /* 51 * RTC configuration 52 */ 53 #define RTC 54 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ 55 56 /* EEPROM */ 57 #define CONFIG_ID_EEPROM 58 #define CONFIG_SYS_I2C_EEPROM_NXID 59 #define CONFIG_SYS_EEPROM_BUS_NUM 0 60 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 61 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 62 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 63 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 64 65 66 /* Voltage monitor on channel 2*/ 67 #define I2C_VOL_MONITOR_ADDR 0x40 68 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 69 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 70 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 71 72 /* DSPI */ 73 #define CONFIG_FSL_DSPI1 74 75 #define MMAP_DSPI DSPI1_BASE_ADDR 76 77 #define CONFIG_SYS_DSPI_CTAR0 1 78 79 #define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ 80 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ 81 DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \ 82 DSPI_CTAR_DT(0)) 83 #define CONFIG_SPI_FLASH_SST /* cs1 */ 84 85 #define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ 86 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ 87 DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \ 88 DSPI_CTAR_DT(0)) 89 #define CONFIG_SPI_FLASH_STMICRO /* cs2 */ 90 91 #define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ 92 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ 93 DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \ 94 DSPI_CTAR_DT(0)) 95 #define CONFIG_SPI_FLASH_EON /* cs3 */ 96 97 #define CONFIG_PCIE1 /* PCIE controller 1 */ 98 99 #define CONFIG_PCI_SCAN_SHOW 100 101 #undef CONFIG_EXTRA_ENV_SETTINGS 102 #define CONFIG_EXTRA_ENV_SETTINGS \ 103 "verify=no\0" \ 104 "fdt_addr=0x00f00000\0" \ 105 "kernel_addr=0x01000000\0" \ 106 "kernelheader_addr=0x600000\0" \ 107 "scriptaddr=0x80000000\0" \ 108 "scripthdraddr=0x80080000\0" \ 109 "fdtheader_addr_r=0x80100000\0" \ 110 "kernelheader_addr_r=0x80200000\0" \ 111 "kernel_addr_r=0x96000000\0" \ 112 "fdt_addr_r=0x90000000\0" \ 113 "load_addr=0xa0000000\0" \ 114 "kernel_size=0x2800000\0" \ 115 "kernelheader_size=0x40000\0" \ 116 "console=ttyS0,115200\0" \ 117 BOOTENV \ 118 "boot_scripts=ls1012aqds_boot.scr\0" \ 119 "boot_script_hdr=hdr_ls1012aqds_bs.out\0" \ 120 "scan_dev_for_boot_part=" \ 121 "part list ${devtype} ${devnum} devplist; " \ 122 "env exists devplist || setenv devplist 1; " \ 123 "for distro_bootpart in ${devplist}; do " \ 124 "if fstype ${devtype} " \ 125 "${devnum}:${distro_bootpart} " \ 126 "bootfstype; then " \ 127 "run scan_dev_for_boot; " \ 128 "fi; " \ 129 "done\0" \ 130 "boot_a_script=" \ 131 "load ${devtype} ${devnum}:${distro_bootpart} " \ 132 "${scriptaddr} ${prefix}${script}; " \ 133 "env exists secureboot && load ${devtype} " \ 134 "${devnum}:${distro_bootpart} " \ 135 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ 136 "env exists secureboot " \ 137 "&& esbc_validate ${scripthdraddr};" \ 138 "source ${scriptaddr}\0" \ 139 "qspi_bootcmd=echo Trying load from qspi..;" \ 140 "sf probe 0:0 && sf read $load_addr " \ 141 "$kernel_addr $kernel_size; env exists secureboot " \ 142 "&& sf read $kernelheader_addr_r $kernelheader_addr " \ 143 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 144 "bootm $load_addr#$board\0" 145 146 #undef CONFIG_BOOTCOMMAND 147 #ifdef CONFIG_TFABOOT 148 #undef QSPI_NOR_BOOTCOMMAND 149 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "\ 150 "env exists secureboot && esbc_halt;" 151 #else 152 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "\ 153 "env exists secureboot && esbc_halt;" 154 #endif 155 156 #include <asm/fsl_secure_boot.h> 157 #endif /* __LS1012AQDS_H__ */ 158