1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2009-2011 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef _ASM_CONFIG_H_ 7 #define _ASM_CONFIG_H_ 8 9 #ifdef CONFIG_MPC85xx 10 #include <asm/config_mpc85xx.h> 11 #endif 12 13 #ifdef CONFIG_MPC86xx 14 #include <asm/config_mpc86xx.h> 15 #endif 16 17 #ifndef HWCONFIG_BUFFER_SIZE 18 #define HWCONFIG_BUFFER_SIZE 256 19 #endif 20 21 #define CONFIG_SYS_BOOT_RAMDISK_HIGH 22 23 #ifndef CONFIG_MAX_MEM_MAPPED 24 #if defined(CONFIG_E500) || \ 25 defined(CONFIG_MPC86xx) || \ 26 defined(CONFIG_E300) 27 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) 28 #else 29 #define CONFIG_MAX_MEM_MAPPED (256 << 20) 30 #endif 31 #endif 32 33 /* Check if boards need to enable FSL DMA engine for SDRAM init */ 34 #if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC) 35 #if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \ 36 ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \ 37 !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) 38 #define CONFIG_FSL_DMA 39 #endif 40 #endif 41 42 /* 43 * Provide a default boot page translation virtual address that lines up with 44 * Freescale's default e500 reset page. 45 */ 46 #if (defined(CONFIG_E500) && defined(CONFIG_MP)) 47 #ifndef CONFIG_BPTR_VIRT_ADDR 48 #define CONFIG_BPTR_VIRT_ADDR 0xfffff000 49 #endif 50 #endif 51 52 /* Since so many PPC SOCs have a semi-common LBC, define this here */ 53 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ 54 defined(CONFIG_MPC83xx) 55 #if !defined(CONFIG_FSL_IFC) 56 #define CONFIG_FSL_LBC 57 #endif 58 #endif 59 60 /* The TSEC driver uses the PHYLIB infrastructure */ 61 #if defined(CONFIG_TSEC_ENET) && defined(CONFIG_PHYLIB) 62 #include <config_phylib_all_drivers.h> 63 #endif /* TSEC_ENET */ 64 65 /* The FMAN driver uses the PHYLIB infrastructure */ 66 67 /* All PPC boards must swap IDE bytes */ 68 #define CONFIG_IDE_SWAP_IO 69 70 #if defined(CONFIG_DM_SERIAL) && !defined(CONFIG_CLK_MPC83XX) 71 /* 72 * TODO: Convert this to a clock driver exists that can give us the UART 73 * clock here. 74 */ 75 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 76 #endif 77 78 #endif /* _ASM_CONFIG_H_ */ 79