1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <asm/arch/at91_common.h>
11 #include <asm/arch/clk.h>
12 #include <asm/arch/gpio.h>
13 #include <asm/io.h>
14
15 /*
16 * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
17 * peripheral pins. Good to have if hardware is soldered optionally
18 * or in case of SPI no slave is selected. Avoid lines to float
19 * needlessly. Use a short local PUP define.
20 *
21 * Due to errata "TXD floats when CTS is inactive" pullups are always
22 * on for TXD pins.
23 */
24 #ifdef CONFIG_AT91_GPIO_PULLUP
25 # define PUP CONFIG_AT91_GPIO_PULLUP
26 #else
27 # define PUP 0
28 #endif
29
at91_serial0_hw_init(void)30 void at91_serial0_hw_init(void)
31 {
32 at91_set_a_periph(AT91_PIO_PORTB, 19, 1); /* TXD0 */
33 at91_set_a_periph(AT91_PIO_PORTB, 18, PUP); /* RXD0 */
34 at91_periph_clk_enable(ATMEL_ID_USART0);
35 }
36
at91_serial1_hw_init(void)37 void at91_serial1_hw_init(void)
38 {
39 at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD1 */
40 at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD1 */
41 at91_periph_clk_enable(ATMEL_ID_USART1);
42 }
43
at91_serial2_hw_init(void)44 void at91_serial2_hw_init(void)
45 {
46 at91_set_a_periph(AT91_PIO_PORTD, 6, 1); /* TXD2 */
47 at91_set_a_periph(AT91_PIO_PORTD, 7, PUP); /* RXD2 */
48 at91_periph_clk_enable(ATMEL_ID_USART2);
49 }
50
at91_seriald_hw_init(void)51 void at91_seriald_hw_init(void)
52 {
53 at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* DRXD */
54 at91_set_a_periph(AT91_PIO_PORTB, 13, 1); /* DTXD */
55 at91_periph_clk_enable(ATMEL_ID_SYS);
56 }
57
58 #ifdef CONFIG_ATMEL_SPI
at91_spi0_hw_init(unsigned long cs_mask)59 void at91_spi0_hw_init(unsigned long cs_mask)
60 {
61 at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI0_MISO */
62 at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI0_MOSI */
63 at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI0_SPCK */
64
65 at91_periph_clk_enable(ATMEL_ID_SPI0);
66
67 if (cs_mask & (1 << 0)) {
68 at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
69 }
70 if (cs_mask & (1 << 1)) {
71 at91_set_b_periph(AT91_PIO_PORTB, 18, 1);
72 }
73 if (cs_mask & (1 << 2)) {
74 at91_set_b_periph(AT91_PIO_PORTB, 19, 1);
75 }
76 if (cs_mask & (1 << 3)) {
77 at91_set_b_periph(AT91_PIO_PORTD, 27, 1);
78 }
79 if (cs_mask & (1 << 4)) {
80 at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
81 }
82 if (cs_mask & (1 << 5)) {
83 at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
84 }
85 if (cs_mask & (1 << 6)) {
86 at91_set_pio_output(AT91_PIO_PORTB, 19, 1);
87 }
88 if (cs_mask & (1 << 7)) {
89 at91_set_pio_output(AT91_PIO_PORTD, 27, 1);
90 }
91 }
92
at91_spi1_hw_init(unsigned long cs_mask)93 void at91_spi1_hw_init(unsigned long cs_mask)
94 {
95 at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* SPI1_MISO */
96 at91_set_a_periph(AT91_PIO_PORTB, 15, PUP); /* SPI1_MOSI */
97 at91_set_a_periph(AT91_PIO_PORTB, 16, PUP); /* SPI1_SPCK */
98
99 at91_periph_clk_enable(ATMEL_ID_SPI1);
100
101 if (cs_mask & (1 << 0)) {
102 at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
103 }
104 if (cs_mask & (1 << 1)) {
105 at91_set_b_periph(AT91_PIO_PORTD, 28, 1);
106 }
107 if (cs_mask & (1 << 2)) {
108 at91_set_a_periph(AT91_PIO_PORTD, 18, 1);
109 }
110 if (cs_mask & (1 << 3)) {
111 at91_set_a_periph(AT91_PIO_PORTD, 19, 1);
112 }
113 if (cs_mask & (1 << 4)) {
114 at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
115 }
116 if (cs_mask & (1 << 5)) {
117 at91_set_pio_output(AT91_PIO_PORTD, 28, 1);
118 }
119 if (cs_mask & (1 << 6)) {
120 at91_set_pio_output(AT91_PIO_PORTD, 18, 1);
121 }
122 if (cs_mask & (1 << 7)) {
123 at91_set_pio_output(AT91_PIO_PORTD, 19, 1);
124 }
125
126 }
127 #endif
128
129 #ifdef CONFIG_MACB
at91_macb_hw_init(void)130 void at91_macb_hw_init(void)
131 {
132 at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* ETXCK_EREFCK */
133 at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* ERXDV */
134 at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* ERX0 */
135 at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* ERX1 */
136 at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* ERXER */
137 at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* ETXEN */
138 at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* ETX0 */
139 at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* ETX1 */
140 at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* EMDIO */
141 at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* EMDC */
142 #ifndef CONFIG_RMII
143 at91_set_b_periph(AT91_PIO_PORTA, 29, 0); /* ECRS */
144 at91_set_b_periph(AT91_PIO_PORTA, 30, 0); /* ECOL */
145 at91_set_b_periph(AT91_PIO_PORTA, 8, 0); /* ERX2 */
146 at91_set_b_periph(AT91_PIO_PORTA, 9, 0); /* ERX3 */
147 at91_set_b_periph(AT91_PIO_PORTA, 28, 0); /* ERXCK */
148 at91_set_b_periph(AT91_PIO_PORTA, 6, 0); /* ETX2 */
149 at91_set_b_periph(AT91_PIO_PORTA, 7, 0); /* ETX3 */
150 at91_set_b_periph(AT91_PIO_PORTA, 27, 0); /* ETXER */
151 #endif
152 }
153 #endif
154
155 #ifdef CONFIG_GENERIC_ATMEL_MCI
at91_mci_hw_init(void)156 void at91_mci_hw_init(void)
157 {
158 at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* MCI0 CLK */
159 at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* MCI0 CDA */
160 at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* MCI0 DA0 */
161 at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* MCI0 DA1 */
162 at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* MCI0 DA2 */
163 at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* MCI0 DA3 */
164
165 at91_periph_clk_enable(ATMEL_ID_MCI0);
166 }
167 #endif
168
169 /* Platform data for the GPIOs */
170 static const struct at91_port_plat at91sam9260_plat[] = {
171 { ATMEL_BASE_PIOA, "PA" },
172 { ATMEL_BASE_PIOB, "PB" },
173 { ATMEL_BASE_PIOC, "PC" },
174 { ATMEL_BASE_PIOD, "PD" },
175 { ATMEL_BASE_PIOE, "PE" },
176 };
177
178 U_BOOT_DRVINFOS(at91sam9260_gpios) = {
179 { "atmel_at91rm9200_gpio", &at91sam9260_plat[0] },
180 { "atmel_at91rm9200_gpio", &at91sam9260_plat[1] },
181 { "atmel_at91rm9200_gpio", &at91sam9260_plat[2] },
182 { "atmel_at91rm9200_gpio", &at91sam9260_plat[3] },
183 { "atmel_at91rm9200_gpio", &at91sam9260_plat[4] },
184 };
185