1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * mcf5329.h -- Definitions for Freescale Coldfire 5329
4  *
5  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7  */
8 
9 #ifndef mcf5235_h
10 #define mcf5235_h
11 /****************************************************************************/
12 
13 /*********************************************************************
14 * System Control Module (SCM)
15 *********************************************************************/
16 
17 /* Bit definition and macros for SCM_IPSBAR */
18 #define SCM_IPSBAR_BA(x)		(((x)&0x03)<<30)
19 #define SCM_IPSBAR_V			(0x00000001)
20 
21 /* Bit definition and macros for SCM_RAMBAR */
22 #define SCM_RAMBAR_BA(x)		(((x)&0xFFFF)<<16)
23 #define SCM_RAMBAR_BDE			(0x00000200)
24 
25 /* Bit definition and macros for SCM_CRSR */
26 #define SCM_CRSR_EXT			(0x80)
27 
28 /* Bit definitions and macros for SCM_CWCR */
29 #define SCM_CWCR_CWE			(0x80)
30 #define SCM_CWCR_CWRI			(0x40)
31 #define SCM_CWCR_CWT(x)			(((x)&0x07)<<3)
32 #define SCM_CWCR_CWTA			(0x04)
33 #define SCM_CWCR_CWTAVAL		(0x02)
34 #define SCM_CWCR_CWTIC			(0x01)
35 
36 /* Bit definitions and macros for SCM_LPICR */
37 #define SCM_LPICR_ENBSTOP		(0x80)
38 #define SCM_LPICR_XLPM_IPL(x)		(((x)&0x07)<<4)
39 #define SCM_LPICR_XLPM_IPL_ANY		(0x00)
40 #define SCM_LPICR_XLPM_IPL_L2_7		(0x10)
41 #define SCM_LPICR_XLPM_IPL_L3_7		(0x20)
42 #define SCM_LPICR_XLPM_IPL_L4_7		(0x30)
43 #define SCM_LPICR_XLPM_IPL_L5_7		(0x40)
44 #define SCM_LPICR_XLPM_IPL_L6_7		(0x50)
45 #define SCM_LPICR_XLPM_IPL_L7		(0x70)
46 
47 /* Bit definitions and macros for SCM_DMAREQC */
48 #define SCM_DMAREQC_EXT(x)		(((x)&0x0F)<<16)
49 #define SCM_DMAREQC_EXT_ETPU		(0x00080000)
50 #define SCM_DMAREQC_EXT_EXTDREQ2	(0x00040000)
51 #define SCM_DMAREQC_EXT_EXTDREQ1	(0x00020000)
52 #define SCM_DMAREQC_EXT_EXTDREQ0	(0x00010000)
53 #define SCM_DMAREQC_DMAC3(x)		(((x)&0x0F)<<12)
54 #define SCM_DMAREQC_DMAC2(x)		(((x)&0x0F)<<8)
55 #define SCM_DMAREQC_DMAC1(x)		(((x)&0x0F)<<4)
56 #define SCM_DMAREQC_DMAC0(x)		(((x)&0x0F))
57 #define SCM_DMAREQC_DMACn_DTMR0		(0x04)
58 #define SCM_DMAREQC_DMACn_DTMR1		(0x05)
59 #define SCM_DMAREQC_DMACn_DTMR2		(0x06)
60 #define SCM_DMAREQC_DMACn_DTMR3		(0x07)
61 #define SCM_DMAREQC_DMACn_UART0RX	(0x08)
62 #define SCM_DMAREQC_DMACn_UART1RX	(0x09)
63 #define SCM_DMAREQC_DMACn_UART2RX	(0x0A)
64 #define SCM_DMAREQC_DMACn_UART0TX	(0x0C)
65 #define SCM_DMAREQC_DMACn_UART1TX	(0x0D)
66 #define SCM_DMAREQC_DMACn_UART3TX	(0x0E)
67 
68 /* Bit definitions and macros for SCM_MPARK */
69 #define SCM_MPARK_M2_P_EN		(0x02000000)
70 #define SCM_MPARK_M3_PRTY_MSK		(0x00C00000)
71 #define SCM_MPARK_M3_PRTY_4TH		(0x00000000)
72 #define SCM_MPARK_M3_PRTY_3RD		(0x00400000)
73 #define SCM_MPARK_M3_PRTY_2ND		(0x00800000)
74 #define SCM_MPARK_M3_PRTY_1ST		(0x00C00000)
75 #define SCM_MPARK_M2_PRTY_MSK		(0x00300000)
76 #define SCM_MPARK_M2_PRTY_4TH		(0x00000000)
77 #define SCM_MPARK_M2_PRTY_3RD		(0x00100000)
78 #define SCM_MPARK_M2_PRTY_2ND		(0x00200000)
79 #define SCM_MPARK_M2_PRTY_1ST		(0x00300000)
80 #define SCM_MPARK_M0_PRTY_MSK		(0x000C0000)
81 #define SCM_MPARK_M0_PRTY_4TH		(0x00000000)
82 #define SCM_MPARK_M0_PRTY_3RD		(0x00040000)
83 #define SCM_MPARK_M0_PRTY_2ND		(0x00080000)
84 #define SCM_MPARK_M0_PRTY_1ST		(0x000C0000)
85 #define SCM_MPARK_FIXED			(0x00004000)
86 #define SCM_MPARK_TIMEOUT		(0x00002000)
87 #define SCM_MPARK_PRKLAST		(0x00001000)
88 #define SCM_MPARK_LCKOUT_TIME(x)	(((x)&0x0F)<<8)
89 
90 /* Bit definitions and macros for SCM_MPR */
91 #define SCM_MPR_MPR3			(0x08)
92 #define SCM_MPR_MPR2			(0x04)
93 #define SCM_MPR_MPR1			(0x02)
94 #define SCM_MPR_MPR0			(0x01)
95 
96 /* Bit definitions and macros for SCM_PACRn */
97 #define SCM_PACRn_LOCK1			(0x80)
98 #define SCM_PACRn_ACCESSCTRL1(x)	(((x)&0x07)<<4)
99 #define SCM_PACRn_LOCK0			(0x08)
100 #define SCM_PACRn_ACCESSCTRL0(x)	(((x)&0x07))
101 
102 /* Bit definitions and macros for SCM_GPACR */
103 #define SCM_PACRn_LOCK			(0x80)
104 #define SCM_PACRn_ACCESSCTRL0(x)	(((x)&0x07))
105 
106 /*********************************************************************
107 * SDRAM Controller (SDRAMC)
108 *********************************************************************/
109 /* Bit definitions and macros for SDRAMC_DCR */
110 #define SDRAMC_DCR_NAM			(0x2000)
111 #define SDRAMC_DCR_COC			(0x1000)
112 #define SDRAMC_DCR_IS			(0x0800)
113 #define SDRAMC_DCR_RTIM_MASK		(0x0C00)
114 #define SDRAMC_DCR_RTIM_3CLKS		(0x0000)
115 #define SDRAMC_DCR_RTIM_6CLKS		(0x0200)
116 #define SDRAMC_DCR_RTIM_9CLKS		(0x0400)
117 #define SDRAMC_DCR_RC(x)		(((x)&0xFF)<<8)
118 
119 /* Bit definitions and macros for SDRAMC_DARCn */
120 #define SDRAMC_DARCn_BA(x)		((x)&0xFFFC0000)
121 #define SDRAMC_DARCn_RE			(0x00008000)
122 #define SDRAMC_DARCn_CASL_MASK		(0x00003000)
123 #define SDRAMC_DARCn_CASL_C0		(0x00000000)
124 #define SDRAMC_DARCn_CASL_C1		(0x00001000)
125 #define SDRAMC_DARCn_CASL_C2		(0x00002000)
126 #define SDRAMC_DARCn_CASL_C3		(0x00003000)
127 #define SDRAMC_DARCn_CBM_MASK		(0x00000700)
128 #define SDRAMC_DARCn_CBM_CMD17		(0x00000000)
129 #define SDRAMC_DARCn_CBM_CMD18		(0x00000100)
130 #define SDRAMC_DARCn_CBM_CMD19		(0x00000200)
131 #define SDRAMC_DARCn_CBM_CMD20		(0x00000300)
132 #define SDRAMC_DARCn_CBM_CMD21		(0x00000400)
133 #define SDRAMC_DARCn_CBM_CMD22		(0x00000500)
134 #define SDRAMC_DARCn_CBM_CMD23		(0x00000600)
135 #define SDRAMC_DARCn_CBM_CMD24		(0x00000700)
136 #define SDRAMC_DARCn_IMRS		(0x00000040)
137 #define SDRAMC_DARCn_PS_MASK		(0x00000030)
138 #define SDRAMC_DARCn_PS_32		(0x00000000)
139 #define SDRAMC_DARCn_PS_16		(0x00000010)
140 #define SDRAMC_DARCn_PS_8		(0x00000020)
141 #define SDRAMC_DARCn_IP			(0x00000008)
142 
143 /* Bit definitions and macros for SDRAMC_DMRn */
144 #define SDRAMC_DMRn_BAM(x)		(((x)&0x3FFF)<<18)
145 #define SDRAMC_DMRn_WP			(0x00000100)
146 #define SDRAMC_DMRn_V			(0x00000001)
147 
148 /*********************************************************************
149 * Interrupt Controller (INTC)
150 *********************************************************************/
151 #define INT0_LO_RSVD0			(0)
152 #define INT0_LO_EPORT1			(1)
153 #define INT0_LO_EPORT2			(2)
154 #define INT0_LO_EPORT3			(3)
155 #define INT0_LO_EPORT4			(4)
156 #define INT0_LO_EPORT5			(5)
157 #define INT0_LO_EPORT6			(6)
158 #define INT0_LO_EPORT7			(7)
159 #define INT0_LO_SCM			(8)
160 #define INT0_LO_DMA0			(9)
161 #define INT0_LO_DMA1			(10)
162 #define INT0_LO_DMA2			(11)
163 #define INT0_LO_DMA3			(12)
164 #define INT0_LO_UART0			(13)
165 #define INT0_LO_UART1			(14)
166 #define INT0_LO_UART2			(15)
167 #define INT0_LO_RSVD1			(16)
168 #define INT0_LO_I2C			(17)
169 #define INT0_LO_QSPI			(18)
170 #define INT0_LO_DTMR0			(19)
171 #define INT0_LO_DTMR1			(20)
172 #define INT0_LO_DTMR2			(21)
173 #define INT0_LO_DTMR3			(22)
174 #define INT0_LO_FEC_TXF			(23)
175 #define INT0_LO_FEC_TXB			(24)
176 #define INT0_LO_FEC_UN			(25)
177 #define INT0_LO_FEC_RL			(26)
178 #define INT0_LO_FEC_RXF			(27)
179 #define INT0_LO_FEC_RXB			(28)
180 #define INT0_LO_FEC_MII			(29)
181 #define INT0_LO_FEC_LC			(30)
182 #define INT0_LO_FEC_HBERR		(31)
183 #define INT0_HI_FEC_GRA			(32)
184 #define INT0_HI_FEC_EBERR		(33)
185 #define INT0_HI_FEC_BABT		(34)
186 #define INT0_HI_FEC_BABR		(35)
187 #define INT0_HI_PIT0			(36)
188 #define INT0_HI_PIT1			(37)
189 #define INT0_HI_PIT2			(38)
190 #define INT0_HI_PIT3			(39)
191 #define INT0_HI_RNG			(40)
192 #define INT0_HI_SKHA			(41)
193 #define INT0_HI_MDHA			(42)
194 #define INT0_HI_CAN1_BUF0I		(43)
195 #define INT0_HI_CAN1_BUF1I		(44)
196 #define INT0_HI_CAN1_BUF2I		(45)
197 #define INT0_HI_CAN1_BUF3I		(46)
198 #define INT0_HI_CAN1_BUF4I		(47)
199 #define INT0_HI_CAN1_BUF5I		(48)
200 #define INT0_HI_CAN1_BUF6I		(49)
201 #define INT0_HI_CAN1_BUF7I		(50)
202 #define INT0_HI_CAN1_BUF8I		(51)
203 #define INT0_HI_CAN1_BUF9I		(52)
204 #define INT0_HI_CAN1_BUF10I		(53)
205 #define INT0_HI_CAN1_BUF11I		(54)
206 #define INT0_HI_CAN1_BUF12I		(55)
207 #define INT0_HI_CAN1_BUF13I		(56)
208 #define INT0_HI_CAN1_BUF14I		(57)
209 #define INT0_HI_CAN1_BUF15I		(58)
210 #define INT0_HI_CAN1_ERRINT		(59)
211 #define INT0_HI_CAN1_BOFFINT		(60)
212 /* 60-63 Reserved */
213 
214 /* 0 - 7 Reserved */
215 #define INT1_LO_CAN1_BUF0I		(8)
216 #define INT1_LO_CAN1_BUF1I		(9)
217 #define INT1_LO_CAN1_BUF2I		(10)
218 #define INT1_LO_CAN1_BUF3I		(11)
219 #define INT1_LO_CAN1_BUF4I		(12)
220 #define INT1_LO_CAN1_BUF5I		(13)
221 #define INT1_LO_CAN1_BUF6I		(14)
222 #define INT1_LO_CAN1_BUF7I		(15)
223 #define INT1_LO_CAN1_BUF8I		(16)
224 #define INT1_LO_CAN1_BUF9I		(17)
225 #define INT1_LO_CAN1_BUF10I		(18)
226 #define INT1_LO_CAN1_BUF11I		(19)
227 #define INT1_LO_CAN1_BUF12I		(20)
228 #define INT1_LO_CAN1_BUF13I		(21)
229 #define INT1_LO_CAN1_BUF14I		(22)
230 #define INT1_LO_CAN1_BUF15I		(23)
231 #define INT1_LO_CAN1_ERRINT		(24)
232 #define INT1_LO_CAN1_BOFFINT		(25)
233 /* 26 Reserved */
234 #define INT1_LO_ETPU_TC0F		(27)
235 #define INT1_LO_ETPU_TC1F		(28)
236 #define INT1_LO_ETPU_TC2F		(29)
237 #define INT1_LO_ETPU_TC3F		(30)
238 #define INT1_LO_ETPU_TC4F		(31)
239 #define INT1_HI_ETPU_TC5F		(32)
240 #define INT1_HI_ETPU_TC6F		(33)
241 #define INT1_HI_ETPU_TC7F		(34)
242 #define INT1_HI_ETPU_TC8F		(35)
243 #define INT1_HI_ETPU_TC9F		(36)
244 #define INT1_HI_ETPU_TC10F		(37)
245 #define INT1_HI_ETPU_TC11F		(38)
246 #define INT1_HI_ETPU_TC12F		(39)
247 #define INT1_HI_ETPU_TC13F		(40)
248 #define INT1_HI_ETPU_TC14F		(41)
249 #define INT1_HI_ETPU_TC15F		(42)
250 #define INT1_HI_ETPU_TC16F		(43)
251 #define INT1_HI_ETPU_TC17F		(44)
252 #define INT1_HI_ETPU_TC18F		(45)
253 #define INT1_HI_ETPU_TC19F		(46)
254 #define INT1_HI_ETPU_TC20F		(47)
255 #define INT1_HI_ETPU_TC21F		(48)
256 #define INT1_HI_ETPU_TC22F		(49)
257 #define INT1_HI_ETPU_TC23F		(50)
258 #define INT1_HI_ETPU_TC24F		(51)
259 #define INT1_HI_ETPU_TC25F		(52)
260 #define INT1_HI_ETPU_TC26F		(53)
261 #define INT1_HI_ETPU_TC27F		(54)
262 #define INT1_HI_ETPU_TC28F		(55)
263 #define INT1_HI_ETPU_TC29F		(56)
264 #define INT1_HI_ETPU_TC30F		(57)
265 #define INT1_HI_ETPU_TC31F		(58)
266 #define INT1_HI_ETPU_TGIF		(59)
267 
268 /*********************************************************************
269 * General Purpose I/O (GPIO)
270 *********************************************************************/
271 /* Bit definitions and macros for GPIO_PODR */
272 #define GPIO_PODR_ADDR(x)		(((x)&0x07)<<5)
273 #define GPIO_PODR_ADDR_MASK		(0xE0)
274 #define GPIO_PODR_BS(x)			((x)&0x0F)
275 #define GPIO_PODR_BS_MASK		(0x0F)
276 #define GPIO_PODR_CS(x)			(((x)&0x7F)<<1)
277 #define GPIO_PODR_CS_MASK		(0xFE)
278 #define GPIO_PODR_SDRAM(X)		((x)&0x3F)
279 #define GPIO_PODR_SDRAM_MASK		(0x3F)
280 #define GPIO_PODR_FECI2C(x)		GPIO_PODR_BS(x)
281 #define GPIO_PODR_FECI2C_MASK		GPIO_PODR_BS_MASK
282 #define GPIO_PODR_UARTH(x)		((x)&0x03)
283 #define GPIO_PODR_UARTH_MASK		(0x03)
284 #define GPIO_PODR_QSPI(x)		((x)&0x1F)
285 #define GPIO_PODR_QSPI_MASK		(0x1F)
286 #define GPIO_PODR_ETPU(x)		((x)&0x07)
287 #define GPIO_PODR_ETPU_MASK		(0x07)
288 
289 /* Bit definitions and macros for GPIO_PDDR */
290 #define GPIO_PDDR_ADDR(x)		GPIO_PODR_ADDR(x)
291 #define GPIO_PDDR_ADDR_MASK		GPIO_PODR_ADDR_MASK
292 #define GPIO_PDDR_BS(x)			GPIO_PODR_BS(x)
293 #define GPIO_PDDR_BS_MASK		GPIO_PODR_BS_MASK
294 #define GPIO_PDDR_CS(x)			GPIO_PODR_CS(x)
295 #define GPIO_PDDR_CS_MASK		GPIO_PODR_CS_MASK
296 #define GPIO_PDDR_SDRAM(X)		GPIO_PODR_SDRAM(X)
297 #define GPIO_PDDR_SDRAM_MASK		GPIO_PODR_SDRAM_MASK
298 #define GPIO_PDDR_FECI2C(x)		GPIO_PDDR_BS(x)
299 #define GPIO_PDDR_FECI2C_MASK		GPIO_PDDR_BS_MASK
300 #define GPIO_PDDR_UARTH(x)		GPIO_PODR_UARTH(x)
301 #define GPIO_PDDR_UARTH_MASK		GPIO_PODR_UARTH_MASK
302 #define GPIO_PDDR_QSPI(x)		GPIO_PODR_QSPI(x)
303 #define GPIO_PDDR_QSPI_MASK		GPIO_PODR_QSPI_MASK
304 #define GPIO_PDDR_ETPU(x)		GPIO_PODR_ETPU(x)
305 #define GPIO_PDDR_ETPU_MASK		GPIO_PODR_ETPU_MASK
306 
307 /* Bit definitions and macros for GPIO_PPDSDR */
308 #define GPIO_PPDSDR_ADDR(x)		GPIO_PODR_ADDR(x)
309 #define GPIO_PPDSDR_ADDR_MASK		GPIO_PODR_ADDR_MASK
310 #define GPIO_PPDSDR_BS(x)		GPIO_PODR_BS(x)
311 #define GPIO_PPDSDR_BS_MASK		GPIO_PODR_BS_MASK
312 #define GPIO_PPDSDR_CS(x)		GPIO_PODR_CS(x)
313 #define GPIO_PPDSDR_CS_MASK		GPIO_PODR_CS_MASK
314 #define GPIO_PPDSDR_SDRAM(X)		GPIO_PODR_SDRAM(X)
315 #define GPIO_PPDSDR_SDRAM_MASK		GPIO_PODR_SDRAM_MASK
316 #define GPIO_PPDSDR_FECI2C(x)		GPIO_PPDSDR_BS(x)
317 #define GPIO_PPDSDR_FECI2C_MASK		GPIO_PPDSDR_BS_MASK
318 #define GPIO_PPDSDR_UARTH(x)		GPIO_PODR_UARTH(x)
319 #define GPIO_PPDSDR_UARTH_MASK		GPIO_PODR_UARTH_MASK
320 #define GPIO_PPDSDR_QSPI(x)		GPIO_PODR_QSPI(x)
321 #define GPIO_PPDSDR_QSPI_MASK		GPIO_PODR_QSPI_MASK
322 #define GPIO_PPDSDR_ETPU(x)		GPIO_PODR_ETPU(x)
323 #define GPIO_PPDSDR_ETPU_MASK		GPIO_PODR_ETPU_MASK
324 
325 /* Bit definitions and macros for GPIO_PCLRR */
326 #define GPIO_PCLRR_ADDR(x)		GPIO_PODR_ADDR(x)
327 #define GPIO_PCLRR_ADDR_MASK		GPIO_PODR_ADDR_MASK
328 #define GPIO_PCLRR_BS(x)		GPIO_PODR_BS(x)
329 #define GPIO_PCLRR_BS_MASK		GPIO_PODR_BS_MASK
330 #define GPIO_PCLRR_CS(x)		GPIO_PODR_CS(x)
331 #define GPIO_PCLRR_CS_MASK		GPIO_PODR_CS_MASK
332 #define GPIO_PCLRR_SDRAM(X)		GPIO_PODR_SDRAM(X)
333 #define GPIO_PCLRR_SDRAM_MASK		GPIO_PODR_SDRAM_MASK
334 #define GPIO_PCLRR_FECI2C(x)		GPIO_PCLRR_BS(x)
335 #define GPIO_PCLRR_FECI2C_MASK		GPIO_PCLRR_BS_MASK
336 #define GPIO_PCLRR_UARTH(x)		GPIO_PODR_UARTH(x)
337 #define GPIO_PCLRR_UARTH_MASK		GPIO_PODR_UARTH_MASK
338 #define GPIO_PCLRR_QSPI(x)		GPIO_PODR_QSPI(x)
339 #define GPIO_PCLRR_QSPI_MASK		GPIO_PODR_QSPI_MASK
340 #define GPIO_PCLRR_ETPU(x)		GPIO_PODR_ETPU(x)
341 #define GPIO_PCLRR_ETPU_MASK		GPIO_PODR_ETPU_MASK
342 
343 /* Bit definitions and macros for GPIO_PAR */
344 #define GPIO_PAR_AD_ADDR23		(0x80)
345 #define GPIO_PAR_AD_ADDR22		(0x40)
346 #define GPIO_PAR_AD_ADDR21		(0x20)
347 #define GPIO_PAR_AD_DATAL		(0x01)
348 #define GPIO_PAR_BUSCTL_OE		(0x4000)
349 #define GPIO_PAR_BUSCTL_TA		(0x1000)
350 #define GPIO_PAR_BUSCTL_TEA(x)		(((x)&0x03)<<10)
351 #define GPIO_PAR_BUSCTL_TEA_MASK	(0x0C00)
352 #define GPIO_PAR_BUSCTL_TEA_GPIO	(0x0400)
353 #define GPIO_PAR_BUSCTL_TEA_DREQ1	(0x0800)
354 #define GPIO_PAR_BUSCTL_TEA_EXTBUS	(0x0C00)
355 #define GPIO_PAR_BUSCTL_RWB		(0x0100)
356 #define GPIO_PAR_BUSCTL_TSIZ1		(0x0040)
357 #define GPIO_PAR_BUSCTL_TSIZ0		(0x0010)
358 #define GPIO_PAR_BUSCTL_TS(x)		(((x)&0x03)<<2)
359 #define GPIO_PAR_BUSCTL_TS_MASK		(0x0C)
360 #define GPIO_PAR_BUSCTL_TS_GPIO		(0x04)
361 #define GPIO_PAR_BUSCTL_TS_DACK2	(0x08)
362 #define GPIO_PAR_BUSCTL_TS_EXTBUS	(0x0C)
363 #define GPIO_PAR_BUSCTL_TIP(x)		((x)&0x03)
364 #define GPIO_PAR_BUSCTL_TIP_MASK	(0x03)
365 #define GPIO_PAR_BUSCTL_TIP_GPIO	(0x01)
366 #define GPIO_PAR_BUSCTL_TIP_DREQ0	(0x02)
367 #define GPIO_PAR_BUSCTL_TIP_EXTBUS	(0x03)
368 #define GPIO_PAR_BS(x)			((x)&0x0F)
369 #define GPIO_PAR_BS_MASK		(0x0F)
370 #define GPIO_PAR_CS(x)			(((x)&0x7F)<<1)
371 #define GPIO_PAR_CS_MASK		(0xFE)
372 #define GPIO_PAR_CS_CS7			(0x80)
373 #define GPIO_PAR_CS_CS6			(0x40)
374 #define GPIO_PAR_CS_CS5			(0x20)
375 #define GPIO_PAR_CS_CS4			(0x10)
376 #define GPIO_PAR_CS_CS3			(0x08)
377 #define GPIO_PAR_CS_CS2			(0x04)
378 #define GPIO_PAR_CS_CS1			(0x02)
379 #define GPIO_PAR_CS_SD3			GPIO_PAR_CS_CS3
380 #define GPIO_PAR_CS_SD2			GPIO_PAR_CS_CS2
381 #define GPIO_PAR_SDRAM_CSSDCS(x)	(((x)&0x03)<<6)
382 #define GPIO_PAR_SDRAM_CSSDCS_MASK	(0xC0)
383 #define GPIO_PAR_SDRAM_SDWE		(0x20)
384 #define GPIO_PAR_SDRAM_SCAS		(0x10)
385 #define GPIO_PAR_SDRAM_SRAS		(0x08)
386 #define GPIO_PAR_SDRAM_SCKE		(0x04)
387 #define GPIO_PAR_SDRAM_SDCS(x)		((x)&0x03)
388 #define GPIO_PAR_SDRAM_SDCS_MASK	(0x03)
389 #define GPIO_PAR_FECI2C_EMDC(x)		(((x)&0x03)<<6)
390 #define GPIO_PAR_FECI2C_EMDC_MASK	(0xC0)
391 #define GPIO_PAR_FECI2C_EMDC_U2TXD	(0x40)
392 #define GPIO_PAR_FECI2C_EMDC_I2CSCL	(0x80)
393 #define GPIO_PAR_FECI2C_EMDC_FECEMDC	(0xC0)
394 #define GPIO_PAR_FECI2C_EMDIO(x)	(((x)&0x03)<<4)
395 #define GPIO_PAR_FECI2C_EMDIO_MASK	(0x30)
396 #define GPIO_PAR_FECI2C_EMDIO_U2RXD	(0x10)
397 #define GPIO_PAR_FECI2C_EMDIO_I2CSDA	(0x20)
398 #define GPIO_PAR_FECI2C_EMDIO_FECEMDIO	(0x30)
399 #define GPIO_PAR_FECI2C_SCL(x)		(((x)&0x03)<<2)
400 #define GPIO_PAR_FECI2C_SCL_MASK	(0x0C)
401 #define GPIO_PAR_FECI2C_SCL_CAN0RX	(0x08)
402 #define GPIO_PAR_FECI2C_SCL_I2CSCL	(0x0C)
403 #define GPIO_PAR_FECI2C_SDA(x)		((x)&0x03)
404 #define GPIO_PAR_FECI2C_SDA_MASK	(0x03)
405 #define GPIO_PAR_FECI2C_SDA_CAN0TX	(0x02)
406 #define GPIO_PAR_FECI2C_SDA_I2CSDA	(0x03)
407 #define GPIO_PAR_UART_DREQ2		(0x8000)
408 #define GPIO_PAR_UART_CAN1EN		(0x4000)
409 #define GPIO_PAR_UART_U2RXD		(0x2000)
410 #define GPIO_PAR_UART_U2TXD		(0x1000)
411 #define GPIO_PAR_UART_U1RXD(x)		(((x)&0x03)<<10)
412 #define GPIO_PAR_UART_U1RXD_MASK	(0x0C00)
413 #define GPIO_PAR_UART_U1RXD_CAN0RX	(0x0800)
414 #define GPIO_PAR_UART_U1RXD_U1RXD	(0x0C00)
415 #define GPIO_PAR_UART_U1TXD(x)		(((x)&0x03)<<8)
416 #define GPIO_PAR_UART_U1TXD_MASK	(0x0300)
417 #define GPIO_PAR_UART_U1TXD_CAN0TX	(0x0200)
418 #define GPIO_PAR_UART_U1TXD_U1TXD	(0x0300)
419 #define GPIO_PAR_UART_U1CTS(x)		(((x)&0x03)<<6)
420 #define GPIO_PAR_UART_U1CTS_MASK	(0x00C0)
421 #define GPIO_PAR_UART_U1CTS_U2CTS	(0x0080)
422 #define GPIO_PAR_UART_U1CTS_U1CTS	(0x00C0)
423 #define GPIO_PAR_UART_U1RTS(x)		(((x)&0x03)<<4)
424 #define GPIO_PAR_UART_U1RTS_MASK	(0x0030)
425 #define GPIO_PAR_UART_U1RTS_U2RTS	(0x0020)
426 #define GPIO_PAR_UART_U1RTS_U1RTS	(0x0030)
427 #define GPIO_PAR_UART_U0RXD		(0x0008)
428 #define GPIO_PAR_UART_U0TXD		(0x0004)
429 #define GPIO_PAR_UART_U0CTS		(0x0002)
430 #define GPIO_PAR_UART_U0RTS		(0x0001)
431 #define GPIO_PAR_QSPI_CS1(x)		(((x)&0x03)<<6)
432 #define GPIO_PAR_QSPI_CS1_MASK		(0xC0)
433 #define GPIO_PAR_QSPI_CS1_SDRAMSCKE	(0x80)
434 #define GPIO_PAR_QSPI_CS1_QSPICS1	(0xC0)
435 #define GPIO_PAR_QSPI_CS0		(0x20)
436 #define GPIO_PAR_QSPI_DIN(x)		(((x)&0x03)<<3)
437 #define GPIO_PAR_QSPI_DIN_MASK		(0x18)
438 #define GPIO_PAR_QSPI_DIN_I2CSDA	(0x10)
439 #define GPIO_PAR_QSPI_DIN_QSPIDIN	(0x18)
440 #define GPIO_PAR_QSPI_DOUT		(0x04)
441 #define GPIO_PAR_QSPI_SCK(x)		((x)&0x03)
442 #define GPIO_PAR_QSPI_SCK_MASK		(0x03)
443 #define GPIO_PAR_QSPI_SCK_I2CSCL	(0x02)
444 #define GPIO_PAR_QSPI_SCK_QSPISCK	(0x03)
445 #define GPIO_PAR_DT3IN(x)		(((x)&0x03)<<14)
446 #define GPIO_PAR_DT3IN_MASK		(0xC000)
447 #define GPIO_PAR_DT3IN_QSPICS2		(0x4000)
448 #define GPIO_PAR_DT3IN_U2CTS		(0x8000)
449 #define GPIO_PAR_DT3IN_DT3IN		(0xC000)
450 #define GPIO_PAR_DT2IN(x)		(((x)&0x03)<<12)
451 #define GPIO_PAR_DT2IN_MASK		(0x3000)
452 #define GPIO_PAR_DT2IN_DT2OUT		(0x1000)
453 #define GPIO_PAR_DT2IN_DREQ2		(0x2000)
454 #define GPIO_PAR_DT2IN_DT2IN		(0x3000)
455 #define GPIO_PAR_DT1IN(x)		(((x)&0x03)<<10)
456 #define GPIO_PAR_DT1IN_MASK		(0x0C00)
457 #define GPIO_PAR_DT1IN_DT1OUT		(0x0400)
458 #define GPIO_PAR_DT1IN_DREQ1		(0x0800)
459 #define GPIO_PAR_DT1IN_DT1IN		(0x0C00)
460 #define GPIO_PAR_DT0IN(x)		(((x)&0x03)<<8)
461 #define GPIO_PAR_DT0IN_MASK		(0x0300)
462 #define GPIO_PAR_DT0IN_DREQ0		(0x0200)
463 #define GPIO_PAR_DT0IN_DT0IN		(0x0300)
464 #define GPIO_PAR_DT3OUT(x)		(((x)&0x03)<<6)
465 #define GPIO_PAR_DT3OUT_MASK		(0x00C0)
466 #define GPIO_PAR_DT3OUT_QSPICS3		(0x0040)
467 #define GPIO_PAR_DT3OUT_U2RTS		(0x0080)
468 #define GPIO_PAR_DT3OUT_DT3OUT		(0x00C0)
469 #define GPIO_PAR_DT2OUT(x)		(((x)&0x03)<<4)
470 #define GPIO_PAR_DT2OUT_MASK		(0x0030)
471 #define GPIO_PAR_DT2OUT_DACK2		(0x0020)
472 #define GPIO_PAR_DT2OUT_DT2OUT		(0x0030)
473 #define GPIO_PAR_DT1OUT(x)		(((x)&0x03)<<2)
474 #define GPIO_PAR_DT1OUT_MASK		(0x000C)
475 #define GPIO_PAR_DT1OUT_DACK1		(0x0008)
476 #define GPIO_PAR_DT1OUT_DT1OUT		(0x000C)
477 #define GPIO_PAR_DT0OUT(x)		((x)&0x03)
478 #define GPIO_PAR_DT0OUT_MASK		(0x0003)
479 #define GPIO_PAR_DT0OUT_DACK0		(0x0002)
480 #define GPIO_PAR_DT0OUT_DT0OUT		(0x0003)
481 #define GPIO_PAR_ETPU_TCRCLK		(0x04)
482 #define GPIO_PAR_ETPU_UTPU_ODIS		(0x02)
483 #define GPIO_PAR_ETPU_LTPU_ODIS		(0x01)
484 
485 /* Bit definitions and macros for GPIO_DSCR */
486 #define GPIO_DSCR_EIM_EIM1		(0x10)
487 #define GPIO_DSCR_EIM_EIM0		(0x01)
488 #define GPIO_DSCR_ETPU_ETPU31_24	(0x40)
489 #define GPIO_DSCR_ETPU_ETPU23_16	(0x10)
490 #define GPIO_DSCR_ETPU_ETPU15_8		(0x04)
491 #define GPIO_DSCR_ETPU_ETPU7_0		(0x01)
492 #define GPIO_DSCR_FECI2C_FEC		(0x10)
493 #define GPIO_DSCR_FECI2C_I2C		(0x01)
494 #define GPIO_DSCR_UART_IRQ		(0x40)
495 #define GPIO_DSCR_UART_UART2		(0x10)
496 #define GPIO_DSCR_UART_UART1		(0x04)
497 #define GPIO_DSCR_UART_UART0		(0x01)
498 #define GPIO_DSCR_QSPI_QSPI		(0x01)
499 #define GPIO_DSCR_TIMER			(0x01)
500 
501 /*********************************************************************
502 * Chip Configuration Module (CCM)
503 *********************************************************************/
504 /* Bit definitions and macros for CCM_RCR */
505 #define CCM_RCR_SOFTRST			(0x80)
506 #define CCM_RCR_FRCRSTOUT		(0x40)
507 
508 /* Bit definitions and macros for CCM_RSR */
509 #define CCM_RSR_SOFT			(0x20)
510 #define CCM_RSR_WDR			(0x10)
511 #define CCM_RSR_POR			(0x08)
512 #define CCM_RSR_EXT			(0x04)
513 #define CCM_RSR_LOC			(0x02)
514 #define CCM_RSR_LOL			(0x01)
515 
516 /* Bit definitions and macros for CCM_CCR */
517 #define CCM_CCR_LOAD			(0x8000)
518 #define CCM_CCR_SZEN			(0x0040)
519 #define CCM_CCR_PSTEN			(0x0020)
520 #define CCM_CCR_BME			(0x0008)
521 #define CCM_CCR_BMT(x)			((x)&0x07)
522 #define CCM_CCR_BMT_MASK		(0x0007)
523 #define CCM_CCR_BMT_64K			(0x0000)
524 #define CCM_CCR_BMT_32K			(0x0001)
525 #define CCM_CCR_BMT_16K			(0x0002)
526 #define CCM_CCR_BMT_8K			(0x0003)
527 #define CCM_CCR_BMT_4K			(0x0004)
528 #define CCM_CCR_BMT_2K			(0x0005)
529 #define CCM_CCR_BMT_1K			(0x0006)
530 #define CCM_CCR_BMT_512			(0x0007)
531 
532 /* Bit definitions and macros for CCM_RCON */
533 #define CCM_RCON_RCSC(x)		(((x)&0x0003)<<8)
534 #define CCM_RCON_RLOAD			(0x0020)
535 #define CCM_RCON_BOOTPS(x)		(((x)&0x0003)<<3)
536 #define CCM_RCON_BOOTPS_MASK		(0x0018)
537 #define CCM_RCON_BOOTPS_32		(0x0018)
538 #define CCM_RCON_BOOTPS_16		(0x0008)
539 #define CCM_RCON_BOOTPS_8		(0x0010)
540 #define CCM_RCON_MODE			(0x0001)
541 
542 /* Bit definitions and macros for CCM_CIR */
543 #define CCM_CIR_PIN(x)			(((x) & 0xFFC0) >> 6)
544 #define CCM_CIR_PRN(x)			((x) & 0x003F)
545 
546 /*********************************************************************
547 * PLL Clock Module
548 *********************************************************************/
549 /* Bit definitions and macros for PLL_SYNCR */
550 #define PLL_SYNCR_MFD(x)		(((x)&0x07)<<24)
551 #define PLL_SYNCR_MFD_MASK		(0x07000000)
552 #define PLL_SYNCR_RFC(x)		(((x)&0x07)<<19)
553 #define PLL_SYNCR_RFC_MASK		(0x00380000)
554 #define PLL_SYNCR_LOCEN			(0x00040000)
555 #define PLL_SYNCR_LOLRE			(0x00020000)
556 #define PLL_SYNCR_LOCRE			(0x00010000)
557 #define PLL_SYNCR_DISCLK		(0x00008000)
558 #define PLL_SYNCR_LOLIRQ		(0x00004000)
559 #define PLL_SYNCR_LOCIRQ		(0x00002000)
560 #define PLL_SYNCR_RATE			(0x00001000)
561 #define PLL_SYNCR_DEPTH(x)		(((x)&0x03)<<10)
562 #define PLL_SYNCR_EXP(x)		((x)&0x03FF)
563 
564 /* Bit definitions and macros for PLL_SYNSR */
565 #define PLL_SYNSR_LOLF			(0x00000200)
566 #define PLL_SYNSR_LOC			(0x00000100)
567 #define PLL_SYNSR_MODE			(0x00000080)
568 #define PLL_SYNSR_PLLSEL		(0x00000040)
569 #define PLL_SYNSR_PLLREF		(0x00000020)
570 #define PLL_SYNSR_LOCKS			(0x00000010)
571 #define PLL_SYNSR_LOCK			(0x00000008)
572 #define PLL_SYNSR_LOCF			(0x00000004)
573 #define PLL_SYNSR_CALDONE		(0x00000002)
574 #define PLL_SYNSR_CALPASS		(0x00000001)
575 
576 /*********************************************************************
577 * Watchdog Timer Modules (WTM)
578 *********************************************************************/
579 /* Bit definitions and macros for WTM_WCR */
580 #define WTM_WCR_WAIT			(0x0008)
581 #define WTM_WCR_DOZE			(0x0004)
582 #define WTM_WCR_HALTED			(0x0002)
583 #define WTM_WCR_EN			(0x0001)
584 
585 #endif				/* mcf5235_h */
586