1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * uart.h -- ColdFire internal UART support defines.
4  *
5  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7  */
8 
9 /****************************************************************************/
10 #ifndef	uart_h
11 #define	uart_h
12 /****************************************************************************/
13 
14 /* UART module registers */
15 /* Register read/write struct */
16 typedef struct uart {
17 	u8 umr;			/* 0x00 Mode Register */
18 	u8 resv0[0x3];
19 	union {
20 		u8 usr;		/* 0x04 Status Register */
21 		u8 ucsr;	/* 0x04 Clock Select Register */
22 	};
23 	u8 resv1[0x3];
24 	u8 ucr;			/* 0x08 Command Register */
25 	u8 resv2[0x3];
26 	union {
27 		u8 utb;		/* 0x0c Transmit Buffer */
28 		u8 urb;		/* 0x0c Receive Buffer */
29 	};
30 	u8 resv3[0x3];
31 	union {
32 		u8 uipcr;	/* 0x10 Input Port Change Register */
33 		u8 uacr;	/* 0x10 Auxiliary Control reg */
34 	};
35 	u8 resv4[0x3];
36 	union {
37 		u8 uimr;	/* 0x14 Interrupt Mask reg */
38 		u8 uisr;	/* 0x14 Interrupt Status reg */
39 	};
40 	u8 resv5[0x3];
41 	u8 ubg1;		/* 0x18 Counter Timer Upper Register */
42 	u8 resv6[0x3];
43 	u8 ubg2;		/* 0x1c Counter Timer Lower Register */
44 	u8 resv7[0x17];
45 	u8 uip;			/* 0x34 Input Port Register */
46 	u8 resv8[0x3];
47 	u8 uop1;		/* 0x38 Output Port Set Register */
48 	u8 resv9[0x3];
49 	u8 uop0;		/* 0x3c Output Port Reset Register */
50 } uart_t;
51 
52 /*********************************************************************
53 * Universal Asynchronous Receiver Transmitter (UART)
54 *********************************************************************/
55 /* Bit definitions and macros for UMR */
56 #define UART_UMR_BC(x)			(((x)&0x03))
57 #define UART_UMR_PT			(0x04)
58 #define UART_UMR_PM(x)			(((x)&0x03)<<3)
59 #define UART_UMR_ERR			(0x20)
60 #define UART_UMR_RXIRQ			(0x40)
61 #define UART_UMR_RXRTS			(0x80)
62 #define UART_UMR_SB(x)			(((x)&0x0F))
63 #define UART_UMR_TXCTS			(0x10)	/* Trsnsmit CTS */
64 #define UART_UMR_TXRTS			(0x20)	/* Transmit RTS */
65 #define UART_UMR_CM(x)			(((x)&0x03)<<6)	/* CM bits */
66 #define UART_UMR_PM_MULTI_ADDR		(0x1C)
67 #define UART_UMR_PM_MULTI_DATA		(0x18)
68 #define UART_UMR_PM_NONE		(0x10)
69 #define UART_UMR_PM_FORCE_HI		(0x0C)
70 #define UART_UMR_PM_FORCE_LO		(0x08)
71 #define UART_UMR_PM_ODD			(0x04)
72 #define UART_UMR_PM_EVEN		(0x00)
73 #define UART_UMR_BC_5			(0x00)
74 #define UART_UMR_BC_6			(0x01)
75 #define UART_UMR_BC_7			(0x02)
76 #define UART_UMR_BC_8			(0x03)
77 #define UART_UMR_CM_NORMAL		(0x00)
78 #define UART_UMR_CM_ECH			(0x40)
79 #define UART_UMR_CM_LOCAL_LOOP		(0x80)
80 #define UART_UMR_CM_REMOTE_LOOP		(0xC0)
81 #define UART_UMR_SB_STOP_BITS_1		(0x07)
82 #define UART_UMR_SB_STOP_BITS_15	(0x08)
83 #define UART_UMR_SB_STOP_BITS_2		(0x0F)
84 
85 /* Bit definitions and macros for USR */
86 #define UART_USR_RXRDY			(0x01)
87 #define UART_USR_FFULL			(0x02)
88 #define UART_USR_TXRDY			(0x04)
89 #define UART_USR_TXEMP			(0x08)
90 #define UART_USR_OE			(0x10)
91 #define UART_USR_PE			(0x20)
92 #define UART_USR_FE			(0x40)
93 #define UART_USR_RB			(0x80)
94 
95 /* Bit definitions and macros for UCSR */
96 #define UART_UCSR_TCS(x)		(((x)&0x0F))
97 #define UART_UCSR_RCS(x)		(((x)&0x0F)<<4)
98 #define UART_UCSR_RCS_SYS_CLK		(0xD0)
99 #define UART_UCSR_RCS_CTM16		(0xE0)
100 #define UART_UCSR_RCS_CTM		(0xF0)
101 #define UART_UCSR_TCS_SYS_CLK		(0x0D)
102 #define UART_UCSR_TCS_CTM16		(0x0E)
103 #define UART_UCSR_TCS_CTM		(0x0F)
104 
105 /* Bit definitions and macros for UCR */
106 #define UART_UCR_RXC(x)			(((x)&0x03))
107 #define UART_UCR_TXC(x)			(((x)&0x03)<<2)
108 #define UART_UCR_MISC(x)		(((x)&0x07)<<4)
109 #define UART_UCR_NONE			(0x00)
110 #define UART_UCR_STOP_BREAK		(0x70)
111 #define UART_UCR_START_BREAK		(0x60)
112 #define UART_UCR_BKCHGINT		(0x50)
113 #define UART_UCR_RESET_ERROR		(0x40)
114 #define UART_UCR_RESET_TX		(0x30)
115 #define UART_UCR_RESET_RX		(0x20)
116 #define UART_UCR_RESET_MR		(0x10)
117 #define UART_UCR_TX_DISABLED		(0x08)
118 #define UART_UCR_TX_ENABLED		(0x04)
119 #define UART_UCR_RX_DISABLED		(0x02)
120 #define UART_UCR_RX_ENABLED		(0x01)
121 
122 /* Bit definitions and macros for UIPCR */
123 #define UART_UIPCR_CTS			(0x01)
124 #define UART_UIPCR_COS			(0x10)
125 
126 /* Bit definitions and macros for UACR */
127 #define UART_UACR_IEC			(0x01)
128 
129 /* Bit definitions and macros for UIMR */
130 #define UART_UIMR_TXRDY			(0x01)
131 #define UART_UIMR_RXRDY_FU		(0x02)
132 #define UART_UIMR_DB			(0x04)
133 #define UART_UIMR_COS			(0x80)
134 
135 /* Bit definitions and macros for UISR */
136 #define UART_UISR_TXRDY			(0x01)
137 #define UART_UISR_RXRDY_FU		(0x02)
138 #define UART_UISR_DB			(0x04)
139 #define UART_UISR_RXFTO			(0x08)
140 #define UART_UISR_TXFIFO		(0x10)
141 #define UART_UISR_RXFIFO		(0x20)
142 #define UART_UISR_COS			(0x80)
143 
144 /* Bit definitions and macros for UIP */
145 #define UART_UIP_CTS			(0x01)
146 
147 /* Bit definitions and macros for UOP1 */
148 #define UART_UOP1_RTS			(0x01)
149 
150 /* Bit definitions and macros for UOP0 */
151 #define UART_UOP0_RTS			(0x01)
152 
153 /****************************************************************************/
154 #endif				/* mcfuart_h */
155