1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * Author: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
5 */
6
7 /*
8 * This file handles the board muxing between the Fman Ethernet MACs and
9 * the RGMII/SGMII/XGMII PHYs on a Freescale P5040 "Super Hydra" reference
10 * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
11 * provided by the standard Freescale four-port SGMII riser card. The 10Gb
12 * XGMII PHYs are provided via the XAUI riser card. The P5040 has 2 FMans
13 * and 5 1G interfaces and 10G interface per FMan. Based on the options in
14 * the RCW, we could have upto 3 SGMII cards and 1 XAUI card at a time.
15 *
16 * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control
17 * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is
18 * always the same (0). The value for SGMII depends on which slot the riser is
19 * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII,
20 * the value is based on which slot the XAUI is inserted in.
21 *
22 * The SERDES configuration is used to determine where the SGMII and XAUI cards
23 * exist, and also which Fman's MACs are routed to which PHYs. So for a given
24 * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed
25 * to PHYs dynamically.
26 *
27 *
28 * This file also updates the device tree in three ways:
29 *
30 * 1) The status of each virtual MDIO node that is referenced by an Ethernet
31 * node is set to "okay".
32 *
33 * 2) The phy-handle property of each active Ethernet MAC node is set to the
34 * appropriate PHY node.
35 *
36 * 3) The "mux value" for each virtual MDIO node is set to the correct value,
37 * if necessary. Some virtual MDIO nodes do not have configurable mux
38 * values, so those values are hard-coded in the DTS. On the HYDRA board,
39 * the virtual MDIO node for the SGMII card needs to be updated.
40 *
41 * For all this to work, the device tree needs to have the following:
42 *
43 * 1) An alias for each PHY node that an Ethernet node could be routed to.
44 *
45 * 2) An alias for each real and virtual MDIO node that is disabled by default
46 * and might need to be enabled, and also might need to have its mux-value
47 * updated.
48 */
49
50 #include <common.h>
51 #include <log.h>
52 #include <net.h>
53 #include <netdev.h>
54 #include <asm/fsl_serdes.h>
55 #include <fm_eth.h>
56 #include <fsl_mdio.h>
57 #include <malloc.h>
58 #include <fdt_support.h>
59 #include <fsl_dtsec.h>
60
61 #include "../common/ngpixis.h"
62 #include "../common/fman.h"
63
64 #ifdef CONFIG_FMAN_ENET
65
66 #define BRDCFG1_EMI1_SEL_MASK 0x70
67 #define BRDCFG1_EMI1_SEL_SLOT1 0x10
68 #define BRDCFG1_EMI1_SEL_SLOT2 0x20
69 #define BRDCFG1_EMI1_SEL_SLOT5 0x30
70 #define BRDCFG1_EMI1_SEL_SLOT6 0x40
71 #define BRDCFG1_EMI1_SEL_SLOT7 0x50
72 #define BRDCFG1_EMI1_SEL_SLOT3 0x60
73 #define BRDCFG1_EMI1_SEL_RGMII 0x00
74 #define BRDCFG1_EMI1_EN 0x08
75 #define BRDCFG1_EMI2_SEL_MASK 0x06
76 #define BRDCFG1_EMI2_SEL_SLOT1 0x00
77 #define BRDCFG1_EMI2_SEL_SLOT2 0x02
78
79 #define BRDCFG2_REG_GPIO_SEL 0x20
80
81 /* SGMII */
82 #define PHY_BASE_ADDR 0x00
83 #define REGNUM 0x00
84 #define PORT_NUM_FM1 0x04
85 #define PORT_NUM_FM2 0x02
86
87 /*
88 * BRDCFG1 mask and value for each MAC
89 *
90 * This array contains the BRDCFG1 values (in mask/val format) that route the
91 * MDIO bus to a particular RGMII or SGMII PHY.
92 */
93 static struct {
94 u8 mask;
95 u8 val;
96 } mdio_mux[NUM_FM_PORTS];
97
98 /*
99 * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
100 * that the mapping must be determined dynamically, or that the lane maps to
101 * something other than a board slot
102 */
103 static u8 lane_to_slot[] = {
104 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0, 0, 0
105 };
106
107 /*
108 * Set the board muxing for a given MAC
109 *
110 * The MDIO layer calls this function every time it wants to talk to a PHY.
111 */
super_hydra_mux_mdio(u8 mask,u8 val)112 void super_hydra_mux_mdio(u8 mask, u8 val)
113 {
114 clrsetbits_8(&pixis->brdcfg1, mask, val);
115 }
116
117 struct super_hydra_mdio {
118 u8 mask;
119 u8 val;
120 struct mii_dev *realbus;
121 };
122
super_hydra_mdio_read(struct mii_dev * bus,int addr,int devad,int regnum)123 static int super_hydra_mdio_read(struct mii_dev *bus, int addr, int devad,
124 int regnum)
125 {
126 struct super_hydra_mdio *priv = bus->priv;
127
128 super_hydra_mux_mdio(priv->mask, priv->val);
129
130 return priv->realbus->read(priv->realbus, addr, devad, regnum);
131 }
132
super_hydra_mdio_write(struct mii_dev * bus,int addr,int devad,int regnum,u16 value)133 static int super_hydra_mdio_write(struct mii_dev *bus, int addr, int devad,
134 int regnum, u16 value)
135 {
136 struct super_hydra_mdio *priv = bus->priv;
137
138 super_hydra_mux_mdio(priv->mask, priv->val);
139
140 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
141 }
142
super_hydra_mdio_reset(struct mii_dev * bus)143 static int super_hydra_mdio_reset(struct mii_dev *bus)
144 {
145 struct super_hydra_mdio *priv = bus->priv;
146
147 return priv->realbus->reset(priv->realbus);
148 }
149
super_hydra_mdio_set_mux(char * name,u8 mask,u8 val)150 static void super_hydra_mdio_set_mux(char *name, u8 mask, u8 val)
151 {
152 struct mii_dev *bus = miiphy_get_dev_by_name(name);
153 struct super_hydra_mdio *priv = bus->priv;
154
155 priv->mask = mask;
156 priv->val = val;
157 }
158
super_hydra_mdio_init(char * realbusname,char * fakebusname)159 static int super_hydra_mdio_init(char *realbusname, char *fakebusname)
160 {
161 struct super_hydra_mdio *hmdio;
162 struct mii_dev *bus = mdio_alloc();
163
164 if (!bus) {
165 printf("Failed to allocate Hydra MDIO bus\n");
166 return -1;
167 }
168
169 hmdio = malloc(sizeof(*hmdio));
170 if (!hmdio) {
171 printf("Failed to allocate Hydra private data\n");
172 free(bus);
173 return -1;
174 }
175
176 bus->read = super_hydra_mdio_read;
177 bus->write = super_hydra_mdio_write;
178 bus->reset = super_hydra_mdio_reset;
179 strcpy(bus->name, fakebusname);
180
181 hmdio->realbus = miiphy_get_dev_by_name(realbusname);
182
183 if (!hmdio->realbus) {
184 printf("No bus with name %s\n", realbusname);
185 free(bus);
186 free(hmdio);
187 return -1;
188 }
189
190 bus->priv = hmdio;
191
192 return mdio_register(bus);
193 }
194
195 /*
196 * Given the following ...
197 *
198 * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
199 * compatible string and 'addr' physical address)
200 *
201 * 2) An Fman port
202 *
203 * ... update the phy-handle property of the Ethernet node to point to the
204 * right PHY. This assumes that we already know the PHY for each port. That
205 * information is stored in mdio_mux[].
206 *
207 * The offset of the Fman Ethernet node is also passed in for convenience, but
208 * it is not used.
209 *
210 * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
211 * Inside the Fman, "ports" are things that connect to MACs. We only call them
212 * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
213 * and ports are the same thing.
214 */
board_ft_fman_fixup_port(void * fdt,char * compat,phys_addr_t addr,enum fm_port port,int offset)215 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
216 enum fm_port port, int offset)
217 {
218 enum srds_prtcl device;
219 int lane, slot, phy;
220 char alias[32];
221
222 /* RGMII and XGMII are already mapped correctly in the DTS */
223
224 if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
225 device = serdes_device_from_fm_port(port);
226 lane = serdes_get_first_lane(device);
227 slot = lane_to_slot[lane];
228 phy = fm_info_get_phy_address(port);
229
230 sprintf(alias, "phy_sgmii_slot%u_%x", slot, phy);
231 fdt_set_phy_handle(fdt, compat, addr, alias);
232 }
233 }
234
235 #define PIXIS_SW2_LANE_23_SEL 0x80
236 #define PIXIS_SW2_LANE_45_SEL 0x40
237 #define PIXIS_SW2_LANE_67_SEL_MASK 0x30
238 #define PIXIS_SW2_LANE_67_SEL_5 0x00
239 #define PIXIS_SW2_LANE_67_SEL_6 0x20
240 #define PIXIS_SW2_LANE_67_SEL_7 0x10
241 #define PIXIS_SW2_LANE_8_SEL 0x08
242 #define PIXIS_SW2_LANE_1617_SEL 0x04
243 #define PIXIS_SW11_LANE_9_SEL 0x04
244 /*
245 * Initialize the lane_to_slot[] array.
246 *
247 * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board
248 * slots is hard-coded. On the Hydra board, however, the mapping is controlled
249 * by board switch SW2, so the lane_to_slot[] array needs to be dynamically
250 * initialized.
251 */
initialize_lane_to_slot(void)252 static void initialize_lane_to_slot(void)
253 {
254 u8 sw2 = in_8(&PIXIS_SW(2));
255 /* SW11 appears in the programming model as SW9 */
256 u8 sw11 = in_8(&PIXIS_SW(9));
257
258 lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4;
259 lane_to_slot[3] = lane_to_slot[2];
260
261 lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6;
262 lane_to_slot[5] = lane_to_slot[4];
263
264 switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) {
265 case PIXIS_SW2_LANE_67_SEL_5:
266 lane_to_slot[6] = 5;
267 break;
268 case PIXIS_SW2_LANE_67_SEL_6:
269 lane_to_slot[6] = 6;
270 break;
271 case PIXIS_SW2_LANE_67_SEL_7:
272 lane_to_slot[6] = 7;
273 break;
274 }
275 lane_to_slot[7] = lane_to_slot[6];
276
277 lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0;
278 lane_to_slot[9] = (sw11 & PIXIS_SW11_LANE_9_SEL) ? 0 : 3;
279
280 lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0;
281 lane_to_slot[17] = lane_to_slot[16];
282 }
283
284 #endif /* #ifdef CONFIG_FMAN_ENET */
285
286 /*
287 * Configure the status for the virtual MDIO nodes
288 *
289 * Rather than create the virtual MDIO nodes from scratch for each active
290 * virtual MDIO, we expect the DTS to have the nodes defined already, and we
291 * only enable the ones that are actually active.
292 *
293 * We assume that the DTS already hard-codes the status for all the
294 * virtual MDIO nodes to "disabled", so all we need to do is enable the
295 * active ones.
296 */
fdt_fixup_board_enet(void * fdt)297 void fdt_fixup_board_enet(void *fdt)
298 {
299 #ifdef CONFIG_FMAN_ENET
300 enum fm_port i;
301 int lane, slot;
302
303 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
304 int idx = i - FM1_DTSEC1;
305
306 switch (fm_info_get_enet_if(i)) {
307 case PHY_INTERFACE_MODE_SGMII:
308 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
309 if (lane >= 0) {
310 char alias[32];
311
312 slot = lane_to_slot[lane];
313 sprintf(alias, "hydra_sg_slot%u", slot);
314 fdt_status_okay_by_alias(fdt, alias);
315 debug("Enabled MDIO node %s (slot %i)\n",
316 alias, slot);
317 }
318 break;
319 case PHY_INTERFACE_MODE_RGMII:
320 case PHY_INTERFACE_MODE_RGMII_TXID:
321 case PHY_INTERFACE_MODE_RGMII_RXID:
322 case PHY_INTERFACE_MODE_RGMII_ID:
323 fdt_status_okay_by_alias(fdt, "hydra_rg");
324 debug("Enabled MDIO node hydra_rg\n");
325 break;
326 default:
327 break;
328 }
329 }
330
331 lane = serdes_get_first_lane(XAUI_FM1);
332 if (lane >= 0) {
333 char alias[32];
334
335 slot = lane_to_slot[lane];
336 sprintf(alias, "hydra_xg_slot%u", slot);
337 fdt_status_okay_by_alias(fdt, alias);
338 debug("Enabled MDIO node %s (slot %i)\n", alias, slot);
339 }
340
341 #if CONFIG_SYS_NUM_FMAN == 2
342 for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
343 int idx = i - FM2_DTSEC1;
344
345 switch (fm_info_get_enet_if(i)) {
346 case PHY_INTERFACE_MODE_SGMII:
347 lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
348 if (lane >= 0) {
349 char alias[32];
350
351 slot = lane_to_slot[lane];
352 sprintf(alias, "hydra_sg_slot%u", slot);
353 fdt_status_okay_by_alias(fdt, alias);
354 debug("Enabled MDIO node %s (slot %i)\n",
355 alias, slot);
356 }
357 break;
358 case PHY_INTERFACE_MODE_RGMII:
359 case PHY_INTERFACE_MODE_RGMII_TXID:
360 case PHY_INTERFACE_MODE_RGMII_RXID:
361 case PHY_INTERFACE_MODE_RGMII_ID:
362 fdt_status_okay_by_alias(fdt, "hydra_rg");
363 debug("Enabled MDIO node hydra_rg\n");
364 break;
365 default:
366 break;
367 }
368 }
369
370 lane = serdes_get_first_lane(XAUI_FM2);
371 if (lane >= 0) {
372 char alias[32];
373
374 slot = lane_to_slot[lane];
375 sprintf(alias, "hydra_xg_slot%u", slot);
376 fdt_status_okay_by_alias(fdt, alias);
377 debug("Enabled MDIO node %s (slot %i)\n", alias, slot);
378 }
379 #endif /* CONFIG_SYS_NUM_FMAN == 2 */
380 #endif /* CONFIG_FMAN_ENET */
381 }
382
383 /*
384 * Mapping of SerDes Protocol to MDIO MUX value and PHY address.
385 *
386 * Fman 1:
387 * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4
388 * Mux Phy | Mux Phy | Mux Phy | Mux Phy
389 * Value Addr | Value Addr | Value Addr | Value Addr
390 * 0x00 2 1c | 2 1d | 2 1e | 2 1f
391 * 0x01 | | 6 1c |
392 * 0x02 | | 3 1c | 3 1d
393 * 0x03 2 1c | 2 1d | 2 1e | 2 1f
394 * 0x04 2 1c | 2 1d | 2 1e | 2 1f
395 * 0x05 | | 3 1c | 3 1d
396 * 0x06 2 1c | 2 1d | 2 1e | 2 1f
397 * 0x07 | | 6 1c |
398 * 0x11 2 1c | 2 1d | 2 1e | 2 1f
399 * 0x2a 2 | | 2 1e | 2 1f
400 * 0x34 6 1c | 6 1d | 4 1e | 4 1f
401 * 0x35 | | 3 1c | 3 1d
402 * 0x36 6 1c | 6 1d | 4 1e | 4 1f
403 * | | |
404 * Fman 2: | | |
405 * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4
406 * EMI1 | EMI1 | EMI1 | EMI1
407 * Mux Phy | Mux Phy | Mux Phy | Mux Phy
408 * Value Addr | Value Addr | Value Addr | Value Addr
409 * 0x00 | | 6 1c | 6 1d
410 * 0x01 | | |
411 * 0x02 | | 6 1c | 6 1d
412 * 0x03 3 1c | 3 1d | 6 1c | 6 1d
413 * 0x04 3 1c | 3 1d | 6 1c | 6 1d
414 * 0x05 | | 6 1c | 6 1d
415 * 0x06 | | 6 1c | 6 1d
416 * 0x07 | | |
417 * 0x11 | | |
418 * 0x2a | | |
419 * 0x34 | | |
420 * 0x35 | | |
421 * 0x36 | | |
422 */
423
board_eth_init(struct bd_info * bis)424 int board_eth_init(struct bd_info *bis)
425 {
426 #ifdef CONFIG_FMAN_ENET
427 struct fsl_pq_mdio_info dtsec_mdio_info;
428 struct tgec_mdio_info tgec_mdio_info;
429 unsigned int i, slot;
430 int lane;
431 struct mii_dev *bus;
432 int qsgmii;
433 int phy_real_addr;
434 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
435 int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
436 FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
437
438 printf("Initializing Fman\n");
439
440 initialize_lane_to_slot();
441
442 /* We want to use the PIXIS to configure MUX routing, not GPIOs. */
443 setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL);
444
445 memset(mdio_mux, 0, sizeof(mdio_mux));
446
447 dtsec_mdio_info.regs =
448 (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
449 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
450
451 /* Register the real 1G MDIO bus */
452 fsl_pq_mdio_init(bis, &dtsec_mdio_info);
453
454 tgec_mdio_info.regs =
455 (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
456 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
457
458 /* Register the real 10G MDIO bus */
459 fm_tgec_mdio_init(bis, &tgec_mdio_info);
460
461 /* Register the three virtual MDIO front-ends */
462 super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
463 "SUPER_HYDRA_RGMII_MDIO");
464 super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
465 "SUPER_HYDRA_FM1_SGMII_MDIO");
466 super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
467 "SUPER_HYDRA_FM2_SGMII_MDIO");
468 super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
469 "SUPER_HYDRA_FM3_SGMII_MDIO");
470 super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME,
471 "SUPER_HYDRA_FM1_TGEC_MDIO");
472 super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME,
473 "SUPER_HYDRA_FM2_TGEC_MDIO");
474
475 /*
476 * Program the DTSEC PHY addresses assuming that they are all SGMII.
477 * For any DTSEC that's RGMII, we'll override its PHY address later.
478 * We assume that DTSEC5 is only used for RGMII.
479 */
480 fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
481 fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
482 fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
483
484 #if (CONFIG_SYS_NUM_FMAN == 2)
485 fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
486 fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
487 fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
488 fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
489 fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
490 #endif
491
492 switch (srds_prtcl) {
493 case 0:
494 case 3:
495 case 4:
496 case 6:
497 case 0x11:
498 case 0x2a:
499 case 0x34:
500 case 0x36:
501 fm_info_set_phy_address(FM1_DTSEC3,
502 CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
503 fm_info_set_phy_address(FM1_DTSEC4,
504 CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
505 break;
506 case 1:
507 case 2:
508 case 5:
509 case 7:
510 case 0x35:
511 fm_info_set_phy_address(FM1_DTSEC3,
512 CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
513 fm_info_set_phy_address(FM1_DTSEC4,
514 CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
515 break;
516 default:
517 printf("Fman: Unsupport SerDes Protocol 0x%02x\n", srds_prtcl);
518 break;
519 }
520
521 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
522 int idx = i - FM1_DTSEC1;
523
524 switch (fm_info_get_enet_if(i)) {
525 case PHY_INTERFACE_MODE_SGMII:
526 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
527 if (lane < 0)
528 break;
529 slot = lane_to_slot[lane];
530 mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
531 debug("FM1@DTSEC%u expects SGMII in slot %u\n",
532 idx + 1, slot);
533 switch (slot) {
534 case 1:
535 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
536 BRDCFG1_EMI1_EN;
537 break;
538 case 2:
539 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
540 BRDCFG1_EMI1_EN;
541 break;
542 case 3:
543 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 |
544 BRDCFG1_EMI1_EN;
545 break;
546 case 5:
547 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
548 BRDCFG1_EMI1_EN;
549 break;
550 case 6:
551 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
552 BRDCFG1_EMI1_EN;
553 break;
554 case 7:
555 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
556 BRDCFG1_EMI1_EN;
557 break;
558 };
559
560 super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_SGMII_MDIO",
561 mdio_mux[i].mask, mdio_mux[i].val);
562 fm_info_set_mdio(i,
563 miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"));
564 break;
565 case PHY_INTERFACE_MODE_RGMII:
566 case PHY_INTERFACE_MODE_RGMII_TXID:
567 case PHY_INTERFACE_MODE_RGMII_RXID:
568 case PHY_INTERFACE_MODE_RGMII_ID:
569 /*
570 * FM1 DTSEC5 is routed via EC1 to the first on-board
571 * RGMII port. FM2 DTSEC5 is routed via EC2 to the
572 * second on-board RGMII port. The other DTSECs cannot
573 * be routed to RGMII.
574 */
575 debug("FM1@DTSEC%u is RGMII at address %u\n",
576 idx + 1, 0);
577 fm_info_set_phy_address(i, 0);
578 mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
579 mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
580 BRDCFG1_EMI1_EN;
581 super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO",
582 mdio_mux[i].mask, mdio_mux[i].val);
583 fm_info_set_mdio(i,
584 miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
585 break;
586 case PHY_INTERFACE_MODE_NONE:
587 fm_info_set_phy_address(i, 0);
588 break;
589 default:
590 printf("Fman1: DTSEC%u set to unknown interface %i\n",
591 idx + 1, fm_info_get_enet_if(i));
592 fm_info_set_phy_address(i, 0);
593 break;
594 }
595 }
596
597 bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO");
598 qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM_FM1, REGNUM);
599
600 if (qsgmii) {
601 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + PORT_NUM_FM1; i++) {
602 if (fm_info_get_enet_if(i) ==
603 PHY_INTERFACE_MODE_SGMII) {
604 phy_real_addr = PHY_BASE_ADDR + i - FM1_DTSEC1;
605 fm_info_set_phy_address(i, phy_real_addr);
606 }
607 }
608 switch (srds_prtcl) {
609 case 0x00:
610 case 0x03:
611 case 0x04:
612 case 0x06:
613 case 0x11:
614 case 0x2a:
615 case 0x34:
616 case 0x36:
617 fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 2);
618 fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 3);
619 break;
620 case 0x01:
621 case 0x02:
622 case 0x05:
623 case 0x07:
624 case 0x35:
625 fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 0);
626 fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1);
627 break;
628 default:
629 break;
630 }
631 }
632
633 /*
634 * For 10G, we only support one XAUI card per Fman. If present, then we
635 * force its routing and never touch those bits again, which removes the
636 * need for Linux to do any muxing. This works because of the way
637 * BRDCFG1 is defined, but it's a bit hackish.
638 *
639 * The PHY address for the XAUI card depends on which slot it's in. The
640 * macros we use imply that the PHY address is based on which FM, but
641 * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
642 * and FM2 could only use a XAUI in slot 4. On the Hydra board, we
643 * check the actual slot and just use the macros as-is, even though
644 * the P3041 and P5020 only have one Fman.
645 */
646 lane = serdes_get_first_lane(XAUI_FM1);
647 if (lane >= 0) {
648 debug("FM1@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]);
649 mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK;
650 mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT2;
651 super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_TGEC_MDIO",
652 mdio_mux[i].mask, mdio_mux[i].val);
653 }
654
655 fm_info_set_mdio(FM1_10GEC1,
656 miiphy_get_dev_by_name("SUPER_HYDRA_FM1_TGEC_MDIO"));
657
658 #if (CONFIG_SYS_NUM_FMAN == 2)
659 for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
660 int idx = i - FM2_DTSEC1;
661
662 switch (fm_info_get_enet_if(i)) {
663 case PHY_INTERFACE_MODE_SGMII:
664 lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
665 if (lane < 0)
666 break;
667 slot = lane_to_slot[lane];
668 mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
669 debug("FM2@DTSEC%u expects SGMII in slot %u\n",
670 idx + 1, slot);
671 switch (slot) {
672 case 1:
673 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
674 BRDCFG1_EMI1_EN;
675 break;
676 case 2:
677 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
678 BRDCFG1_EMI1_EN;
679 break;
680 case 3:
681 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 |
682 BRDCFG1_EMI1_EN;
683 break;
684 case 5:
685 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
686 BRDCFG1_EMI1_EN;
687 break;
688 case 6:
689 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
690 BRDCFG1_EMI1_EN;
691 break;
692 case 7:
693 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
694 BRDCFG1_EMI1_EN;
695 break;
696 };
697
698 if (i == FM2_DTSEC1 || i == FM2_DTSEC2) {
699 super_hydra_mdio_set_mux(
700 "SUPER_HYDRA_FM3_SGMII_MDIO",
701 mdio_mux[i].mask,
702 mdio_mux[i].val);
703 fm_info_set_mdio(i, miiphy_get_dev_by_name(
704 "SUPER_HYDRA_FM3_SGMII_MDIO"));
705 } else {
706 super_hydra_mdio_set_mux(
707 "SUPER_HYDRA_FM2_SGMII_MDIO",
708 mdio_mux[i].mask,
709 mdio_mux[i].val);
710 fm_info_set_mdio(i, miiphy_get_dev_by_name(
711 "SUPER_HYDRA_FM2_SGMII_MDIO"));
712 }
713
714 break;
715 case PHY_INTERFACE_MODE_RGMII:
716 case PHY_INTERFACE_MODE_RGMII_TXID:
717 case PHY_INTERFACE_MODE_RGMII_RXID:
718 case PHY_INTERFACE_MODE_RGMII_ID:
719 /*
720 * FM1 DTSEC5 is routed via EC1 to the first on-board
721 * RGMII port. FM2 DTSEC5 is routed via EC2 to the
722 * second on-board RGMII port. The other DTSECs cannot
723 * be routed to RGMII.
724 */
725 debug("FM2@DTSEC%u is RGMII at address %u\n",
726 idx + 1, 1);
727 fm_info_set_phy_address(i, 1);
728 mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
729 mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
730 BRDCFG1_EMI1_EN;
731 super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO",
732 mdio_mux[i].mask, mdio_mux[i].val);
733 fm_info_set_mdio(i,
734 miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
735 break;
736 case PHY_INTERFACE_MODE_NONE:
737 fm_info_set_phy_address(i, 0);
738 break;
739 default:
740 printf("Fman2: DTSEC%u set to unknown interface %i\n",
741 idx + 1, fm_info_get_enet_if(i));
742 fm_info_set_phy_address(i, 0);
743 break;
744 }
745 }
746
747 bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM2_SGMII_MDIO");
748 set_sgmii_phy(bus, FM2_DTSEC3, PORT_NUM_FM2, PHY_BASE_ADDR);
749 bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM3_SGMII_MDIO");
750 set_sgmii_phy(bus, FM2_DTSEC1, PORT_NUM_FM2, PHY_BASE_ADDR);
751
752 /*
753 * For 10G, we only support one XAUI card per Fman. If present, then we
754 * force its routing and never touch those bits again, which removes the
755 * need for Linux to do any muxing. This works because of the way
756 * BRDCFG1 is defined, but it's a bit hackish.
757 *
758 * The PHY address for the XAUI card depends on which slot it's in. The
759 * macros we use imply that the PHY address is based on which FM, but
760 * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
761 * and FM2 could only use a XAUI in slot 4. On the Hydra board, we
762 * check the actual slot and just use the macros as-is, even though
763 * the P3041 and P5020 only have one Fman.
764 */
765 lane = serdes_get_first_lane(XAUI_FM2);
766 if (lane >= 0) {
767 debug("FM2@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]);
768 mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK;
769 mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT1;
770 super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_TGEC_MDIO",
771 mdio_mux[i].mask, mdio_mux[i].val);
772 }
773
774 fm_info_set_mdio(FM2_10GEC1,
775 miiphy_get_dev_by_name("SUPER_HYDRA_FM2_TGEC_MDIO"));
776
777 #endif
778
779 cpu_eth_init(bis);
780 #endif
781
782 return pci_eth_init(bis);
783 }
784