1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * board.c
4 *
5 * Board functions for TI AM43XX based boards
6 *
7 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
8 */
9
10 #include <common.h>
11 #include <eeprom.h>
12 #include <image.h>
13 #include <asm/global_data.h>
14 #include <dm/uclass.h>
15 #include <env.h>
16 #include <fdt_support.h>
17 #include <i2c.h>
18 #include <init.h>
19 #include <net.h>
20 #include <linux/errno.h>
21 #include <spl.h>
22 #include <usb.h>
23 #include <asm/omap_sec_common.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm/arch/mux.h>
27 #include <asm/arch/ddr_defs.h>
28 #include <asm/arch/gpio.h>
29 #include <asm/emif.h>
30 #include <asm/omap_common.h>
31 #include "../common/board_detect.h"
32 #include "board.h"
33 #include <power/pmic.h>
34 #include <power/tps65218.h>
35 #include <power/tps62362.h>
36 #include <linux/usb/gadget.h>
37 #include <dwc3-uboot.h>
38 #include <dwc3-omap-uboot.h>
39 #include <ti-usb-phy-uboot.h>
40
41 DECLARE_GLOBAL_DATA_PTR;
42
43 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
44
45 /*
46 * Read header information from EEPROM into global structure.
47 */
48 #ifdef CONFIG_TI_I2C_BOARD_DETECT
do_board_detect(void)49 void do_board_detect(void)
50 {
51 /* Ensure I2C is initialized for EEPROM access*/
52 gpi2c_init();
53 if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
54 CONFIG_EEPROM_CHIP_ADDRESS))
55 printf("ti_i2c_eeprom_init failed\n");
56 }
57 #endif
58
59 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
60
61 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
62 { /* 19.2 MHz */
63 {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
64 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
65 {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */
66 {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */
67 {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */
68 {625, 11, 1, -1, -1, -1, -1} /* OPP NT */
69 },
70 { /* 24 MHz */
71 {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */
72 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
73 {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */
74 {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */
75 {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */
76 {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */
77 },
78 { /* 25 MHz */
79 {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */
80 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
81 {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */
82 {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */
83 {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */
84 {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */
85 },
86 { /* 26 MHz */
87 {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */
88 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
89 {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */
90 {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */
91 {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */
92 {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */
93 },
94 };
95
96 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
97 {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
98 {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */
99 {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */
100 {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */
101 };
102
103 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
104 {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */
105 {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */
106 {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */
107 {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */
108 };
109
110 const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
111 {665, 47, 1, -1, 4, -1, -1}, /*19.2*/
112 {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
113 {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
114 {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */
115 };
116
117 const struct dpll_params gp_evm_dpll_ddr = {
118 50, 2, 1, -1, 2, -1, -1};
119
120 static const struct dpll_params idk_dpll_ddr = {
121 400, 23, 1, -1, 2, -1, -1
122 };
123
124 static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
125 0x00500050,
126 0x00350035,
127 0x00350035,
128 0x00350035,
129 0x00350035,
130 0x00350035,
131 0x00000000,
132 0x00000000,
133 0x00000000,
134 0x00000000,
135 0x00000000,
136 0x00000000,
137 0x00000000,
138 0x00000000,
139 0x00000000,
140 0x00000000,
141 0x00000000,
142 0x00000000,
143 0x40001000,
144 0x08102040
145 };
146
147 const struct ctrl_ioregs ioregs_lpddr2 = {
148 .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
149 .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
150 .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
151 .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
152 .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
153 .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
154 .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
155 .emif_sdram_config_ext = 0x1,
156 };
157
158 const struct emif_regs emif_regs_lpddr2 = {
159 .sdram_config = 0x808012BA,
160 .ref_ctrl = 0x0000040D,
161 .sdram_tim1 = 0xEA86B411,
162 .sdram_tim2 = 0x103A094A,
163 .sdram_tim3 = 0x0F6BA37F,
164 .read_idle_ctrl = 0x00050000,
165 .zq_config = 0x50074BE4,
166 .temp_alert_config = 0x0,
167 .emif_rd_wr_lvl_rmp_win = 0x0,
168 .emif_rd_wr_lvl_rmp_ctl = 0x0,
169 .emif_rd_wr_lvl_ctl = 0x0,
170 .emif_ddr_phy_ctlr_1 = 0x0E284006,
171 .emif_rd_wr_exec_thresh = 0x80000405,
172 .emif_ddr_ext_phy_ctrl_1 = 0x04010040,
173 .emif_ddr_ext_phy_ctrl_2 = 0x00500050,
174 .emif_ddr_ext_phy_ctrl_3 = 0x00500050,
175 .emif_ddr_ext_phy_ctrl_4 = 0x00500050,
176 .emif_ddr_ext_phy_ctrl_5 = 0x00500050,
177 .emif_prio_class_serv_map = 0x80000001,
178 .emif_connect_id_serv_1_map = 0x80000094,
179 .emif_connect_id_serv_2_map = 0x00000000,
180 .emif_cos_config = 0x000FFFFF
181 };
182
183 const struct ctrl_ioregs ioregs_ddr3 = {
184 .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
185 .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
186 .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
187 .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
188 .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
189 .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
190 .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
191 .emif_sdram_config_ext = 0xc163,
192 };
193
194 const struct emif_regs ddr3_emif_regs_400Mhz = {
195 .sdram_config = 0x638413B2,
196 .ref_ctrl = 0x00000C30,
197 .sdram_tim1 = 0xEAAAD4DB,
198 .sdram_tim2 = 0x266B7FDA,
199 .sdram_tim3 = 0x107F8678,
200 .read_idle_ctrl = 0x00050000,
201 .zq_config = 0x50074BE4,
202 .temp_alert_config = 0x0,
203 .emif_ddr_phy_ctlr_1 = 0x0E004008,
204 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
205 .emif_ddr_ext_phy_ctrl_2 = 0x00400040,
206 .emif_ddr_ext_phy_ctrl_3 = 0x00400040,
207 .emif_ddr_ext_phy_ctrl_4 = 0x00400040,
208 .emif_ddr_ext_phy_ctrl_5 = 0x00400040,
209 .emif_rd_wr_lvl_rmp_win = 0x0,
210 .emif_rd_wr_lvl_rmp_ctl = 0x0,
211 .emif_rd_wr_lvl_ctl = 0x0,
212 .emif_rd_wr_exec_thresh = 0x80000405,
213 .emif_prio_class_serv_map = 0x80000001,
214 .emif_connect_id_serv_1_map = 0x80000094,
215 .emif_connect_id_serv_2_map = 0x00000000,
216 .emif_cos_config = 0x000FFFFF
217 };
218
219 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
220 const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
221 .sdram_config = 0x638413B2,
222 .ref_ctrl = 0x00000C30,
223 .sdram_tim1 = 0xEAAAD4DB,
224 .sdram_tim2 = 0x266B7FDA,
225 .sdram_tim3 = 0x107F8678,
226 .read_idle_ctrl = 0x00050000,
227 .zq_config = 0x50074BE4,
228 .temp_alert_config = 0x0,
229 .emif_ddr_phy_ctlr_1 = 0x0E004008,
230 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
231 .emif_ddr_ext_phy_ctrl_2 = 0x00000065,
232 .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
233 .emif_ddr_ext_phy_ctrl_4 = 0x000000B5,
234 .emif_ddr_ext_phy_ctrl_5 = 0x000000E5,
235 .emif_rd_wr_exec_thresh = 0x80000405,
236 .emif_prio_class_serv_map = 0x80000001,
237 .emif_connect_id_serv_1_map = 0x80000094,
238 .emif_connect_id_serv_2_map = 0x00000000,
239 .emif_cos_config = 0x000FFFFF
240 };
241
242 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
243 const struct emif_regs ddr3_emif_regs_400Mhz_production = {
244 .sdram_config = 0x638413B2,
245 .ref_ctrl = 0x00000C30,
246 .sdram_tim1 = 0xEAAAD4DB,
247 .sdram_tim2 = 0x266B7FDA,
248 .sdram_tim3 = 0x107F8678,
249 .read_idle_ctrl = 0x00050000,
250 .zq_config = 0x50074BE4,
251 .temp_alert_config = 0x0,
252 .emif_ddr_phy_ctlr_1 = 0x00048008,
253 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
254 .emif_ddr_ext_phy_ctrl_2 = 0x00000066,
255 .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
256 .emif_ddr_ext_phy_ctrl_4 = 0x000000B9,
257 .emif_ddr_ext_phy_ctrl_5 = 0x000000E6,
258 .emif_rd_wr_exec_thresh = 0x80000405,
259 .emif_prio_class_serv_map = 0x80000001,
260 .emif_connect_id_serv_1_map = 0x80000094,
261 .emif_connect_id_serv_2_map = 0x00000000,
262 .emif_cos_config = 0x000FFFFF
263 };
264
265 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
266 .sdram_config = 0x638413b2,
267 .sdram_config2 = 0x00000000,
268 .ref_ctrl = 0x00000c30,
269 .sdram_tim1 = 0xeaaad4db,
270 .sdram_tim2 = 0x266b7fda,
271 .sdram_tim3 = 0x107f8678,
272 .read_idle_ctrl = 0x00050000,
273 .zq_config = 0x50074be4,
274 .temp_alert_config = 0x0,
275 .emif_ddr_phy_ctlr_1 = 0x0e084008,
276 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
277 .emif_ddr_ext_phy_ctrl_2 = 0x89,
278 .emif_ddr_ext_phy_ctrl_3 = 0x90,
279 .emif_ddr_ext_phy_ctrl_4 = 0x8e,
280 .emif_ddr_ext_phy_ctrl_5 = 0x8d,
281 .emif_rd_wr_lvl_rmp_win = 0x0,
282 .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
283 .emif_rd_wr_lvl_ctl = 0x00000000,
284 .emif_rd_wr_exec_thresh = 0x80000000,
285 .emif_prio_class_serv_map = 0x80000001,
286 .emif_connect_id_serv_1_map = 0x80000094,
287 .emif_connect_id_serv_2_map = 0x00000000,
288 .emif_cos_config = 0x000FFFFF
289 };
290
291 static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
292 .sdram_config = 0x61a11b32,
293 .sdram_config2 = 0x00000000,
294 .ref_ctrl = 0x00000c30,
295 .sdram_tim1 = 0xeaaad4db,
296 .sdram_tim2 = 0x266b7fda,
297 .sdram_tim3 = 0x107f8678,
298 .read_idle_ctrl = 0x00050000,
299 .zq_config = 0x50074be4,
300 .temp_alert_config = 0x00000000,
301 .emif_ddr_phy_ctlr_1 = 0x00008009,
302 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
303 .emif_ddr_ext_phy_ctrl_2 = 0x00000040,
304 .emif_ddr_ext_phy_ctrl_3 = 0x0000003e,
305 .emif_ddr_ext_phy_ctrl_4 = 0x00000051,
306 .emif_ddr_ext_phy_ctrl_5 = 0x00000051,
307 .emif_rd_wr_lvl_rmp_win = 0x00000000,
308 .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
309 .emif_rd_wr_lvl_ctl = 0x00000000,
310 .emif_rd_wr_exec_thresh = 0x00000405,
311 .emif_prio_class_serv_map = 0x00000000,
312 .emif_connect_id_serv_1_map = 0x00000000,
313 .emif_connect_id_serv_2_map = 0x00000000,
314 .emif_cos_config = 0x00ffffff
315 };
316
emif_get_ext_phy_ctrl_const_regs(const u32 ** regs,u32 * size)317 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
318 {
319 if (board_is_eposevm()) {
320 *regs = ext_phy_ctrl_const_base_lpddr2;
321 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
322 }
323
324 return;
325 }
326
get_dpll_ddr_params(void)327 const struct dpll_params *get_dpll_ddr_params(void)
328 {
329 int ind = get_sys_clk_index();
330
331 if (board_is_eposevm())
332 return &epos_evm_dpll_ddr[ind];
333 else if (board_is_evm() || board_is_sk())
334 return &gp_evm_dpll_ddr;
335 else if (board_is_idk())
336 return &idk_dpll_ddr;
337
338 printf(" Board '%s' not supported\n", board_ti_get_name());
339 return NULL;
340 }
341
342
343 /*
344 * get_opp_offset:
345 * Returns the index for safest OPP of the device to boot.
346 * max_off: Index of the MAX OPP in DEV ATTRIBUTE register.
347 * min_off: Index of the MIN OPP in DEV ATTRIBUTE register.
348 * This data is read from dev_attribute register which is e-fused.
349 * A'1' in bit indicates OPP disabled and not available, a '0' indicates
350 * OPP available. Lowest OPP starts with min_off. So returning the
351 * bit with rightmost '0'.
352 */
get_opp_offset(int max_off,int min_off)353 static int get_opp_offset(int max_off, int min_off)
354 {
355 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
356 int opp, offset, i;
357
358 /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
359 opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
360
361 for (i = max_off; i >= min_off; i--) {
362 offset = opp & (1 << i);
363 if (!offset)
364 return i;
365 }
366
367 return min_off;
368 }
369
get_dpll_mpu_params(void)370 const struct dpll_params *get_dpll_mpu_params(void)
371 {
372 int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
373 u32 ind = get_sys_clk_index();
374
375 return &dpll_mpu[ind][opp];
376 }
377
get_dpll_core_params(void)378 const struct dpll_params *get_dpll_core_params(void)
379 {
380 int ind = get_sys_clk_index();
381
382 return &dpll_core[ind];
383 }
384
get_dpll_per_params(void)385 const struct dpll_params *get_dpll_per_params(void)
386 {
387 int ind = get_sys_clk_index();
388
389 return &dpll_per[ind];
390 }
391
scale_vcores_generic(u32 m)392 void scale_vcores_generic(u32 m)
393 {
394 int mpu_vdd, ddr_volt;
395
396 #if !CONFIG_IS_ENABLED(DM_I2C)
397 if (i2c_probe(TPS65218_CHIP_PM))
398 return;
399 #else
400 if (power_tps65218_init(0))
401 return;
402 #endif
403
404 switch (m) {
405 case 1000:
406 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
407 break;
408 case 800:
409 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
410 break;
411 case 720:
412 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
413 break;
414 case 600:
415 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
416 break;
417 case 300:
418 mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
419 break;
420 default:
421 puts("Unknown MPU clock, not scaling\n");
422 return;
423 }
424
425 /* Set DCDC1 (CORE) voltage to 1.1V */
426 if (tps65218_voltage_update(TPS65218_DCDC1,
427 TPS65218_DCDC_VOLT_SEL_1100MV)) {
428 printf("%s failure\n", __func__);
429 return;
430 }
431
432 /* Set DCDC2 (MPU) voltage */
433 if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
434 printf("%s failure\n", __func__);
435 return;
436 }
437
438 if (board_is_eposevm())
439 ddr_volt = TPS65218_DCDC3_VOLT_SEL_1200MV;
440 else
441 ddr_volt = TPS65218_DCDC3_VOLT_SEL_1350MV;
442
443 /* Set DCDC3 (DDR) voltage */
444 if (tps65218_voltage_update(TPS65218_DCDC3, ddr_volt)) {
445 printf("%s failure\n", __func__);
446 return;
447 }
448 }
449
scale_vcores_idk(u32 m)450 void scale_vcores_idk(u32 m)
451 {
452 int mpu_vdd;
453
454 #if !CONFIG_IS_ENABLED(DM_I2C)
455 if (i2c_probe(TPS62362_I2C_ADDR))
456 return;
457 #else
458 if (power_tps62362_init(0))
459 return;
460 #endif
461
462 switch (m) {
463 case 1000:
464 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
465 break;
466 case 800:
467 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
468 break;
469 case 720:
470 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
471 break;
472 case 600:
473 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
474 break;
475 case 300:
476 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
477 break;
478 default:
479 puts("Unknown MPU clock, not scaling\n");
480 return;
481 }
482 /* Set VDD_MPU voltage */
483 if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
484 printf("%s failure\n", __func__);
485 return;
486 }
487 }
gpi2c_init(void)488 void gpi2c_init(void)
489 {
490 /* When needed to be invoked prior to BSS initialization */
491 static bool first_time = true;
492
493 if (first_time) {
494 enable_i2c0_pin_mux();
495 #if !CONFIG_IS_ENABLED(DM_I2C)
496 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
497 CONFIG_SYS_OMAP24_I2C_SLAVE);
498 #endif
499 first_time = false;
500 }
501 }
502
scale_vcores(void)503 void scale_vcores(void)
504 {
505 const struct dpll_params *mpu_params;
506
507 /* Ensure I2C is initialized for PMIC configuration */
508 gpi2c_init();
509
510 /* Get the frequency */
511 mpu_params = get_dpll_mpu_params();
512
513 if (board_is_idk())
514 scale_vcores_idk(mpu_params->m);
515 else
516 scale_vcores_generic(mpu_params->m);
517 }
518
set_uart_mux_conf(void)519 void set_uart_mux_conf(void)
520 {
521 enable_uart0_pin_mux();
522 }
523
set_mux_conf_regs(void)524 void set_mux_conf_regs(void)
525 {
526 enable_board_pin_mux();
527 }
528
enable_vtt_regulator(void)529 static void enable_vtt_regulator(void)
530 {
531 u32 temp;
532
533 /* enable module */
534 writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
535
536 /* enable output for GPIO5_7 */
537 writel(GPIO_SETDATAOUT(7),
538 AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
539 temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
540 temp = temp & ~(GPIO_OE_ENABLE(7));
541 writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
542 }
543
544 enum {
545 RTC_BOARD_EPOS = 1,
546 RTC_BOARD_EVM14,
547 RTC_BOARD_EVM12,
548 RTC_BOARD_GPEVM,
549 RTC_BOARD_SK,
550 };
551
552 /*
553 * In the rtc_only+DRR in self-refresh boot path we have the board type info
554 * in the rtc scratch pad register hence we bypass the costly i2c reads to
555 * eeprom and directly programthe board name string
556 */
rtc_only_update_board_type(u32 btype)557 void rtc_only_update_board_type(u32 btype)
558 {
559 const char *name = "";
560 const char *rev = "1.0";
561
562 switch (btype) {
563 case RTC_BOARD_EPOS:
564 name = "AM43EPOS";
565 break;
566 case RTC_BOARD_EVM14:
567 name = "AM43__GP";
568 rev = "1.4";
569 break;
570 case RTC_BOARD_EVM12:
571 name = "AM43__GP";
572 rev = "1.2";
573 break;
574 case RTC_BOARD_GPEVM:
575 name = "AM43__GP";
576 break;
577 case RTC_BOARD_SK:
578 name = "AM43__SK";
579 break;
580 }
581 ti_i2c_eeprom_am_set(name, rev);
582 }
583
rtc_only_get_board_type(void)584 u32 rtc_only_get_board_type(void)
585 {
586 if (board_is_eposevm())
587 return RTC_BOARD_EPOS;
588 else if (board_is_evm_14_or_later())
589 return RTC_BOARD_EVM14;
590 else if (board_is_evm_12_or_later())
591 return RTC_BOARD_EVM12;
592 else if (board_is_gpevm())
593 return RTC_BOARD_GPEVM;
594 else if (board_is_sk())
595 return RTC_BOARD_SK;
596
597 return 0;
598 }
599
sdram_init(void)600 void sdram_init(void)
601 {
602 /*
603 * EPOS EVM has 1GB LPDDR2 connected to EMIF.
604 * GP EMV has 1GB DDR3 connected to EMIF
605 * along with VTT regulator.
606 */
607 if (board_is_eposevm()) {
608 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
609 } else if (board_is_evm_14_or_later()) {
610 enable_vtt_regulator();
611 config_ddr(0, &ioregs_ddr3, NULL, NULL,
612 &ddr3_emif_regs_400Mhz_production, 0);
613 } else if (board_is_evm_12_or_later()) {
614 enable_vtt_regulator();
615 config_ddr(0, &ioregs_ddr3, NULL, NULL,
616 &ddr3_emif_regs_400Mhz_beta, 0);
617 } else if (board_is_evm()) {
618 enable_vtt_regulator();
619 config_ddr(0, &ioregs_ddr3, NULL, NULL,
620 &ddr3_emif_regs_400Mhz, 0);
621 } else if (board_is_sk()) {
622 config_ddr(400, &ioregs_ddr3, NULL, NULL,
623 &ddr3_sk_emif_regs_400Mhz, 0);
624 } else if (board_is_idk()) {
625 config_ddr(400, &ioregs_ddr3, NULL, NULL,
626 &ddr3_idk_emif_regs_400Mhz, 0);
627 }
628 }
629 #endif
630
631 /* setup board specific PMIC */
power_init_board(void)632 int power_init_board(void)
633 {
634 int rc;
635 #if !CONFIG_IS_ENABLED(DM_I2C)
636 struct pmic *p = NULL;
637 #endif
638 if (board_is_idk()) {
639 rc = power_tps62362_init(0);
640 if (rc)
641 goto done;
642 #if !CONFIG_IS_ENABLED(DM_I2C)
643 p = pmic_get("TPS62362");
644 if (!p || pmic_probe(p))
645 goto done;
646 #endif
647 puts("PMIC: TPS62362\n");
648 } else {
649 rc = power_tps65218_init(0);
650 if (rc)
651 goto done;
652 #if !CONFIG_IS_ENABLED(DM_I2C)
653 p = pmic_get("TPS65218_PMIC");
654 if (!p || pmic_probe(p))
655 goto done;
656 #endif
657 puts("PMIC: TPS65218\n");
658 }
659 done:
660 return 0;
661 }
662
board_init(void)663 int board_init(void)
664 {
665 struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
666 u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
667 modena_init0_bw_integer, modena_init0_watermark_0;
668
669 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
670 gpmc_init();
671
672 /*
673 * Call this to initialize *ctrl again
674 */
675 hw_data_init();
676
677 /* Clear all important bits for DSS errata that may need to be tweaked*/
678 mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
679 MREQPRIO_0_SAB_INIT0_MASK;
680
681 mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
682
683 modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
684 BW_LIMITER_BW_FRAC_MASK;
685
686 modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
687 BW_LIMITER_BW_INT_MASK;
688
689 modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
690 BW_LIMITER_BW_WATERMARK_MASK;
691
692 /* Setting MReq Priority of the DSS*/
693 mreqprio_0 |= 0x77;
694
695 /*
696 * Set L3 Fast Configuration Register
697 * Limiting bandwith for ARM core to 700 MBPS
698 */
699 modena_init0_bw_fractional |= 0x10;
700 modena_init0_bw_integer |= 0x3;
701
702 writel(mreqprio_0, &cdev->mreqprio_0);
703 writel(mreqprio_1, &cdev->mreqprio_1);
704
705 writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
706 writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
707 writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
708
709 return 0;
710 }
711
712 #ifdef CONFIG_BOARD_LATE_INIT
713 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
device_okay(const char * path)714 static int device_okay(const char *path)
715 {
716 int node;
717
718 node = fdt_path_offset(gd->fdt_blob, path);
719 if (node < 0)
720 return 0;
721
722 return fdtdec_get_is_enabled(gd->fdt_blob, node);
723 }
724 #endif
725
board_late_init(void)726 int board_late_init(void)
727 {
728 struct udevice *dev;
729 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
730 set_board_info_env(NULL);
731
732 /*
733 * Default FIT boot on HS devices. Non FIT images are not allowed
734 * on HS devices.
735 */
736 if (get_device_type() == HS_DEVICE)
737 env_set("boot_fit", "1");
738 #endif
739
740 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
741 if (device_okay("/ocp/omap_dwc3@48380000"))
742 enable_usb_clocks(0);
743 if (device_okay("/ocp/omap_dwc3@483c0000"))
744 enable_usb_clocks(1);
745 #endif
746
747 /* Just probe the potentially supported cdce913 device */
748 uclass_get_device_by_name(UCLASS_CLK, "cdce913@65", &dev);
749
750 return 0;
751 }
752 #endif
753
754 #if !CONFIG_IS_ENABLED(DM_USB_GADGET)
755 #ifdef CONFIG_USB_DWC3
756 static struct dwc3_device usb_otg_ss1 = {
757 .maximum_speed = USB_SPEED_HIGH,
758 .base = USB_OTG_SS1_BASE,
759 .tx_fifo_resize = false,
760 .index = 0,
761 };
762
763 static struct dwc3_omap_device usb_otg_ss1_glue = {
764 .base = (void *)USB_OTG_SS1_GLUE_BASE,
765 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
766 .index = 0,
767 };
768
769 static struct ti_usb_phy_device usb_phy1_device = {
770 .usb2_phy_power = (void *)USB2_PHY1_POWER,
771 .index = 0,
772 };
773
774 static struct dwc3_device usb_otg_ss2 = {
775 .maximum_speed = USB_SPEED_HIGH,
776 .base = USB_OTG_SS2_BASE,
777 .tx_fifo_resize = false,
778 .index = 1,
779 };
780
781 static struct dwc3_omap_device usb_otg_ss2_glue = {
782 .base = (void *)USB_OTG_SS2_GLUE_BASE,
783 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
784 .index = 1,
785 };
786
787 static struct ti_usb_phy_device usb_phy2_device = {
788 .usb2_phy_power = (void *)USB2_PHY2_POWER,
789 .index = 1,
790 };
791
usb_gadget_handle_interrupts(int index)792 int usb_gadget_handle_interrupts(int index)
793 {
794 u32 status;
795
796 status = dwc3_omap_uboot_interrupt_status(index);
797 if (status)
798 dwc3_uboot_handle_interrupt(index);
799
800 return 0;
801 }
802 #endif /* CONFIG_USB_DWC3 */
803
804 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
board_usb_init(int index,enum usb_init_type init)805 int board_usb_init(int index, enum usb_init_type init)
806 {
807 enable_usb_clocks(index);
808 #ifdef CONFIG_USB_DWC3
809 switch (index) {
810 case 0:
811 if (init == USB_INIT_DEVICE) {
812 usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
813 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
814 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
815 ti_usb_phy_uboot_init(&usb_phy1_device);
816 dwc3_uboot_init(&usb_otg_ss1);
817 }
818 break;
819 case 1:
820 if (init == USB_INIT_DEVICE) {
821 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
822 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
823 ti_usb_phy_uboot_init(&usb_phy2_device);
824 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
825 dwc3_uboot_init(&usb_otg_ss2);
826 }
827 break;
828 default:
829 printf("Invalid Controller Index\n");
830 }
831 #endif
832
833 return 0;
834 }
835
board_usb_cleanup(int index,enum usb_init_type init)836 int board_usb_cleanup(int index, enum usb_init_type init)
837 {
838 #ifdef CONFIG_USB_DWC3
839 switch (index) {
840 case 0:
841 case 1:
842 if (init == USB_INIT_DEVICE) {
843 ti_usb_phy_uboot_exit(index);
844 dwc3_uboot_exit(index);
845 dwc3_omap_uboot_exit(index);
846 }
847 break;
848 default:
849 printf("Invalid Controller Index\n");
850 }
851 #endif
852 disable_usb_clocks(index);
853
854 return 0;
855 }
856 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
857 #endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
858
859 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,struct bd_info * bd)860 int ft_board_setup(void *blob, struct bd_info *bd)
861 {
862 ft_cpu_setup(blob, bd);
863
864 return 0;
865 }
866 #endif
867
868 #if defined(CONFIG_SPL_LOAD_FIT) || defined(CONFIG_DTB_RESELECT)
board_fit_config_name_match(const char * name)869 int board_fit_config_name_match(const char *name)
870 {
871 bool eeprom_read = board_ti_was_eeprom_read();
872
873 if (!strcmp(name, "am4372-generic") && !eeprom_read)
874 return 0;
875 else if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
876 return 0;
877 else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
878 return 0;
879 else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
880 return 0;
881 else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
882 return 0;
883 else
884 return -1;
885 }
886 #endif
887
888 #ifdef CONFIG_DTB_RESELECT
embedded_dtb_select(void)889 int embedded_dtb_select(void)
890 {
891 do_board_detect();
892 fdtdec_setup();
893
894 return 0;
895 }
896 #endif
897
898 #ifdef CONFIG_TI_SECURE_DEVICE
board_fit_image_post_process(void ** p_image,size_t * p_size)899 void board_fit_image_post_process(void **p_image, size_t *p_size)
900 {
901 secure_boot_verify_image(p_image, p_size);
902 }
903
board_tee_image_process(ulong tee_image,size_t tee_size)904 void board_tee_image_process(ulong tee_image, size_t tee_size)
905 {
906 secure_tee_install((u32)tee_image);
907 }
908
909 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
910 #endif
911