1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2019 NXP
4 * Peng Fan <peng.fan@nxp.com>
5 */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <clk-uclass.h>
10 #include <dm.h>
11 #include <log.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/imx-regs.h>
14 #include <dt-bindings/clock/imx8mn-clock.h>
15
16 #include "clk.h"
17
18 #define PLL_1416X_RATE(_rate, _m, _p, _s) \
19 { \
20 .rate = (_rate), \
21 .mdiv = (_m), \
22 .pdiv = (_p), \
23 .sdiv = (_s), \
24 }
25
26 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
27 { \
28 .rate = (_rate), \
29 .mdiv = (_m), \
30 .pdiv = (_p), \
31 .sdiv = (_s), \
32 .kdiv = (_k), \
33 }
34
35 static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = {
36 PLL_1416X_RATE(1800000000U, 225, 3, 0),
37 PLL_1416X_RATE(1600000000U, 200, 3, 0),
38 PLL_1416X_RATE(1200000000U, 300, 3, 1),
39 PLL_1416X_RATE(1000000000U, 250, 3, 1),
40 PLL_1416X_RATE(800000000U, 200, 3, 1),
41 PLL_1416X_RATE(750000000U, 250, 2, 2),
42 PLL_1416X_RATE(700000000U, 350, 3, 2),
43 PLL_1416X_RATE(600000000U, 300, 3, 2),
44 };
45
46 static const struct imx_pll14xx_rate_table imx8mn_drampll_tbl[] = {
47 PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
48 };
49
50 static struct imx_pll14xx_clk imx8mn_dram_pll __initdata = {
51 .type = PLL_1443X,
52 .rate_table = imx8mn_drampll_tbl,
53 .rate_count = ARRAY_SIZE(imx8mn_drampll_tbl),
54 };
55
56 static struct imx_pll14xx_clk imx8mn_arm_pll __initdata = {
57 .type = PLL_1416X,
58 .rate_table = imx8mn_pll1416x_tbl,
59 .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
60 };
61
62 static struct imx_pll14xx_clk imx8mn_sys_pll __initdata = {
63 .type = PLL_1416X,
64 .rate_table = imx8mn_pll1416x_tbl,
65 .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
66 };
67
68 static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
69 static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
70 static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
71 static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
72 static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
73 static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
74
75 static const char *imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m",
76 "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", };
77
78 static const char *imx8mn_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m",
79 "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", };
80
81 static const char *imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
82 "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
83
84 #ifndef CONFIG_SPL_BUILD
85 static const char *imx8mn_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m",
86 "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", };
87
88 static const char *imx8mn_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
89 "clk_ext3", "clk_ext4", "video_pll1_out", };
90
91 static const char *imx8mn_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
92 "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", };
93 #endif
94
95 static const char *imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
96 "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
97
98 static const char * const imx8mn_usb_bus_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m",
99 "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
100 "clk_ext4", "audio_pll2_out", };
101
102 static const char *imx8mn_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
103 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
104
105 static const char *imx8mn_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
106 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
107
108 #if CONFIG_IS_ENABLED(DM_SPI)
109 static const char *imx8mn_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
110 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
111 "sys_pll2_250m", "audio_pll2_out", };
112
113 static const char *imx8mn_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
114 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
115 "sys_pll2_250m", "audio_pll2_out", };
116
117 static const char *imx8mn_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
118 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
119 "sys_pll2_250m", "audio_pll2_out", };
120 #endif
121
122 static const char *imx8mn_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
123 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
124
125 static const char *imx8mn_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
126 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
127
128 static const char *imx8mn_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
129 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
130
131 static const char *imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
132 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
133
134 static const char *imx8mn_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",
135 "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
136
137 static const char *imx8mn_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
138 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", };
139
140 static const char *imx8mn_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m",
141 "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", };
142
143 static const char * const imx8mn_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
144 "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
145 "clk_ext3", "audio_pll2_out", };
146
147 static const char * const imx8mn_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
148 "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
149 "clk_ext3", "audio_pll2_out", };
150
imx8mn_clk_get_rate(struct clk * clk)151 static ulong imx8mn_clk_get_rate(struct clk *clk)
152 {
153 struct clk *c;
154 int ret;
155
156 debug("%s(#%lu)\n", __func__, clk->id);
157
158 ret = clk_get_by_id(clk->id, &c);
159 if (ret)
160 return ret;
161
162 return clk_get_rate(c);
163 }
164
imx8mn_clk_set_rate(struct clk * clk,unsigned long rate)165 static ulong imx8mn_clk_set_rate(struct clk *clk, unsigned long rate)
166 {
167 struct clk *c;
168 int ret;
169
170 debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
171
172 ret = clk_get_by_id(clk->id, &c);
173 if (ret)
174 return ret;
175
176 return clk_set_rate(c, rate);
177 }
178
__imx8mn_clk_enable(struct clk * clk,bool enable)179 static int __imx8mn_clk_enable(struct clk *clk, bool enable)
180 {
181 struct clk *c;
182 int ret;
183
184 debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
185
186 ret = clk_get_by_id(clk->id, &c);
187 if (ret)
188 return ret;
189
190 if (enable)
191 ret = clk_enable(c);
192 else
193 ret = clk_disable(c);
194
195 return ret;
196 }
197
imx8mn_clk_disable(struct clk * clk)198 static int imx8mn_clk_disable(struct clk *clk)
199 {
200 return __imx8mn_clk_enable(clk, 0);
201 }
202
imx8mn_clk_enable(struct clk * clk)203 static int imx8mn_clk_enable(struct clk *clk)
204 {
205 return __imx8mn_clk_enable(clk, 1);
206 }
207
imx8mn_clk_set_parent(struct clk * clk,struct clk * parent)208 static int imx8mn_clk_set_parent(struct clk *clk, struct clk *parent)
209 {
210 struct clk *c, *cp;
211 int ret;
212
213 debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
214
215 ret = clk_get_by_id(clk->id, &c);
216 if (ret)
217 return ret;
218
219 ret = clk_get_by_id(parent->id, &cp);
220 if (ret)
221 return ret;
222
223 ret = clk_set_parent(c, cp);
224 c->dev->parent = cp->dev;
225
226 return ret;
227 }
228
229 static struct clk_ops imx8mn_clk_ops = {
230 .set_rate = imx8mn_clk_set_rate,
231 .get_rate = imx8mn_clk_get_rate,
232 .enable = imx8mn_clk_enable,
233 .disable = imx8mn_clk_disable,
234 .set_parent = imx8mn_clk_set_parent,
235 };
236
imx8mn_clk_probe(struct udevice * dev)237 static int imx8mn_clk_probe(struct udevice *dev)
238 {
239 void __iomem *base;
240
241 base = (void *)ANATOP_BASE_ADDR;
242
243 clk_dm(IMX8MN_DRAM_PLL_REF_SEL,
244 imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
245 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
246 clk_dm(IMX8MN_ARM_PLL_REF_SEL,
247 imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
248 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
249 clk_dm(IMX8MN_SYS_PLL1_REF_SEL,
250 imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
251 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
252 clk_dm(IMX8MN_SYS_PLL2_REF_SEL,
253 imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
254 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
255 clk_dm(IMX8MN_SYS_PLL3_REF_SEL,
256 imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
257 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
258
259 clk_dm(IMX8MN_DRAM_PLL,
260 imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
261 base + 0x50, &imx8mn_dram_pll));
262 clk_dm(IMX8MN_ARM_PLL,
263 imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
264 base + 0x84, &imx8mn_arm_pll));
265 clk_dm(IMX8MN_SYS_PLL1,
266 imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",
267 base + 0x94, &imx8mn_sys_pll));
268 clk_dm(IMX8MN_SYS_PLL2,
269 imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",
270 base + 0x104, &imx8mn_sys_pll));
271 clk_dm(IMX8MN_SYS_PLL3,
272 imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
273 base + 0x114, &imx8mn_sys_pll));
274
275 /* PLL bypass out */
276 clk_dm(IMX8MN_DRAM_PLL_BYPASS,
277 imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1,
278 dram_pll_bypass_sels,
279 ARRAY_SIZE(dram_pll_bypass_sels),
280 CLK_SET_RATE_PARENT));
281 clk_dm(IMX8MN_ARM_PLL_BYPASS,
282 imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1,
283 arm_pll_bypass_sels,
284 ARRAY_SIZE(arm_pll_bypass_sels),
285 CLK_SET_RATE_PARENT));
286 clk_dm(IMX8MN_SYS_PLL1_BYPASS,
287 imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1,
288 sys_pll1_bypass_sels,
289 ARRAY_SIZE(sys_pll1_bypass_sels),
290 CLK_SET_RATE_PARENT));
291 clk_dm(IMX8MN_SYS_PLL2_BYPASS,
292 imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1,
293 sys_pll2_bypass_sels,
294 ARRAY_SIZE(sys_pll2_bypass_sels),
295 CLK_SET_RATE_PARENT));
296 clk_dm(IMX8MN_SYS_PLL3_BYPASS,
297 imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1,
298 sys_pll3_bypass_sels,
299 ARRAY_SIZE(sys_pll3_bypass_sels),
300 CLK_SET_RATE_PARENT));
301
302 /* PLL out gate */
303 clk_dm(IMX8MN_DRAM_PLL_OUT,
304 imx_clk_gate("dram_pll_out", "dram_pll_bypass",
305 base + 0x50, 13));
306 clk_dm(IMX8MN_ARM_PLL_OUT,
307 imx_clk_gate("arm_pll_out", "arm_pll_bypass",
308 base + 0x84, 11));
309 clk_dm(IMX8MN_SYS_PLL1_OUT,
310 imx_clk_gate("sys_pll1_out", "sys_pll1_bypass",
311 base + 0x94, 11));
312 clk_dm(IMX8MN_SYS_PLL2_OUT,
313 imx_clk_gate("sys_pll2_out", "sys_pll2_bypass",
314 base + 0x104, 11));
315 clk_dm(IMX8MN_SYS_PLL3_OUT,
316 imx_clk_gate("sys_pll3_out", "sys_pll3_bypass",
317 base + 0x114, 11));
318
319 /* SYS PLL fixed output */
320 clk_dm(IMX8MN_SYS_PLL1_40M,
321 imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
322 clk_dm(IMX8MN_SYS_PLL1_80M,
323 imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
324 clk_dm(IMX8MN_SYS_PLL1_100M,
325 imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
326 clk_dm(IMX8MN_SYS_PLL1_133M,
327 imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
328 clk_dm(IMX8MN_SYS_PLL1_160M,
329 imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
330 clk_dm(IMX8MN_SYS_PLL1_200M,
331 imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
332 clk_dm(IMX8MN_SYS_PLL1_266M,
333 imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
334 clk_dm(IMX8MN_SYS_PLL1_400M,
335 imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
336 clk_dm(IMX8MN_SYS_PLL1_800M,
337 imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
338
339 clk_dm(IMX8MN_SYS_PLL2_50M,
340 imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
341 clk_dm(IMX8MN_SYS_PLL2_100M,
342 imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
343 clk_dm(IMX8MN_SYS_PLL2_125M,
344 imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
345 clk_dm(IMX8MN_SYS_PLL2_166M,
346 imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
347 clk_dm(IMX8MN_SYS_PLL2_200M,
348 imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
349 clk_dm(IMX8MN_SYS_PLL2_250M,
350 imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
351 clk_dm(IMX8MN_SYS_PLL2_333M,
352 imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
353 clk_dm(IMX8MN_SYS_PLL2_500M,
354 imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
355 clk_dm(IMX8MN_SYS_PLL2_1000M,
356 imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
357
358 base = dev_read_addr_ptr(dev);
359 if (!base)
360 return -EINVAL;
361
362 clk_dm(IMX8MN_CLK_A53_SRC,
363 imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
364 imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels)));
365 clk_dm(IMX8MN_CLK_A53_CG,
366 imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
367 clk_dm(IMX8MN_CLK_A53_DIV,
368 imx_clk_divider2("arm_a53_div", "arm_a53_cg",
369 base + 0x8000, 0, 3));
370
371 clk_dm(IMX8MN_CLK_AHB,
372 imx8m_clk_composite_critical("ahb", imx8mn_ahb_sels,
373 base + 0x9000));
374 clk_dm(IMX8MN_CLK_IPG_ROOT,
375 imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
376
377 clk_dm(IMX8MN_CLK_ENET_AXI,
378 imx8m_clk_composite("enet_axi", imx8mn_enet_axi_sels,
379 base + 0x8880));
380 clk_dm(IMX8MN_CLK_NAND_USDHC_BUS,
381 imx8m_clk_composite_critical("nand_usdhc_bus",
382 imx8mn_nand_usdhc_sels,
383 base + 0x8900));
384 clk_dm(IMX8MN_CLK_USB_BUS,
385 imx8m_clk_composite("usb_bus", imx8mn_usb_bus_sels, base + 0x8b80));
386
387 /* IP */
388 clk_dm(IMX8MN_CLK_USDHC1,
389 imx8m_clk_composite("usdhc1", imx8mn_usdhc1_sels,
390 base + 0xac00));
391 clk_dm(IMX8MN_CLK_USDHC2,
392 imx8m_clk_composite("usdhc2", imx8mn_usdhc2_sels,
393 base + 0xac80));
394 clk_dm(IMX8MN_CLK_I2C1,
395 imx8m_clk_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00));
396 clk_dm(IMX8MN_CLK_I2C2,
397 imx8m_clk_composite("i2c2", imx8mn_i2c2_sels, base + 0xad80));
398 clk_dm(IMX8MN_CLK_I2C3,
399 imx8m_clk_composite("i2c3", imx8mn_i2c3_sels, base + 0xae00));
400 clk_dm(IMX8MN_CLK_I2C4,
401 imx8m_clk_composite("i2c4", imx8mn_i2c4_sels, base + 0xae80));
402 clk_dm(IMX8MN_CLK_WDOG,
403 imx8m_clk_composite("wdog", imx8mn_wdog_sels, base + 0xb900));
404 clk_dm(IMX8MN_CLK_USDHC3,
405 imx8m_clk_composite("usdhc3", imx8mn_usdhc3_sels,
406 base + 0xbc80));
407 clk_dm(IMX8MN_CLK_QSPI,
408 imx8m_clk_composite("qspi", imx8mn_qspi_sels, base + 0xab80));
409 clk_dm(IMX8MN_CLK_USB_CORE_REF,
410 imx8m_clk_composite("usb_core_ref", imx8mn_usb_core_sels, base + 0xb100));
411 clk_dm(IMX8MN_CLK_USB_PHY_REF,
412 imx8m_clk_composite("usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180));
413
414 clk_dm(IMX8MN_CLK_I2C1_ROOT,
415 imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
416 clk_dm(IMX8MN_CLK_I2C2_ROOT,
417 imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
418 clk_dm(IMX8MN_CLK_I2C3_ROOT,
419 imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
420 clk_dm(IMX8MN_CLK_I2C4_ROOT,
421 imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
422 clk_dm(IMX8MN_CLK_OCOTP_ROOT,
423 imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
424 clk_dm(IMX8MN_CLK_USDHC1_ROOT,
425 imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
426 clk_dm(IMX8MN_CLK_USDHC2_ROOT,
427 imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
428 clk_dm(IMX8MN_CLK_WDOG1_ROOT,
429 imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
430 clk_dm(IMX8MN_CLK_WDOG2_ROOT,
431 imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
432 clk_dm(IMX8MN_CLK_WDOG3_ROOT,
433 imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
434 clk_dm(IMX8MN_CLK_USDHC3_ROOT,
435 imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
436 clk_dm(IMX8MN_CLK_QSPI_ROOT,
437 imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
438 clk_dm(IMX8MN_CLK_USB1_CTRL_ROOT,
439 imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
440
441 /* clks not needed in SPL stage */
442 #ifndef CONFIG_SPL_BUILD
443 clk_dm(IMX8MN_CLK_ENET_REF,
444 imx8m_clk_composite("enet_ref", imx8mn_enet_ref_sels,
445 base + 0xa980));
446 clk_dm(IMX8MN_CLK_ENET_TIMER,
447 imx8m_clk_composite("enet_timer", imx8mn_enet_timer_sels,
448 base + 0xaa00));
449 clk_dm(IMX8MN_CLK_ENET_PHY_REF,
450 imx8m_clk_composite("enet_phy", imx8mn_enet_phy_sels,
451 base + 0xaa80));
452 clk_dm(IMX8MN_CLK_ENET1_ROOT,
453 imx_clk_gate4("enet1_root_clk", "enet_axi",
454 base + 0x40a0, 0));
455 #endif
456
457 #if CONFIG_IS_ENABLED(DM_SPI)
458 clk_dm(IMX8MN_CLK_ECSPI1,
459 imx8m_clk_composite("ecspi1", imx8mn_ecspi1_sels, base + 0xb280));
460 clk_dm(IMX8MN_CLK_ECSPI2,
461 imx8m_clk_composite("ecspi2", imx8mn_ecspi2_sels, base + 0xb300));
462 clk_dm(IMX8MN_CLK_ECSPI3,
463 imx8m_clk_composite("ecspi3", imx8mn_ecspi3_sels, base + 0xc180));
464 clk_dm(IMX8MN_CLK_ECSPI1_ROOT,
465 imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
466 clk_dm(IMX8MN_CLK_ECSPI2_ROOT,
467 imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
468 clk_dm(IMX8MN_CLK_ECSPI3_ROOT,
469 imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
470 #endif
471
472 return 0;
473 }
474
475 static const struct udevice_id imx8mn_clk_ids[] = {
476 { .compatible = "fsl,imx8mn-ccm" },
477 { },
478 };
479
480 U_BOOT_DRIVER(imx8mn_clk) = {
481 .name = "clk_imx8mn",
482 .id = UCLASS_CLK,
483 .of_match = imx8mn_clk_ids,
484 .ops = &imx8mn_clk_ops,
485 .probe = imx8mn_clk_probe,
486 .flags = DM_FLAG_PRE_RELOC,
487 };
488