1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2010-2013 NVIDIA Corporation
4 * With help from the mpc8xxx SPI driver
5 * With more help from omap3_spi SPI driver
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <log.h>
12 #include <time.h>
13 #include <asm/global_data.h>
14 #include <asm/io.h>
15 #include <asm/gpio.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/pinmux.h>
18 #include <asm/arch-tegra/clk_rst.h>
19 #include <spi.h>
20 #include <fdtdec.h>
21 #include <linux/bitops.h>
22 #include <linux/delay.h>
23 #include "tegra_spi.h"
24
25 DECLARE_GLOBAL_DATA_PTR;
26
27 #define SPI_CMD_GO BIT(30)
28 #define SPI_CMD_ACTIVE_SCLK_SHIFT 26
29 #define SPI_CMD_ACTIVE_SCLK_MASK (3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
30 #define SPI_CMD_CK_SDA BIT(21)
31 #define SPI_CMD_ACTIVE_SDA_SHIFT 18
32 #define SPI_CMD_ACTIVE_SDA_MASK (3 << SPI_CMD_ACTIVE_SDA_SHIFT)
33 #define SPI_CMD_CS_POL BIT(16)
34 #define SPI_CMD_TXEN BIT(15)
35 #define SPI_CMD_RXEN BIT(14)
36 #define SPI_CMD_CS_VAL BIT(13)
37 #define SPI_CMD_CS_SOFT BIT(12)
38 #define SPI_CMD_CS_DELAY BIT(9)
39 #define SPI_CMD_CS3_EN BIT(8)
40 #define SPI_CMD_CS2_EN BIT(7)
41 #define SPI_CMD_CS1_EN BIT(6)
42 #define SPI_CMD_CS0_EN BIT(5)
43 #define SPI_CMD_BIT_LENGTH BIT(4)
44 #define SPI_CMD_BIT_LENGTH_MASK GENMASK(4, 0)
45
46 #define SPI_STAT_BSY BIT(31)
47 #define SPI_STAT_RDY BIT(30)
48 #define SPI_STAT_RXF_FLUSH BIT(29)
49 #define SPI_STAT_TXF_FLUSH BIT(28)
50 #define SPI_STAT_RXF_UNR BIT(27)
51 #define SPI_STAT_TXF_OVF BIT(26)
52 #define SPI_STAT_RXF_EMPTY BIT(25)
53 #define SPI_STAT_RXF_FULL BIT(24)
54 #define SPI_STAT_TXF_EMPTY BIT(23)
55 #define SPI_STAT_TXF_FULL BIT(22)
56 #define SPI_STAT_SEL_TXRX_N BIT(16)
57 #define SPI_STAT_CUR_BLKCNT BIT(15)
58
59 #define SPI_TIMEOUT 1000
60 #define TEGRA_SPI_MAX_FREQ 52000000
61
62 struct spi_regs {
63 u32 command; /* SPI_COMMAND_0 register */
64 u32 status; /* SPI_STATUS_0 register */
65 u32 rx_cmp; /* SPI_RX_CMP_0 register */
66 u32 dma_ctl; /* SPI_DMA_CTL_0 register */
67 u32 tx_fifo; /* SPI_TX_FIFO_0 register */
68 u32 rsvd[3]; /* offsets 0x14 to 0x1F reserved */
69 u32 rx_fifo; /* SPI_RX_FIFO_0 register */
70 };
71
72 struct tegra20_sflash_priv {
73 struct spi_regs *regs;
74 unsigned int freq;
75 unsigned int mode;
76 int periph_id;
77 int valid;
78 int last_transaction_us;
79 };
80
tegra20_sflash_cs_info(struct udevice * bus,unsigned int cs,struct spi_cs_info * info)81 int tegra20_sflash_cs_info(struct udevice *bus, unsigned int cs,
82 struct spi_cs_info *info)
83 {
84 /* Tegra20 SPI-Flash - only 1 device ('bus/cs') */
85 if (cs != 0)
86 return -EINVAL;
87 else
88 return 0;
89 }
90
tegra20_sflash_of_to_plat(struct udevice * bus)91 static int tegra20_sflash_of_to_plat(struct udevice *bus)
92 {
93 struct tegra_spi_plat *plat = dev_get_plat(bus);
94 const void *blob = gd->fdt_blob;
95 int node = dev_of_offset(bus);
96
97 plat->base = dev_read_addr(bus);
98 plat->periph_id = clock_decode_periph_id(bus);
99
100 if (plat->periph_id == PERIPH_ID_NONE) {
101 debug("%s: could not decode periph id %d\n", __func__,
102 plat->periph_id);
103 return -FDT_ERR_NOTFOUND;
104 }
105
106 /* Use 500KHz as a suitable default */
107 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
108 500000);
109 plat->deactivate_delay_us = fdtdec_get_int(blob, node,
110 "spi-deactivate-delay", 0);
111 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
112 __func__, plat->base, plat->periph_id, plat->frequency,
113 plat->deactivate_delay_us);
114
115 return 0;
116 }
117
tegra20_sflash_probe(struct udevice * bus)118 static int tegra20_sflash_probe(struct udevice *bus)
119 {
120 struct tegra_spi_plat *plat = dev_get_plat(bus);
121 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
122
123 priv->regs = (struct spi_regs *)plat->base;
124
125 priv->last_transaction_us = timer_get_us();
126 priv->freq = plat->frequency;
127 priv->periph_id = plat->periph_id;
128
129 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
130 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
131 priv->freq);
132
133 return 0;
134 }
135
tegra20_sflash_claim_bus(struct udevice * dev)136 static int tegra20_sflash_claim_bus(struct udevice *dev)
137 {
138 struct udevice *bus = dev->parent;
139 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
140 struct spi_regs *regs = priv->regs;
141 u32 reg;
142
143 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
144 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
145 priv->freq);
146
147 /* Clear stale status here */
148 reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
149 SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF;
150 writel(reg, ®s->status);
151 debug("%s: STATUS = %08x\n", __func__, readl(®s->status));
152
153 /*
154 * Use sw-controlled CS, so we can clock in data after ReadID, etc.
155 */
156 reg = (priv->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
157 if (priv->mode & 2)
158 reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT;
159 clrsetbits_le32(®s->command, SPI_CMD_ACTIVE_SCLK_MASK |
160 SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg);
161 debug("%s: COMMAND = %08x\n", __func__, readl(®s->command));
162
163 /*
164 * SPI pins on Tegra20 are muxed - change pinmux later due to UART
165 * issue.
166 */
167 pinmux_set_func(PMUX_PINGRP_GMD, PMUX_FUNC_SFLASH);
168 pinmux_tristate_disable(PMUX_PINGRP_LSPI);
169 pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_SFLASH);
170
171 return 0;
172 }
173
spi_cs_activate(struct udevice * dev)174 static void spi_cs_activate(struct udevice *dev)
175 {
176 struct udevice *bus = dev->parent;
177 struct tegra_spi_plat *pdata = dev_get_plat(bus);
178 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
179
180 /* If it's too soon to do another transaction, wait */
181 if (pdata->deactivate_delay_us &&
182 priv->last_transaction_us) {
183 ulong delay_us; /* The delay completed so far */
184 delay_us = timer_get_us() - priv->last_transaction_us;
185 if (delay_us < pdata->deactivate_delay_us)
186 udelay(pdata->deactivate_delay_us - delay_us);
187 }
188
189 /* CS is negated on Tegra, so drive a 1 to get a 0 */
190 setbits_le32(&priv->regs->command, SPI_CMD_CS_VAL);
191 }
192
spi_cs_deactivate(struct udevice * dev)193 static void spi_cs_deactivate(struct udevice *dev)
194 {
195 struct udevice *bus = dev->parent;
196 struct tegra_spi_plat *pdata = dev_get_plat(bus);
197 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
198
199 /* CS is negated on Tegra, so drive a 0 to get a 1 */
200 clrbits_le32(&priv->regs->command, SPI_CMD_CS_VAL);
201
202 /* Remember time of this transaction so we can honour the bus delay */
203 if (pdata->deactivate_delay_us)
204 priv->last_transaction_us = timer_get_us();
205 }
206
tegra20_sflash_xfer(struct udevice * dev,unsigned int bitlen,const void * data_out,void * data_in,unsigned long flags)207 static int tegra20_sflash_xfer(struct udevice *dev, unsigned int bitlen,
208 const void *data_out, void *data_in,
209 unsigned long flags)
210 {
211 struct udevice *bus = dev->parent;
212 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
213 struct spi_regs *regs = priv->regs;
214 u32 reg, tmpdout, tmpdin = 0;
215 const u8 *dout = data_out;
216 u8 *din = data_in;
217 int num_bytes;
218 int ret;
219
220 debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
221 __func__, dev_seq(bus), spi_chip_select(dev), dout, din, bitlen);
222 if (bitlen % 8)
223 return -1;
224 num_bytes = bitlen / 8;
225
226 ret = 0;
227
228 reg = readl(®s->status);
229 writel(reg, ®s->status); /* Clear all SPI events via R/W */
230 debug("spi_xfer entry: STATUS = %08x\n", reg);
231
232 reg = readl(®s->command);
233 reg |= SPI_CMD_TXEN | SPI_CMD_RXEN;
234 writel(reg, ®s->command);
235 debug("spi_xfer: COMMAND = %08x\n", readl(®s->command));
236
237 if (flags & SPI_XFER_BEGIN)
238 spi_cs_activate(dev);
239
240 /* handle data in 32-bit chunks */
241 while (num_bytes > 0) {
242 int bytes;
243 int is_read = 0;
244 int tm, i;
245
246 tmpdout = 0;
247 bytes = (num_bytes > 4) ? 4 : num_bytes;
248
249 if (dout != NULL) {
250 for (i = 0; i < bytes; ++i)
251 tmpdout = (tmpdout << 8) | dout[i];
252 }
253
254 num_bytes -= bytes;
255 if (dout)
256 dout += bytes;
257
258 clrsetbits_le32(®s->command, SPI_CMD_BIT_LENGTH_MASK,
259 bytes * 8 - 1);
260 writel(tmpdout, ®s->tx_fifo);
261 setbits_le32(®s->command, SPI_CMD_GO);
262
263 /*
264 * Wait for SPI transmit FIFO to empty, or to time out.
265 * The RX FIFO status will be read and cleared last
266 */
267 for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
268 u32 status;
269
270 status = readl(®s->status);
271
272 /* We can exit when we've had both RX and TX activity */
273 if (is_read && (status & SPI_STAT_TXF_EMPTY))
274 break;
275
276 if ((status & (SPI_STAT_BSY | SPI_STAT_RDY)) !=
277 SPI_STAT_RDY)
278 tm++;
279
280 else if (!(status & SPI_STAT_RXF_EMPTY)) {
281 tmpdin = readl(®s->rx_fifo);
282 is_read = 1;
283
284 /* swap bytes read in */
285 if (din != NULL) {
286 for (i = bytes - 1; i >= 0; --i) {
287 din[i] = tmpdin & 0xff;
288 tmpdin >>= 8;
289 }
290 din += bytes;
291 }
292 }
293 }
294
295 if (tm >= SPI_TIMEOUT)
296 ret = tm;
297
298 /* clear ACK RDY, etc. bits */
299 writel(readl(®s->status), ®s->status);
300 }
301
302 if (flags & SPI_XFER_END)
303 spi_cs_deactivate(dev);
304
305 debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
306 tmpdin, readl(®s->status));
307
308 if (ret) {
309 printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret);
310 return -1;
311 }
312
313 return 0;
314 }
315
tegra20_sflash_set_speed(struct udevice * bus,uint speed)316 static int tegra20_sflash_set_speed(struct udevice *bus, uint speed)
317 {
318 struct tegra_spi_plat *plat = dev_get_plat(bus);
319 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
320
321 if (speed > plat->frequency)
322 speed = plat->frequency;
323 priv->freq = speed;
324 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
325
326 return 0;
327 }
328
tegra20_sflash_set_mode(struct udevice * bus,uint mode)329 static int tegra20_sflash_set_mode(struct udevice *bus, uint mode)
330 {
331 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
332
333 priv->mode = mode;
334 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
335
336 return 0;
337 }
338
339 static const struct dm_spi_ops tegra20_sflash_ops = {
340 .claim_bus = tegra20_sflash_claim_bus,
341 .xfer = tegra20_sflash_xfer,
342 .set_speed = tegra20_sflash_set_speed,
343 .set_mode = tegra20_sflash_set_mode,
344 .cs_info = tegra20_sflash_cs_info,
345 };
346
347 static const struct udevice_id tegra20_sflash_ids[] = {
348 { .compatible = "nvidia,tegra20-sflash" },
349 { }
350 };
351
352 U_BOOT_DRIVER(tegra20_sflash) = {
353 .name = "tegra20_sflash",
354 .id = UCLASS_SPI,
355 .of_match = tegra20_sflash_ids,
356 .ops = &tegra20_sflash_ops,
357 .of_to_plat = tegra20_sflash_of_to_plat,
358 .plat_auto = sizeof(struct tegra_spi_plat),
359 .priv_auto = sizeof(struct tegra20_sflash_priv),
360 .probe = tegra20_sflash_probe,
361 };
362