1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2010-2011 Freescale Semiconductor, Inc. 4 * Copyright 2020 NXP 5 */ 6 7 /* 8 * QorIQ RDB boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include <linux/stringify.h> 14 15 #if defined(CONFIG_TARGET_P1020RDB_PC) 16 #define CONFIG_BOARDNAME "P1020RDB-PC" 17 #define CONFIG_NAND_FSL_ELBC 18 #define CONFIG_VSC7385_ENET 19 #define CONFIG_SLIC 20 #define __SW_BOOT_MASK 0x03 21 #define __SW_BOOT_NOR 0x5c 22 #define __SW_BOOT_SPI 0x1c 23 #define __SW_BOOT_SD 0x9c 24 #define __SW_BOOT_NAND 0xec 25 #define __SW_BOOT_PCIE 0x6c 26 #define CONFIG_SYS_L2_SIZE (256 << 10) 27 #endif 28 29 /* 30 * P1020RDB-PD board has user selectable switches for evaluating different 31 * frequency and boot options for the P1020 device. The table that 32 * follow describe the available options. The front six binary number was in 33 * accordance with SW3[1:6]. 34 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off 35 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off 36 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off 37 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off 38 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off 39 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off 40 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off 41 */ 42 #if defined(CONFIG_TARGET_P1020RDB_PD) 43 #define CONFIG_BOARDNAME "P1020RDB-PD" 44 #define CONFIG_NAND_FSL_ELBC 45 #define CONFIG_VSC7385_ENET 46 #define CONFIG_SLIC 47 #define __SW_BOOT_MASK 0x03 48 #define __SW_BOOT_NOR 0x64 49 #define __SW_BOOT_SPI 0x34 50 #define __SW_BOOT_SD 0x24 51 #define __SW_BOOT_NAND 0x44 52 #define __SW_BOOT_PCIE 0x74 53 #define CONFIG_SYS_L2_SIZE (256 << 10) 54 /* 55 * Dynamic MTD Partition support with mtdparts 56 */ 57 #endif 58 59 #if defined(CONFIG_TARGET_P2020RDB) 60 #define CONFIG_BOARDNAME "P2020RDB-PC" 61 #define CONFIG_NAND_FSL_ELBC 62 #define CONFIG_VSC7385_ENET 63 #define __SW_BOOT_MASK 0x03 64 #define __SW_BOOT_NOR 0xc8 65 #define __SW_BOOT_SPI 0x28 66 #define __SW_BOOT_SD 0x68 /* or 0x18 */ 67 #define __SW_BOOT_NAND 0xe8 68 #define __SW_BOOT_PCIE 0xa8 69 #define CONFIG_SYS_L2_SIZE (512 << 10) 70 /* 71 * Dynamic MTD Partition support with mtdparts 72 */ 73 #endif 74 75 #ifdef CONFIG_SDCARD 76 #define CONFIG_SPL_FLUSH_IMAGE 77 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 78 #define CONFIG_SPL_PAD_TO 0x20000 79 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 80 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 81 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 82 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 83 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 84 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 85 #ifdef CONFIG_SPL_BUILD 86 #define CONFIG_SPL_COMMON_INIT_DDR 87 #endif 88 #endif 89 90 #ifdef CONFIG_SPIFLASH 91 #define CONFIG_SPL_SPI_FLASH_MINIMAL 92 #define CONFIG_SPL_FLUSH_IMAGE 93 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 94 #define CONFIG_SPL_PAD_TO 0x20000 95 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 96 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 97 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 98 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 99 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 100 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 101 #ifdef CONFIG_SPL_BUILD 102 #define CONFIG_SPL_COMMON_INIT_DDR 103 #endif 104 #endif 105 106 #ifdef CONFIG_MTD_RAW_NAND 107 #ifdef CONFIG_TPL_BUILD 108 #define CONFIG_SPL_FLUSH_IMAGE 109 #define CONFIG_SPL_NAND_INIT 110 #define CONFIG_SPL_COMMON_INIT_DDR 111 #define CONFIG_SPL_MAX_SIZE (128 << 10) 112 #define CONFIG_TPL_TEXT_BASE 0xf8f81000 113 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 114 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 115 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 116 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 117 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 118 #elif defined(CONFIG_SPL_BUILD) 119 #define CONFIG_SPL_INIT_MINIMAL 120 #define CONFIG_SPL_FLUSH_IMAGE 121 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 122 #define CONFIG_SPL_MAX_SIZE 4096 123 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 124 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 125 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 126 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 127 #endif /* not CONFIG_TPL_BUILD */ 128 129 #define CONFIG_SPL_PAD_TO 0x20000 130 #define CONFIG_TPL_PAD_TO 0x20000 131 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 132 #endif 133 134 #ifndef CONFIG_RESET_VECTOR_ADDRESS 135 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 136 #endif 137 138 #ifndef CONFIG_SYS_MONITOR_BASE 139 #ifdef CONFIG_TPL_BUILD 140 #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE 141 #elif defined(CONFIG_SPL_BUILD) 142 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 143 #else 144 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 145 #endif 146 #endif 147 148 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 149 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 150 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 151 152 #define CONFIG_SYS_SATA_MAX_DEVICE 2 153 #define CONFIG_LBA48 154 155 #if defined(CONFIG_TARGET_P2020RDB) 156 #define CONFIG_SYS_CLK_FREQ 100000000 157 #else 158 #define CONFIG_SYS_CLK_FREQ 66666666 159 #endif 160 #define CONFIG_DDR_CLK_FREQ 66666666 161 162 #define CONFIG_HWCONFIG 163 /* 164 * These can be toggled for performance analysis, otherwise use default. 165 */ 166 #define CONFIG_L2_CACHE 167 #define CONFIG_BTB 168 169 #define CONFIG_ENABLE_36BIT_PHYS 170 171 #define CONFIG_SYS_CCSRBAR 0xffe00000 172 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 173 174 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 175 SPL code*/ 176 #ifdef CONFIG_SPL_BUILD 177 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 178 #endif 179 180 /* DDR Setup */ 181 #define CONFIG_SYS_DDR_RAW_TIMING 182 #define CONFIG_DDR_SPD 183 #define CONFIG_SYS_SPD_BUS_NUM 1 184 #define SPD_EEPROM_ADDRESS 0x52 185 186 #if defined(CONFIG_TARGET_P1020RDB_PD) 187 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 188 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 189 #else 190 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 191 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 192 #endif 193 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 194 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 195 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 196 197 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 198 199 /* Default settings for DDR3 */ 200 #ifndef CONFIG_TARGET_P2020RDB 201 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 202 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 203 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 204 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 205 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 206 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 207 208 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 209 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 210 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 211 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 212 213 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 214 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 215 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 216 #define CONFIG_SYS_DDR_RCW_1 0x00000000 217 #define CONFIG_SYS_DDR_RCW_2 0x00000000 218 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 219 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 220 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 221 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 222 223 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 224 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 225 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 226 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 227 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 228 #define CONFIG_SYS_DDR_MODE_1 0x40461520 229 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 230 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 231 #endif 232 233 /* 234 * Memory map 235 * 236 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 237 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 238 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 239 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable 240 * (early boot only) 241 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 242 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 243 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 244 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 245 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 246 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 247 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 248 */ 249 250 /* 251 * Local Bus Definitions 252 */ 253 #if defined(CONFIG_TARGET_P1020RDB_PD) 254 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 255 #define CONFIG_SYS_FLASH_BASE 0xec000000 256 #else 257 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ 258 #define CONFIG_SYS_FLASH_BASE 0xef000000 259 #endif 260 261 #ifdef CONFIG_PHYS_64BIT 262 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 263 #else 264 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 265 #endif 266 267 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 268 | BR_PS_16 | BR_V) 269 270 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 271 272 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 273 #define CONFIG_SYS_FLASH_QUIET_TEST 274 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 275 276 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 277 278 #undef CONFIG_SYS_FLASH_CHECKSUM 279 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 280 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 281 282 #define CONFIG_SYS_FLASH_EMPTY_INFO 283 284 /* Nand Flash */ 285 #ifdef CONFIG_NAND_FSL_ELBC 286 #define CONFIG_SYS_NAND_BASE 0xff800000 287 #ifdef CONFIG_PHYS_64BIT 288 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 289 #else 290 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 291 #endif 292 293 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 294 #define CONFIG_SYS_MAX_NAND_DEVICE 1 295 #if defined(CONFIG_TARGET_P1020RDB_PD) 296 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 297 #else 298 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 299 #endif 300 301 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 302 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 303 | BR_PS_8 /* Port Size = 8 bit */ \ 304 | BR_MS_FCM /* MSEL = FCM */ \ 305 | BR_V) /* valid */ 306 #if defined(CONFIG_TARGET_P1020RDB_PD) 307 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 308 | OR_FCM_PGS /* Large Page*/ \ 309 | OR_FCM_CSCT \ 310 | OR_FCM_CST \ 311 | OR_FCM_CHT \ 312 | OR_FCM_SCY_1 \ 313 | OR_FCM_TRLX \ 314 | OR_FCM_EHTR) 315 #else 316 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 317 | OR_FCM_CSCT \ 318 | OR_FCM_CST \ 319 | OR_FCM_CHT \ 320 | OR_FCM_SCY_1 \ 321 | OR_FCM_TRLX \ 322 | OR_FCM_EHTR) 323 #endif 324 #endif /* CONFIG_NAND_FSL_ELBC */ 325 326 #define CONFIG_SYS_INIT_RAM_LOCK 327 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 328 #ifdef CONFIG_PHYS_64BIT 329 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 330 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 331 /* The assembler doesn't like typecast */ 332 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 333 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 334 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 335 #else 336 /* Initial L1 address */ 337 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 338 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 339 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 340 #endif 341 /* Size of used area in RAM */ 342 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 343 344 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 345 GENERATED_GBL_DATA_SIZE) 346 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 347 348 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 349 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 350 351 #define CONFIG_SYS_CPLD_BASE 0xffa00000 352 #ifdef CONFIG_PHYS_64BIT 353 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 354 #else 355 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 356 #endif 357 /* CPLD config size: 1Mb */ 358 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ 359 BR_PS_8 | BR_V) 360 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) 361 362 #define CONFIG_SYS_PMC_BASE 0xff980000 363 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 364 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 365 BR_PS_8 | BR_V) 366 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 367 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 368 OR_GPCM_EAD) 369 370 #ifdef CONFIG_MTD_RAW_NAND 371 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 372 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 373 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 374 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 375 #else 376 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 377 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 378 #ifdef CONFIG_NAND_FSL_ELBC 379 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 380 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 381 #endif 382 #endif 383 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ 384 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ 385 386 /* Vsc7385 switch */ 387 #ifdef CONFIG_VSC7385_ENET 388 #define __VSCFW_ADDR "vscfw_addr=ef000000" 389 #define CONFIG_SYS_VSC7385_BASE 0xffb00000 390 391 #ifdef CONFIG_PHYS_64BIT 392 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 393 #else 394 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE 395 #endif 396 397 #define CONFIG_SYS_VSC7385_BR_PRELIM \ 398 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) 399 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ 400 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ 401 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 402 403 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM 404 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM 405 406 /* The size of the VSC7385 firmware image */ 407 #define CONFIG_VSC7385_IMAGE_SIZE 8192 408 #endif 409 410 /* 411 * Config the L2 Cache as L2 SRAM 412 */ 413 #if defined(CONFIG_SPL_BUILD) 414 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 415 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 416 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 417 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 418 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 419 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 420 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 421 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 422 #if defined(CONFIG_TARGET_P2020RDB) 423 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) 424 #else 425 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 426 #endif 427 #elif defined(CONFIG_MTD_RAW_NAND) 428 #ifdef CONFIG_TPL_BUILD 429 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 430 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 431 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 432 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 433 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 434 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 435 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 436 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 437 #else 438 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 439 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 440 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 441 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 442 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 443 #endif /* CONFIG_TPL_BUILD */ 444 #endif 445 #endif 446 447 /* Serial Port - controlled on board with jumper J8 448 * open - index 2 449 * shorted - index 1 450 */ 451 #undef CONFIG_SERIAL_SOFTWARE_FIFO 452 #define CONFIG_SYS_NS16550_SERIAL 453 #define CONFIG_SYS_NS16550_REG_SIZE 1 454 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 455 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 456 #define CONFIG_NS16550_MIN_FUNCTIONS 457 #endif 458 459 #define CONFIG_SYS_BAUDRATE_TABLE \ 460 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 461 462 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 463 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 464 465 /* I2C */ 466 #if !CONFIG_IS_ENABLED(DM_I2C) 467 #define CONFIG_SYS_I2C 468 #define CONFIG_SYS_FSL_I2C_SPEED 400000 469 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 470 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 471 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 472 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 473 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 474 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 475 #else 476 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM 477 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 478 #endif 479 480 #define CONFIG_SYS_I2C_FSL 481 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 482 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 483 484 /* 485 * I2C2 EEPROM 486 */ 487 #undef CONFIG_ID_EEPROM 488 489 #define CONFIG_RTC_PT7C4338 490 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 491 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 492 493 /* enable read and write access to EEPROM */ 494 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 495 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 496 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 497 498 #if defined(CONFIG_PCI) 499 /* 500 * General PCI 501 * Memory space is mapped 1-1, but I/O space must start from 0. 502 */ 503 504 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 505 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 506 #ifdef CONFIG_PHYS_64BIT 507 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 508 #else 509 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 510 #endif 511 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 512 #ifdef CONFIG_PHYS_64BIT 513 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 514 #else 515 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 516 #endif 517 518 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 519 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 520 #ifdef CONFIG_PHYS_64BIT 521 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 522 #else 523 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 524 #endif 525 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 526 #ifdef CONFIG_PHYS_64BIT 527 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 528 #else 529 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 530 #endif 531 532 #if !defined(CONFIG_DM_PCI) 533 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 534 #define CONFIG_PCI_INDIRECT_BRIDGE 535 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" 536 #ifdef CONFIG_PHYS_64BIT 537 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 538 #else 539 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 540 #endif 541 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 542 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 543 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 544 545 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 546 #ifdef CONFIG_PHYS_64BIT 547 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 548 #else 549 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 550 #endif 551 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 552 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 553 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 554 #endif 555 556 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 557 #endif /* CONFIG_PCI */ 558 559 #if defined(CONFIG_TSEC_ENET) 560 #define CONFIG_TSEC1 561 #define CONFIG_TSEC1_NAME "eTSEC1" 562 #define CONFIG_TSEC2 563 #define CONFIG_TSEC2_NAME "eTSEC2" 564 #define CONFIG_TSEC3 565 #define CONFIG_TSEC3_NAME "eTSEC3" 566 567 #define TSEC1_PHY_ADDR 2 568 #define TSEC2_PHY_ADDR 0 569 #define TSEC3_PHY_ADDR 1 570 571 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 572 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 573 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 574 575 #define TSEC1_PHYIDX 0 576 #define TSEC2_PHYIDX 0 577 #define TSEC3_PHYIDX 0 578 579 #define CONFIG_ETHPRIME "eTSEC1" 580 581 #define CONFIG_HAS_ETH0 582 #define CONFIG_HAS_ETH1 583 #define CONFIG_HAS_ETH2 584 #endif /* CONFIG_TSEC_ENET */ 585 586 #ifdef CONFIG_QE 587 /* QE microcode/firmware address */ 588 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 589 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 590 #endif /* CONFIG_QE */ 591 592 /* 593 * Environment 594 */ 595 #if defined(CONFIG_SDCARD) 596 #define CONFIG_FSL_FIXED_MMC_LOCATION 597 #elif defined(CONFIG_MTD_RAW_NAND) 598 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 599 #ifdef CONFIG_TPL_BUILD 600 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 601 #endif 602 #elif defined(CONFIG_SYS_RAMBOOT) 603 #define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 604 #endif 605 606 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 607 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 608 609 /* 610 * USB 611 */ 612 #define CONFIG_HAS_FSL_DR_USB 613 614 #if defined(CONFIG_HAS_FSL_DR_USB) 615 #ifdef CONFIG_USB_EHCI_HCD 616 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 617 #define CONFIG_USB_EHCI_FSL 618 #endif 619 #endif 620 621 #if defined(CONFIG_TARGET_P1020RDB_PD) 622 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 623 #endif 624 625 #ifdef CONFIG_MMC 626 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 627 #endif 628 629 #undef CONFIG_WATCHDOG /* watchdog disabled */ 630 631 /* 632 * Miscellaneous configurable options 633 */ 634 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 635 636 /* 637 * For booting Linux, the board info and command line data 638 * have to be in the first 64 MB of memory, since this is 639 * the maximum mapped by the Linux kernel during initialization. 640 */ 641 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 642 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 643 644 #if defined(CONFIG_CMD_KGDB) 645 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 646 #endif 647 648 /* 649 * Environment Configuration 650 */ 651 #define CONFIG_HOSTNAME "unknown" 652 #define CONFIG_ROOTPATH "/opt/nfsroot" 653 #define CONFIG_BOOTFILE "uImage" 654 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 655 656 /* default location for tftp and bootm */ 657 #define CONFIG_LOADADDR 1000000 658 659 #ifdef __SW_BOOT_NOR 660 #define __NOR_RST_CMD \ 661 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ 662 i2c mw 18 3 __SW_BOOT_MASK 1; reset 663 #endif 664 #ifdef __SW_BOOT_SPI 665 #define __SPI_RST_CMD \ 666 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ 667 i2c mw 18 3 __SW_BOOT_MASK 1; reset 668 #endif 669 #ifdef __SW_BOOT_SD 670 #define __SD_RST_CMD \ 671 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ 672 i2c mw 18 3 __SW_BOOT_MASK 1; reset 673 #endif 674 #ifdef __SW_BOOT_NAND 675 #define __NAND_RST_CMD \ 676 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ 677 i2c mw 18 3 __SW_BOOT_MASK 1; reset 678 #endif 679 #ifdef __SW_BOOT_PCIE 680 #define __PCIE_RST_CMD \ 681 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ 682 i2c mw 18 3 __SW_BOOT_MASK 1; reset 683 #endif 684 685 #define CONFIG_EXTRA_ENV_SETTINGS \ 686 "netdev=eth0\0" \ 687 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 688 "loadaddr=1000000\0" \ 689 "bootfile=uImage\0" \ 690 "tftpflash=tftpboot $loadaddr $uboot; " \ 691 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 692 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 693 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 694 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 695 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 696 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 697 "consoledev=ttyS0\0" \ 698 "ramdiskaddr=2000000\0" \ 699 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 700 "fdtaddr=1e00000\0" \ 701 "bdev=sda1\0" \ 702 "jffs2nor=mtdblock3\0" \ 703 "norbootaddr=ef080000\0" \ 704 "norfdtaddr=ef040000\0" \ 705 "jffs2nand=mtdblock9\0" \ 706 "nandbootaddr=100000\0" \ 707 "nandfdtaddr=80000\0" \ 708 "ramdisk_size=120000\0" \ 709 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ 710 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ 711 __stringify(__VSCFW_ADDR)"\0" \ 712 __stringify(__NOR_RST_CMD)"\0" \ 713 __stringify(__SPI_RST_CMD)"\0" \ 714 __stringify(__SD_RST_CMD)"\0" \ 715 __stringify(__NAND_RST_CMD)"\0" \ 716 __stringify(__PCIE_RST_CMD)"\0" 717 718 #define CONFIG_NFSBOOTCOMMAND \ 719 "setenv bootargs root=/dev/nfs rw " \ 720 "nfsroot=$serverip:$rootpath " \ 721 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 722 "console=$consoledev,$baudrate $othbootargs;" \ 723 "tftp $loadaddr $bootfile;" \ 724 "tftp $fdtaddr $fdtfile;" \ 725 "bootm $loadaddr - $fdtaddr" 726 727 #define CONFIG_HDBOOT \ 728 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 729 "console=$consoledev,$baudrate $othbootargs;" \ 730 "usb start;" \ 731 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 732 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 733 "bootm $loadaddr - $fdtaddr" 734 735 #define CONFIG_USB_FAT_BOOT \ 736 "setenv bootargs root=/dev/ram rw " \ 737 "console=$consoledev,$baudrate $othbootargs " \ 738 "ramdisk_size=$ramdisk_size;" \ 739 "usb start;" \ 740 "fatload usb 0:2 $loadaddr $bootfile;" \ 741 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 742 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 743 "bootm $loadaddr $ramdiskaddr $fdtaddr" 744 745 #define CONFIG_USB_EXT2_BOOT \ 746 "setenv bootargs root=/dev/ram rw " \ 747 "console=$consoledev,$baudrate $othbootargs " \ 748 "ramdisk_size=$ramdisk_size;" \ 749 "usb start;" \ 750 "ext2load usb 0:4 $loadaddr $bootfile;" \ 751 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 752 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 753 "bootm $loadaddr $ramdiskaddr $fdtaddr" 754 755 #define CONFIG_NORBOOT \ 756 "setenv bootargs root=/dev/$jffs2nor rw " \ 757 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 758 "bootm $norbootaddr - $norfdtaddr" 759 760 #define CONFIG_RAMBOOTCOMMAND \ 761 "setenv bootargs root=/dev/ram rw " \ 762 "console=$consoledev,$baudrate $othbootargs " \ 763 "ramdisk_size=$ramdisk_size;" \ 764 "tftp $ramdiskaddr $ramdiskfile;" \ 765 "tftp $loadaddr $bootfile;" \ 766 "tftp $fdtaddr $fdtfile;" \ 767 "bootm $loadaddr $ramdiskaddr $fdtaddr" 768 769 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 770 771 #endif /* __CONFIG_H */ 772