1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2014-2015 Freescale Semiconductor
4 * Copyright 2019 NXP
5 *
6 * Extracted from armv8/start.S
7 */
8
9#include <config.h>
10#include <linux/linkage.h>
11#include <asm/gic.h>
12#include <asm/macro.h>
13#include <asm/arch-fsl-layerscape/soc.h>
14#ifdef CONFIG_FSL_LSCH3
15#include <asm/arch-fsl-layerscape/immap_lsch3.h>
16#endif
17#include <asm/u-boot.h>
18
19	.align 3
20	.weak secondary_boot_addr
21secondary_boot_addr:
22	.quad 0
23
24/* Get GIC offset
25* For LS1043a rev1.0, GIC base address align with 4k.
26* For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT]
27* is set, GIC base address align with 4K, or else align
28* with 64k.
29* output:
30*	x0: the base address of GICD
31*	x1: the base address of GICC
32*/
33ENTRY(get_gic_offset)
34	ldr     x0, =GICD_BASE
35#ifdef CONFIG_GICV2
36	ldr     x1, =GICC_BASE
37#endif
38#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
39	ldr     x2, =DCFG_CCSR_SVR
40	ldr	w2, [x2]
41	rev	w2, w2
42	lsr	w3, w2, #16
43	ldr	w4, =SVR_DEV(SVR_LS1043A)
44	cmp	w3, w4
45	b.ne	1f
46	ands	w2, w2, #0xff
47	cmp	w2, #REV1_0
48	b.eq	1f
49	ldr	x2, =SCFG_GIC400_ALIGN
50	ldr	w2, [x2]
51	rev	w2, w2
52	tbnz	w2, #GIC_ADDR_BIT, 1f
53	ldr     x0, =GICD_BASE_64K
54#ifdef CONFIG_GICV2
55	ldr     x1, =GICC_BASE_64K
56#endif
571:
58#endif
59	ret
60ENDPROC(get_gic_offset)
61
62ENTRY(smp_kick_all_cpus)
63	/* Kick secondary cpus up by SGI 0 interrupt */
64#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
65	mov	x29, lr			/* Save LR */
66	bl	get_gic_offset
67	bl	gic_kick_secondary_cpus
68	mov	lr, x29			/* Restore LR */
69#endif
70	ret
71ENDPROC(smp_kick_all_cpus)
72
73
74ENTRY(lowlevel_init)
75	mov	x29, lr			/* Save LR */
76
77	/* unmask SError and abort */
78	msr daifclr, #4
79
80	/* Set HCR_EL2[AMO] so SError @EL2 is taken */
81	mrs	x0, hcr_el2
82	orr	x0, x0, #0x20			/* AMO */
83	msr	hcr_el2, x0
84	isb
85
86	switch_el x1, 1f, 100f, 100f	/* skip if not in EL3 */
871:
88
89#if defined (CONFIG_SYS_FSL_HAS_CCN504)
90
91	/* Set Wuo bit for RN-I 20 */
92#ifdef CONFIG_ARCH_LS2080A
93	ldr	x0, =CCI_AUX_CONTROL_BASE(20)
94	ldr	x1, =0x00000010
95	bl	ccn504_set_aux
96
97	/*
98	 * Set forced-order mode in RNI-6, RNI-20
99	 * This is required for performance optimization on LS2088A
100	 * LS2080A family does not support setting forced-order mode,
101	 * so skip this operation for LS2080A family
102	 */
103	bl	get_svr
104	lsr	w0, w0, #16
105	ldr	w1, =SVR_DEV(SVR_LS2080A)
106	cmp	w0, w1
107	b.eq	1f
108
109	ldr	x0, =CCI_AUX_CONTROL_BASE(6)
110	ldr	x1, =0x00000020
111	bl	ccn504_set_aux
112	ldr	x0, =CCI_AUX_CONTROL_BASE(20)
113	ldr	x1, =0x00000020
114	bl	ccn504_set_aux
1151:
116#endif
117
118	/* Add fully-coherent masters to DVM domain */
119	ldr	x0, =CCI_MN_BASE
120	ldr	x1, =CCI_MN_RNF_NODEID_LIST
121	ldr	x2, =CCI_MN_DVM_DOMAIN_CTL_SET
122	bl	ccn504_add_masters_to_dvm
123
124	/* Set all RN-I ports to QoS of 15 */
125	ldr	x0, =CCI_S0_QOS_CONTROL_BASE(0)
126	ldr	x1, =0x00FF000C
127	bl	ccn504_set_qos
128	ldr	x0, =CCI_S1_QOS_CONTROL_BASE(0)
129	ldr	x1, =0x00FF000C
130	bl	ccn504_set_qos
131	ldr	x0, =CCI_S2_QOS_CONTROL_BASE(0)
132	ldr	x1, =0x00FF000C
133	bl	ccn504_set_qos
134
135	ldr	x0, =CCI_S0_QOS_CONTROL_BASE(2)
136	ldr	x1, =0x00FF000C
137	bl	ccn504_set_qos
138	ldr	x0, =CCI_S1_QOS_CONTROL_BASE(2)
139	ldr	x1, =0x00FF000C
140	bl	ccn504_set_qos
141	ldr	x0, =CCI_S2_QOS_CONTROL_BASE(2)
142	ldr	x1, =0x00FF000C
143	bl	ccn504_set_qos
144
145	ldr	x0, =CCI_S0_QOS_CONTROL_BASE(6)
146	ldr	x1, =0x00FF000C
147	bl	ccn504_set_qos
148	ldr	x0, =CCI_S1_QOS_CONTROL_BASE(6)
149	ldr	x1, =0x00FF000C
150	bl	ccn504_set_qos
151	ldr	x0, =CCI_S2_QOS_CONTROL_BASE(6)
152	ldr	x1, =0x00FF000C
153	bl	ccn504_set_qos
154
155	ldr	x0, =CCI_S0_QOS_CONTROL_BASE(12)
156	ldr	x1, =0x00FF000C
157	bl	ccn504_set_qos
158	ldr	x0, =CCI_S1_QOS_CONTROL_BASE(12)
159	ldr	x1, =0x00FF000C
160	bl	ccn504_set_qos
161	ldr	x0, =CCI_S2_QOS_CONTROL_BASE(12)
162	ldr	x1, =0x00FF000C
163	bl	ccn504_set_qos
164
165	ldr	x0, =CCI_S0_QOS_CONTROL_BASE(16)
166	ldr	x1, =0x00FF000C
167	bl	ccn504_set_qos
168	ldr	x0, =CCI_S1_QOS_CONTROL_BASE(16)
169	ldr	x1, =0x00FF000C
170	bl	ccn504_set_qos
171	ldr	x0, =CCI_S2_QOS_CONTROL_BASE(16)
172	ldr	x1, =0x00FF000C
173	bl	ccn504_set_qos
174
175	ldr	x0, =CCI_S0_QOS_CONTROL_BASE(20)
176	ldr	x1, =0x00FF000C
177	bl	ccn504_set_qos
178	ldr	x0, =CCI_S1_QOS_CONTROL_BASE(20)
179	ldr	x1, =0x00FF000C
180	bl	ccn504_set_qos
181	ldr	x0, =CCI_S2_QOS_CONTROL_BASE(20)
182	ldr	x1, =0x00FF000C
183	bl	ccn504_set_qos
184#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
185
186#ifdef SMMU_BASE
187	/* Set the SMMU page size in the sACR register */
188	ldr	x1, =SMMU_BASE
189	ldr	w0, [x1, #0x10]
190	orr	w0, w0, #1 << 16  /* set sACR.pagesize to indicate 64K page */
191	str	w0, [x1, #0x10]
192#endif
193
194	/* Initialize GIC Secure Bank Status */
195#if !defined(CONFIG_SPL_BUILD)
196#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
197	branch_if_slave x0, 1f
198	bl	get_gic_offset
199	bl	gic_init_secure
2001:
201#ifdef CONFIG_GICV3
202	ldr	x0, =GICR_BASE
203	bl	gic_init_secure_percpu
204#elif defined(CONFIG_GICV2)
205	bl	get_gic_offset
206	bl	gic_init_secure_percpu
207#endif
208#endif
209#endif
210
211100:
212	branch_if_master x0, x1, 2f
213
214#if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
215	/*
216	 * Formerly, here was a jump to secondary_boot_func, but we just
217	 * return early here and let the generic code in start.S handle
218	 * the jump to secondary_boot_func.
219	 */
220	mov	lr, x29			/* Restore LR */
221	ret
222#endif
223
2242:
225	switch_el x1, 1f, 100f, 100f	/* skip if not in EL3 */
2261:
227#ifdef CONFIG_FSL_TZPC_BP147
228	/* Set Non Secure access for all devices protected via TZPC */
229	ldr	x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
230	orr	w0, w0, #1 << 3 /* DCFG_RESET is accessible from NS world */
231	str	w0, [x1]
232
233	isb
234	dsb	sy
235#endif
236
237#ifdef CONFIG_FSL_TZASC_400
238	/*
239	 * LS2080 and its personalities does not support TZASC
240	 * So skip TZASC related operations
241	 */
242	bl	get_svr
243	lsr	w0, w0, #16
244	ldr	w1, =SVR_DEV(SVR_LS2080A)
245	cmp	w0, w1
246	b.eq	1f
247
248	/* Set TZASC so that:
249	 * a. We use only Region0 whose global secure write/read is EN
250	 * b. We use only Region0 whose NSAID write/read is EN
251	 *
252	 * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
253	 * 	 placeholders.
254	 */
255
256.macro tzasc_prog, xreg
257
258	mov     x12, TZASC1_BASE
259	mov     x16, #0x10000
260	mul     x14, \xreg, x16
261	add     x14, x14,x12
262	mov 	x1, #0x8
263	add     x1, x1, x14
264
265	ldr     w0, [x1]		/* Filter 0 Gate Keeper Register */
266	orr     w0, w0, #1 << 0		/* Set open_request for Filter 0 */
267	str     w0, [x1]
268
269	mov	x1, #0x110
270	add     x1, x1, x14
271
272	ldr     w0, [x1]		/* Region-0 Attributes Register */
273	orr     w0, w0, #1 << 31	/* Set Sec global write en, Bit[31] */
274	orr     w0, w0, #1 << 30	/* Set Sec global read en, Bit[30] */
275	str     w0, [x1]
276
277	mov	x1, #0x114
278	add     x1, x1, x14
279
280	ldr     w0, [x1]		/* Region-0 Access Register */
281	mov     w0, #0xFFFFFFFF		/* Set nsaid_wr_en and nsaid_rd_en */
282	str     w0, [x1]
283.endm
284
285#ifdef CONFIG_FSL_TZASC_1
286	mov     x13, #0
287	tzasc_prog	x13
288
289#endif
290#ifdef CONFIG_FSL_TZASC_2
291	mov     x13, #1
292	tzasc_prog	x13
293
294#endif
295	isb
296	dsb	sy
297#endif
298100:
2991:
300#ifdef CONFIG_ARCH_LS1046A
301	switch_el x1, 1f, 100f, 100f	/* skip if not in EL3 */
3021:
303	/* Initialize the L2 RAM latency */
304	mrs   x1, S3_1_c11_c0_2
305	mov   x0, #0x1C7
306	/* Clear L2 Tag RAM latency and L2 Data RAM latency */
307	bic   x1, x1, x0
308	/* Set L2 data ram latency bits [2:0] */
309	orr   x1, x1, #0x2
310	/* set L2 tag ram latency bits [8:6] */
311	orr   x1,  x1, #0x80
312	msr   S3_1_c11_c0_2, x1
313	isb
314100:
315#endif
316
317#if !defined(CONFIG_TFABOOT) && \
318	(defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD))
319	bl	fsl_ocram_init
320#endif
321
322	mov	lr, x29			/* Restore LR */
323	ret
324ENDPROC(lowlevel_init)
325
326#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
327ENTRY(fsl_ocram_init)
328	mov	x28, lr			/* Save LR */
329	bl	fsl_clear_ocram
330	bl	fsl_ocram_clear_ecc_err
331	mov	lr, x28			/* Restore LR */
332	ret
333ENDPROC(fsl_ocram_init)
334
335ENTRY(fsl_clear_ocram)
336/* Clear OCRAM */
337	ldr	x0, =CONFIG_SYS_FSL_OCRAM_BASE
338	ldr	x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE)
339	mov	x2, #0
340clear_loop:
341	str	x2, [x0]
342	add	x0, x0, #8
343	cmp	x0, x1
344	b.lo	clear_loop
345	ret
346ENDPROC(fsl_clear_ocram)
347
348ENTRY(fsl_ocram_clear_ecc_err)
349	/* OCRAM1/2 ECC status bit */
350	mov	w1, #0x60
351	ldr	x0, =DCSR_DCFG_SBEESR2
352	str	w1, [x0]
353	ldr	x0, =DCSR_DCFG_MBEESR2
354	str	w1, [x0]
355	ret
356ENDPROC(fsl_ocram_init)
357#endif
358
359#ifdef CONFIG_FSL_LSCH3
360	.globl get_svr
361get_svr:
362	ldr	x1, =FSL_LSCH3_SVR
363	ldr	w0, [x1]
364	ret
365#endif
366
367#if defined(CONFIG_SYS_FSL_HAS_CCN504) || defined(CONFIG_SYS_FSL_HAS_CCN508)
368hnf_pstate_poll:
369	/* x0 has the desired status, return only if operation succeed
370	 * clobber x1, x2, x6
371	 */
372	mov	x1, x0
373	mov	w6, #8			/* HN-F node count */
374	mov	x0, #0x18
375	movk	x0, #0x420, lsl #16	/* HNF0_PSTATE_STATUS */
3761:
377	ldr	x2, [x0]
378	cmp	x2, x1			/* check status */
379	b.eq	2f
380	b	1b
3812:
382	add	x0, x0, #0x10000	/* move to next node */
383	subs	w6, w6, #1
384	cbnz	w6, 1b
385	ret
386
387hnf_set_pstate:
388	/* x0 has the desired state, clobber x1, x2, x6 */
389	mov	x1, x0
390	/* power state to SFONLY */
391	mov	w6, #8			/* HN-F node count */
392	mov	x0, #0x10
393	movk	x0, #0x420, lsl #16	/* HNF0_PSTATE_REQ */
3941:	/* set pstate to sfonly */
395	ldr	x2, [x0]
396	and	x2, x2, #0xfffffffffffffffc	/* & HNFPSTAT_MASK */
397	orr	x2, x2, x1
398	str	x2, [x0]
399	add	x0, x0, #0x10000	/* move to next node */
400	subs	w6, w6, #1
401	cbnz	w6, 1b
402
403	ret
404
405ENTRY(__asm_flush_l3_dcache)
406	/*
407	 * Return status in x0
408	 *    success 0
409	 */
410	mov	x29, lr
411
412	dsb	sy
413	mov	x0, #0x1		/* HNFPSTAT_SFONLY */
414	bl	hnf_set_pstate
415
416	mov	x0, #0x4		/* SFONLY status */
417	bl	hnf_pstate_poll
418
419	dsb	sy
420	mov	x0, #0x3		/* HNFPSTAT_FAM */
421	bl	hnf_set_pstate
422
423	mov	x0, #0xc		/* FAM status */
424	bl	hnf_pstate_poll
425
426	mov	x0, #0
427	mov	lr, x29
428	ret
429ENDPROC(__asm_flush_l3_dcache)
430#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
431