1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
4  * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
5  */
6 
7 #ifndef _SERIAL_STM32_
8 #define _SERIAL_STM32_
9 
10 #include <linux/bitops.h>
11 #define CR1_OFFSET(x)	(x ? 0x0c : 0x00)
12 #define CR3_OFFSET(x)	(x ? 0x14 : 0x08)
13 #define BRR_OFFSET(x)	(x ? 0x08 : 0x0c)
14 #define ISR_OFFSET(x)	(x ? 0x00 : 0x1c)
15 
16 #define ICR_OFFSET	0x20
17 
18 /*
19  * STM32F4 has one Data Register (DR) for received or transmitted
20  * data, so map Receive Data Register (RDR) and Transmit Data
21  * Register (TDR) at the same offset
22  */
23 #define RDR_OFFSET(x)	(x ? 0x04 : 0x24)
24 #define TDR_OFFSET(x)	(x ? 0x04 : 0x28)
25 
26 struct stm32_uart_info {
27 	u8 uart_enable_bit;	/* UART_CR1_UE */
28 	bool stm32f4;		/* true for STM32F4, false otherwise */
29 	bool has_fifo;
30 };
31 
32 struct stm32_uart_info stm32f4_info = {
33 	.stm32f4 = true,
34 	.uart_enable_bit = 13,
35 	.has_fifo = false,
36 };
37 
38 struct stm32_uart_info stm32f7_info = {
39 	.uart_enable_bit = 0,
40 	.stm32f4 = false,
41 	.has_fifo = true,
42 };
43 
44 struct stm32_uart_info stm32h7_info = {
45 	.uart_enable_bit = 0,
46 	.stm32f4 = false,
47 	.has_fifo = true,
48 };
49 
50 /* Information about a serial port */
51 struct stm32x7_serial_plat {
52 	fdt_addr_t base;  /* address of registers in physical memory */
53 	struct stm32_uart_info *uart_info;
54 	unsigned long int clock_rate;
55 };
56 
57 #define USART_CR1_FIFOEN		BIT(29)
58 #define USART_CR1_M1			BIT(28)
59 #define USART_CR1_OVER8			BIT(15)
60 #define USART_CR1_M0			BIT(12)
61 #define USART_CR1_PCE			BIT(10)
62 #define USART_CR1_PS			BIT(9)
63 #define USART_CR1_TE			BIT(3)
64 #define USART_CR1_RE			BIT(2)
65 
66 #define USART_CR3_OVRDIS		BIT(12)
67 
68 #define USART_ISR_TXE			BIT(7)
69 #define USART_ISR_RXNE			BIT(5)
70 #define USART_ISR_ORE			BIT(3)
71 #define USART_ISR_FE			BIT(1)
72 #define USART_ISR_PE			BIT(0)
73 
74 #define USART_BRR_F_MASK		GENMASK(7, 0)
75 #define USART_BRR_M_SHIFT		4
76 #define USART_BRR_M_MASK		GENMASK(15, 4)
77 
78 #define USART_ICR_ORECF			BIT(3)
79 #define USART_ICR_FECF			BIT(1)
80 #define USART_ICR_PCECF			BIT(0)
81 
82 #endif
83