1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
4 * Copyright (C) 2010 Freescale Semiconductor, Inc.
5 */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <log.h>
10 #include <usb.h>
11 #include <errno.h>
12 #include <wait_bit.h>
13 #include <asm/global_data.h>
14 #include <linux/compiler.h>
15 #include <linux/delay.h>
16 #include <usb/ehci-ci.h>
17 #include <asm/io.h>
18 #include <asm/arch/imx-regs.h>
19 #include <asm/arch/clock.h>
20 #include <asm/mach-imx/iomux-v3.h>
21 #include <asm/mach-imx/sys_proto.h>
22 #include <dm.h>
23 #include <asm/mach-types.h>
24 #include <power/regulator.h>
25 #include <linux/usb/otg.h>
26
27 #include "ehci.h"
28
29 DECLARE_GLOBAL_DATA_PTR;
30
31 #define USB_OTGREGS_OFFSET 0x000
32 #define USB_H1REGS_OFFSET 0x200
33 #define USB_H2REGS_OFFSET 0x400
34 #define USB_H3REGS_OFFSET 0x600
35 #define USB_OTHERREGS_OFFSET 0x800
36
37 #define USB_H1_CTRL_OFFSET 0x04
38
39 #define USBPHY_CTRL 0x00000030
40 #define USBPHY_CTRL_SET 0x00000034
41 #define USBPHY_CTRL_CLR 0x00000038
42 #define USBPHY_CTRL_TOG 0x0000003c
43
44 #define USBPHY_PWD 0x00000000
45 #define USBPHY_CTRL_SFTRST 0x80000000
46 #define USBPHY_CTRL_CLKGATE 0x40000000
47 #define USBPHY_CTRL_ENUTMILEVEL3 0x00008000
48 #define USBPHY_CTRL_ENUTMILEVEL2 0x00004000
49 #define USBPHY_CTRL_OTG_ID 0x08000000
50
51 #define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
52 #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
53
54 #define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
55 #define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
56 #define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
57 #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
58
59 #define USBNC_OFFSET 0x200
60 #define USBNC_PHY_STATUS_OFFSET 0x23C
61 #define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */
62 #define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */
63 #define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */
64 #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
65 #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
66
67 /* USBCMD */
68 #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
69 #define UCMD_RESET (1 << 1) /* controller reset */
70
71 /* If this is not defined, assume MX6/MX7/MX8M SoC default */
72 #ifndef CONFIG_MXC_USB_PORTSC
73 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
74 #endif
75
76 /* Base address for this IP block is 0x02184800 */
77 struct usbnc_regs {
78 u32 ctrl[4]; /* otg/host1-3 */
79 u32 uh2_hsic_ctrl;
80 u32 uh3_hsic_ctrl;
81 u32 otg_phy_ctrl_0;
82 u32 uh1_phy_ctrl_0;
83 u32 reserve1[4];
84 u32 phy_cfg1;
85 u32 phy_cfg2;
86 u32 reserve2;
87 u32 phy_status;
88 u32 reserve3[4];
89 u32 adp_cfg1;
90 u32 adp_cfg2;
91 u32 adp_status;
92 };
93
94 #if defined(CONFIG_MX6) && !defined(CONFIG_PHY)
usb_power_config_mx6(struct anatop_regs __iomem * anatop,int anatop_bits_index)95 static void usb_power_config_mx6(struct anatop_regs __iomem *anatop,
96 int anatop_bits_index)
97 {
98 void __iomem *chrg_detect;
99 void __iomem *pll_480_ctrl_clr;
100 void __iomem *pll_480_ctrl_set;
101
102 if (!is_mx6())
103 return;
104
105 switch (anatop_bits_index) {
106 case 0:
107 chrg_detect = &anatop->usb1_chrg_detect;
108 pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
109 pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
110 break;
111 case 1:
112 chrg_detect = &anatop->usb2_chrg_detect;
113 pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
114 pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
115 break;
116 default:
117 return;
118 }
119 /*
120 * Some phy and power's special controls
121 * 1. The external charger detector needs to be disabled
122 * or the signal at DP will be poor
123 * 2. The PLL's power and output to usb
124 * is totally controlled by IC, so the Software only needs
125 * to enable them at initializtion.
126 */
127 writel(ANADIG_USB2_CHRG_DETECT_EN_B |
128 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
129 chrg_detect);
130
131 writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
132 pll_480_ctrl_clr);
133
134 writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
135 ANADIG_USB2_PLL_480_CTRL_POWER |
136 ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
137 pll_480_ctrl_set);
138 }
139 #else
140 static void __maybe_unused
usb_power_config_mx6(void * anatop,int anatop_bits_index)141 usb_power_config_mx6(void *anatop, int anatop_bits_index) { }
142 #endif
143
144 #if defined(CONFIG_MX7) && !defined(CONFIG_PHY)
usb_power_config_mx7(struct usbnc_regs * usbnc)145 static void usb_power_config_mx7(struct usbnc_regs *usbnc)
146 {
147 void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
148
149 if (!is_mx7())
150 return;
151
152 /*
153 * Clear the ACAENB to enable usb_otg_id detection,
154 * otherwise it is the ACA detection enabled.
155 */
156 clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
157 }
158 #else
159 static void __maybe_unused
usb_power_config_mx7(void * usbnc)160 usb_power_config_mx7(void *usbnc) { }
161 #endif
162
163 #if defined(CONFIG_MX7ULP) && !defined(CONFIG_PHY)
usb_power_config_mx7ulp(struct usbphy_regs __iomem * usbphy)164 static void usb_power_config_mx7ulp(struct usbphy_regs __iomem *usbphy)
165 {
166 if (!is_mx7ulp())
167 return;
168
169 writel(ANADIG_USB2_CHRG_DETECT_EN_B |
170 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
171 &usbphy->usb1_chrg_detect);
172
173 scg_enable_usb_pll(true);
174 }
175 #else
176 static void __maybe_unused
usb_power_config_mx7ulp(void * usbphy)177 usb_power_config_mx7ulp(void *usbphy) { }
178 #endif
179
180 #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
181 static const unsigned phy_bases[] = {
182 USB_PHY0_BASE_ADDR,
183 #if defined(USB_PHY1_BASE_ADDR)
184 USB_PHY1_BASE_ADDR,
185 #endif
186 };
187
188 #if !defined(CONFIG_PHY)
usb_internal_phy_clock_gate(void __iomem * phy_reg,int on)189 static void usb_internal_phy_clock_gate(void __iomem *phy_reg, int on)
190 {
191 phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
192 writel(USBPHY_CTRL_CLKGATE, phy_reg);
193 }
194
195 /* Return 0 : host node, <>0 : device mode */
usb_phy_enable(struct usb_ehci * ehci,void __iomem * phy_reg)196 static int usb_phy_enable(struct usb_ehci *ehci, void __iomem *phy_reg)
197 {
198 void __iomem *phy_ctrl;
199 void __iomem *usb_cmd;
200 int ret;
201
202 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
203 usb_cmd = (void __iomem *)&ehci->usbcmd;
204
205 /* Stop then Reset */
206 clrbits_le32(usb_cmd, UCMD_RUN_STOP);
207 ret = wait_for_bit_le32(usb_cmd, UCMD_RUN_STOP, false, 10000, false);
208 if (ret)
209 return ret;
210
211 setbits_le32(usb_cmd, UCMD_RESET);
212 ret = wait_for_bit_le32(usb_cmd, UCMD_RESET, false, 10000, false);
213 if (ret)
214 return ret;
215
216 /* Reset USBPHY module */
217 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
218 udelay(10);
219
220 /* Remove CLKGATE and SFTRST */
221 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
222 udelay(10);
223
224 /* Power up the PHY */
225 writel(0, phy_reg + USBPHY_PWD);
226 /* enable FS/LS device */
227 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
228 USBPHY_CTRL_ENUTMILEVEL3);
229
230 return 0;
231 }
232 #endif
233
usb_phy_mode(int port)234 int usb_phy_mode(int port)
235 {
236 void __iomem *phy_reg;
237 void __iomem *phy_ctrl;
238 u32 val;
239
240 phy_reg = (void __iomem *)phy_bases[port];
241 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
242
243 val = readl(phy_ctrl);
244
245 if (val & USBPHY_CTRL_OTG_ID)
246 return USB_INIT_DEVICE;
247 else
248 return USB_INIT_HOST;
249 }
250
251 #elif defined(CONFIG_MX7)
usb_phy_mode(int port)252 int usb_phy_mode(int port)
253 {
254 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
255 (0x10000 * port) + USBNC_OFFSET);
256 void __iomem *status = (void __iomem *)(&usbnc->phy_status);
257 u32 val;
258
259 val = readl(status);
260
261 if (val & USBNC_PHYSTATUS_ID_DIG)
262 return USB_INIT_DEVICE;
263 else
264 return USB_INIT_HOST;
265 }
266 #endif
267
268 #if !defined(CONFIG_PHY)
269 /* Should be done in the MXS PHY driver */
usb_oc_config(struct usbnc_regs * usbnc,int index)270 static void usb_oc_config(struct usbnc_regs *usbnc, int index)
271 {
272 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
273
274 #if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
275 /* mx6qarm2 seems to required a different setting*/
276 clrbits_le32(ctrl, UCTRL_OVER_CUR_POL);
277 #else
278 setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
279 #endif
280
281 setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
282
283 /* Set power polarity to high active */
284 #ifdef CONFIG_MXC_USB_OTG_HACTIVE
285 setbits_le32(ctrl, UCTRL_PWR_POL);
286 #else
287 clrbits_le32(ctrl, UCTRL_PWR_POL);
288 #endif
289 }
290 #endif
291
292 #if !CONFIG_IS_ENABLED(DM_USB)
293 /**
294 * board_usb_phy_mode - override usb phy mode
295 * @port: usb host/otg port
296 *
297 * Target board specific, override usb_phy_mode.
298 * When usb-otg is used as usb host port, iomux pad usb_otg_id can be
299 * left disconnected in this case usb_phy_mode will not be able to identify
300 * the phy mode that usb port is used.
301 * Machine file overrides board_usb_phy_mode.
302 *
303 * Return: USB_INIT_DEVICE or USB_INIT_HOST
304 */
board_usb_phy_mode(int port)305 int __weak board_usb_phy_mode(int port)
306 {
307 return usb_phy_mode(port);
308 }
309
310 /**
311 * board_ehci_hcd_init - set usb vbus voltage
312 * @port: usb otg port
313 *
314 * Target board specific, setup iomux pad to setup supply vbus voltage
315 * for usb otg port. Machine board file overrides board_ehci_hcd_init
316 *
317 * Return: 0 Success
318 */
board_ehci_hcd_init(int port)319 int __weak board_ehci_hcd_init(int port)
320 {
321 return 0;
322 }
323
324 /**
325 * board_ehci_power - enables/disables usb vbus voltage
326 * @port: usb otg port
327 * @on: on/off vbus voltage
328 *
329 * Enables/disables supply vbus voltage for usb otg port.
330 * Machine board file overrides board_ehci_power
331 *
332 * Return: 0 Success
333 */
board_ehci_power(int port,int on)334 int __weak board_ehci_power(int port, int on)
335 {
336 return 0;
337 }
338
ehci_hcd_init(int index,enum usb_init_type init,struct ehci_hccr ** hccr,struct ehci_hcor ** hcor)339 int ehci_hcd_init(int index, enum usb_init_type init,
340 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
341 {
342 enum usb_init_type type;
343 #if defined(CONFIG_MX6) || defined(CONFIG_IMXRT)
344 u32 controller_spacing = 0x200;
345 struct anatop_regs __iomem *anatop =
346 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
347 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
348 USB_OTHERREGS_OFFSET);
349 #elif defined(CONFIG_MX7)
350 u32 controller_spacing = 0x10000;
351 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
352 (0x10000 * index) + USBNC_OFFSET);
353 #elif defined(CONFIG_MX7ULP)
354 u32 controller_spacing = 0x10000;
355 struct usbphy_regs __iomem *usbphy =
356 (struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR;
357 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
358 (0x10000 * index) + USBNC_OFFSET);
359 #endif
360 struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
361 (controller_spacing * index));
362 int ret;
363
364 if (index > 3)
365 return -EINVAL;
366
367 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
368 if (usb_fused((ulong)ehci)) {
369 printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
370 (ulong)ehci);
371 return -ENODEV;
372 }
373 }
374
375 enable_usboh3_clk(1);
376 mdelay(1);
377
378 /* Do board specific initialization */
379 ret = board_ehci_hcd_init(index);
380 if (ret) {
381 enable_usboh3_clk(0);
382 return ret;
383 }
384
385 #if defined(CONFIG_MX6) || defined(CONFIG_IMXRT)
386 usb_power_config_mx6(anatop, index);
387 #elif defined (CONFIG_MX7)
388 usb_power_config_mx7(usbnc);
389 #elif defined (CONFIG_MX7ULP)
390 usb_power_config_mx7ulp(usbphy);
391 #endif
392
393 usb_oc_config(usbnc, index);
394
395 #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
396 if (index < ARRAY_SIZE(phy_bases)) {
397 usb_internal_phy_clock_gate((void __iomem *)phy_bases[index], 1);
398 usb_phy_enable(ehci, (void __iomem *)phy_bases[index]);
399 }
400 #endif
401
402 type = board_usb_phy_mode(index);
403
404 if (hccr && hcor) {
405 *hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);
406 *hcor = (struct ehci_hcor *)((uintptr_t)*hccr +
407 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
408 }
409
410 if ((type == init) || (type == USB_INIT_DEVICE))
411 board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
412 if (type != init)
413 return -ENODEV;
414 if (type == USB_INIT_DEVICE)
415 return 0;
416
417 setbits_le32(&ehci->usbmode, CM_HOST);
418 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
419 setbits_le32(&ehci->portsc, USB_EN);
420
421 mdelay(10);
422
423 return 0;
424 }
425
ehci_hcd_stop(int index)426 int ehci_hcd_stop(int index)
427 {
428 return 0;
429 }
430 #else
431 struct ehci_mx6_priv_data {
432 struct ehci_ctrl ctrl;
433 struct usb_ehci *ehci;
434 struct udevice *vbus_supply;
435 struct clk clk;
436 struct phy phy;
437 enum usb_init_type init_type;
438 #if !defined(CONFIG_PHY)
439 int portnr;
440 void __iomem *phy_addr;
441 void __iomem *misc_addr;
442 void __iomem *anatop_addr;
443 #endif
444 };
445
mx6_init_after_reset(struct ehci_ctrl * dev)446 static int mx6_init_after_reset(struct ehci_ctrl *dev)
447 {
448 struct ehci_mx6_priv_data *priv = dev->priv;
449 enum usb_init_type type = priv->init_type;
450 struct usb_ehci *ehci = priv->ehci;
451
452 #if !defined(CONFIG_PHY)
453 usb_power_config_mx6(priv->anatop_addr, priv->portnr);
454 usb_power_config_mx7(priv->misc_addr);
455 usb_power_config_mx7ulp(priv->phy_addr);
456
457 usb_oc_config(priv->misc_addr, priv->portnr);
458
459 #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
460 usb_internal_phy_clock_gate(priv->phy_addr, 1);
461 usb_phy_enable(ehci, priv->phy_addr);
462 #endif
463 #endif
464
465 #if CONFIG_IS_ENABLED(DM_REGULATOR)
466 if (priv->vbus_supply) {
467 int ret;
468 ret = regulator_set_enable(priv->vbus_supply,
469 (type == USB_INIT_DEVICE) ?
470 false : true);
471 if (ret && ret != -ENOSYS) {
472 printf("Error enabling VBUS supply (ret=%i)\n", ret);
473 return ret;
474 }
475 }
476 #endif
477
478 if (type == USB_INIT_DEVICE)
479 return 0;
480
481 setbits_le32(&ehci->usbmode, CM_HOST);
482 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
483 setbits_le32(&ehci->portsc, USB_EN);
484
485 mdelay(10);
486
487 return 0;
488 }
489
490 static const struct ehci_ops mx6_ehci_ops = {
491 .init_after_reset = mx6_init_after_reset
492 };
493
ehci_usb_phy_mode(struct udevice * dev)494 static int ehci_usb_phy_mode(struct udevice *dev)
495 {
496 struct usb_plat *plat = dev_get_plat(dev);
497 void *__iomem addr = dev_read_addr_ptr(dev);
498 void *__iomem phy_ctrl, *__iomem phy_status;
499 const void *blob = gd->fdt_blob;
500 int offset = dev_of_offset(dev), phy_off;
501 u32 val;
502
503 /*
504 * About fsl,usbphy, Refer to
505 * Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt.
506 */
507 if (is_mx6() || is_mx7ulp() || is_imxrt()) {
508 phy_off = fdtdec_lookup_phandle(blob,
509 offset,
510 "fsl,usbphy");
511 if (phy_off < 0)
512 return -EINVAL;
513
514 addr = (void __iomem *)fdtdec_get_addr(blob, phy_off,
515 "reg");
516 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
517 return -EINVAL;
518
519 phy_ctrl = (void __iomem *)(addr + USBPHY_CTRL);
520 val = readl(phy_ctrl);
521
522 if (val & USBPHY_CTRL_OTG_ID)
523 plat->init_type = USB_INIT_DEVICE;
524 else
525 plat->init_type = USB_INIT_HOST;
526 } else if (is_mx7()) {
527 phy_status = (void __iomem *)(addr +
528 USBNC_PHY_STATUS_OFFSET);
529 val = readl(phy_status);
530
531 if (val & USBNC_PHYSTATUS_ID_DIG)
532 plat->init_type = USB_INIT_DEVICE;
533 else
534 plat->init_type = USB_INIT_HOST;
535 } else {
536 return -EINVAL;
537 }
538
539 return 0;
540 }
541
ehci_usb_of_to_plat(struct udevice * dev)542 static int ehci_usb_of_to_plat(struct udevice *dev)
543 {
544 struct usb_plat *plat = dev_get_plat(dev);
545 enum usb_dr_mode dr_mode;
546
547 dr_mode = usb_get_dr_mode(dev_ofnode(dev));
548
549 switch (dr_mode) {
550 case USB_DR_MODE_HOST:
551 plat->init_type = USB_INIT_HOST;
552 break;
553 case USB_DR_MODE_PERIPHERAL:
554 plat->init_type = USB_INIT_DEVICE;
555 break;
556 case USB_DR_MODE_OTG:
557 case USB_DR_MODE_UNKNOWN:
558 return ehci_usb_phy_mode(dev);
559 };
560
561 return 0;
562 }
563
mx6_parse_dt_addrs(struct udevice * dev)564 static int mx6_parse_dt_addrs(struct udevice *dev)
565 {
566 #if !defined(CONFIG_PHY)
567 struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
568 int phy_off, misc_off;
569 const void *blob = gd->fdt_blob;
570 int offset = dev_of_offset(dev);
571 void *__iomem addr;
572
573 phy_off = fdtdec_lookup_phandle(blob, offset, "fsl,usbphy");
574 if (phy_off < 0) {
575 phy_off = fdtdec_lookup_phandle(blob, offset, "phys");
576 if (phy_off < 0)
577 return -EINVAL;
578 }
579
580 misc_off = fdtdec_lookup_phandle(blob, offset, "fsl,usbmisc");
581 if (misc_off < 0)
582 return -EINVAL;
583
584 addr = (void __iomem *)fdtdec_get_addr(blob, phy_off, "reg");
585 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
586 addr = NULL;
587
588 priv->phy_addr = addr;
589
590 addr = (void __iomem *)fdtdec_get_addr(blob, misc_off, "reg");
591 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
592 return -EINVAL;
593
594 priv->misc_addr = addr;
595
596 #if defined(CONFIG_MX6)
597 int anatop_off, ret, devnump;
598
599 ret = fdtdec_get_alias_seq(blob, dev->uclass->uc_drv->name,
600 phy_off, &devnump);
601 if (ret < 0)
602 return ret;
603 priv->portnr = devnump;
604
605 /* Resolve ANATOP offset through USB PHY node */
606 anatop_off = fdtdec_lookup_phandle(blob, phy_off, "fsl,anatop");
607 if (anatop_off < 0)
608 return -EINVAL;
609
610 addr = (void __iomem *)fdtdec_get_addr(blob, anatop_off, "reg");
611 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
612 return -EINVAL;
613
614 priv->anatop_addr = addr;
615 #endif
616 #endif
617 return 0;
618 }
619
ehci_usb_probe(struct udevice * dev)620 static int ehci_usb_probe(struct udevice *dev)
621 {
622 struct usb_plat *plat = dev_get_plat(dev);
623 struct usb_ehci *ehci = dev_read_addr_ptr(dev);
624 struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
625 enum usb_init_type type = plat->init_type;
626 struct ehci_hccr *hccr;
627 struct ehci_hcor *hcor;
628 int ret;
629
630 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
631 if (usb_fused((ulong)ehci)) {
632 printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
633 (ulong)ehci);
634 return -ENODEV;
635 }
636 }
637
638 ret = mx6_parse_dt_addrs(dev);
639 if (ret)
640 return ret;
641
642 priv->ehci = ehci;
643 priv->init_type = type;
644
645 #if CONFIG_IS_ENABLED(CLK)
646 ret = clk_get_by_index(dev, 0, &priv->clk);
647 if (ret < 0)
648 return ret;
649
650 ret = clk_enable(&priv->clk);
651 if (ret)
652 return ret;
653 #else
654 /* Compatibility with DM_USB and !CLK */
655 enable_usboh3_clk(1);
656 mdelay(1);
657 #endif
658
659 #if CONFIG_IS_ENABLED(DM_REGULATOR)
660 ret = device_get_supply_regulator(dev, "vbus-supply",
661 &priv->vbus_supply);
662 if (ret)
663 debug("%s: No vbus supply\n", dev->name);
664 #endif
665
666 #if !defined(CONFIG_PHY)
667 usb_power_config_mx6(priv->anatop_addr, priv->portnr);
668 usb_power_config_mx7(priv->misc_addr);
669 usb_power_config_mx7ulp(priv->phy_addr);
670
671 usb_oc_config(priv->misc_addr, priv->portnr);
672
673 #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
674 usb_internal_phy_clock_gate(priv->phy_addr, 1);
675 usb_phy_enable(ehci, priv->phy_addr);
676 #endif
677 #endif
678
679 #if CONFIG_IS_ENABLED(DM_REGULATOR)
680 if (priv->vbus_supply) {
681 ret = regulator_set_enable(priv->vbus_supply,
682 (type == USB_INIT_DEVICE) ?
683 false : true);
684 if (ret && ret != -ENOSYS) {
685 printf("Error enabling VBUS supply (ret=%i)\n", ret);
686 goto err_clk;
687 }
688 }
689 #endif
690
691 if (priv->init_type == USB_INIT_HOST) {
692 setbits_le32(&ehci->usbmode, CM_HOST);
693 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
694 setbits_le32(&ehci->portsc, USB_EN);
695 }
696
697 mdelay(10);
698
699 #if defined(CONFIG_PHY)
700 ret = ehci_setup_phy(dev, &priv->phy, 0);
701 if (ret)
702 goto err_regulator;
703 #endif
704
705 hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);
706 hcor = (struct ehci_hcor *)((uintptr_t)hccr +
707 HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
708
709 ret = ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type);
710 if (ret)
711 goto err_phy;
712
713 return ret;
714
715 err_phy:
716 #if defined(CONFIG_PHY)
717 ehci_shutdown_phy(dev, &priv->phy);
718 err_regulator:
719 #endif
720 #if CONFIG_IS_ENABLED(DM_REGULATOR)
721 if (priv->vbus_supply)
722 regulator_set_enable(priv->vbus_supply, false);
723 err_clk:
724 #endif
725 #if CONFIG_IS_ENABLED(CLK)
726 clk_disable(&priv->clk);
727 #else
728 /* Compatibility with DM_USB and !CLK */
729 enable_usboh3_clk(0);
730 #endif
731 return ret;
732 }
733
ehci_usb_remove(struct udevice * dev)734 int ehci_usb_remove(struct udevice *dev)
735 {
736 struct ehci_mx6_priv_data *priv __maybe_unused = dev_get_priv(dev);
737
738 ehci_deregister(dev);
739
740 #if defined(CONFIG_PHY)
741 ehci_shutdown_phy(dev, &priv->phy);
742 #endif
743
744 #if CONFIG_IS_ENABLED(DM_REGULATOR)
745 if (priv->vbus_supply)
746 regulator_set_enable(priv->vbus_supply, false);
747 #endif
748
749 #if CONFIG_IS_ENABLED(CLK)
750 clk_disable(&priv->clk);
751 #endif
752
753 return 0;
754 }
755
756 static const struct udevice_id mx6_usb_ids[] = {
757 { .compatible = "fsl,imx27-usb" },
758 { .compatible = "fsl,imx7d-usb" },
759 { .compatible = "fsl,imxrt-usb" },
760 { }
761 };
762
763 U_BOOT_DRIVER(usb_mx6) = {
764 .name = "ehci_mx6",
765 .id = UCLASS_USB,
766 .of_match = mx6_usb_ids,
767 .of_to_plat = ehci_usb_of_to_plat,
768 .probe = ehci_usb_probe,
769 .remove = ehci_usb_remove,
770 .ops = &ehci_usb_ops,
771 .plat_auto = sizeof(struct usb_plat),
772 .priv_auto = sizeof(struct ehci_mx6_priv_data),
773 .flags = DM_FLAG_ALLOC_PRIV_DMA,
774 };
775 #endif
776