1 /* SPDX-License-Identifier: GPL-2.0+ 2 * 3 * Copyright (C) 2016 Nexell Co., Ltd. 4 * 5 * Author: junghyun, kim <jhkim@nexell.co.kr> 6 */ 7 8 #ifndef _S5PXX18_SOC_HDMI_H_ 9 #define _S5PXX18_SOC_HDMI_H_ 10 11 #include "s5pxx18_soc_disptop.h" 12 13 #define PHY_BASEADDR_HDMI_PHY_MODULE 0xc00f0000 14 #define PHY_BASEADDR_HDMI_LIST \ 15 { PHY_BASEADDR_HDMI_MODULE } 16 17 #define HDMI_LINK_INTC_CON_0 (HDMI_ADDR_OFFSET + 0x00000000) 18 #define HDMI_LINK_INTC_FLAG_0 (HDMI_ADDR_OFFSET + 0x00000004) 19 #define HDMI_LINK_AESKEY_VALID (HDMI_ADDR_OFFSET + 0x00000008) 20 #define HDMI_LINK_HPD (HDMI_ADDR_OFFSET + 0x0000000C) 21 #define HDMI_LINK_INTC_CON_1 (HDMI_ADDR_OFFSET + 0x00000010) 22 #define HDMI_LINK_INTC_FLAG_1 (HDMI_ADDR_OFFSET + 0x00000014) 23 #define HDMI_LINK_PHY_STATUS_0 (HDMI_ADDR_OFFSET + 0x00000020) 24 #define HDMI_LINK_PHY_STATUS_CMU (HDMI_ADDR_OFFSET + 0x00000024) 25 #define HDMI_LINK_PHY_STATUS_PLL (HDMI_ADDR_OFFSET + 0x00000028) 26 #define HDMI_LINK_PHY_CON_0 (HDMI_ADDR_OFFSET + 0x00000030) 27 #define HDMI_LINK_HPD_CTRL (HDMI_ADDR_OFFSET + 0x00000040) 28 #define HDMI_LINK_HPD_STATUS (HDMI_ADDR_OFFSET + 0x00000044) 29 #define HDMI_LINK_HPD_TH_x (HDMI_ADDR_OFFSET + 0x00000050) 30 31 #define HDMI_LINK_HDMI_CON_0 (HDMI_ADDR_OFFSET + 0x00010000) 32 #define HDMI_LINK_HDMI_CON_1 (HDMI_ADDR_OFFSET + 0x00010004) 33 #define HDMI_LINK_HDMI_CON_2 (HDMI_ADDR_OFFSET + 0x00010008) 34 #define HDMI_LINK_STATUS (HDMI_ADDR_OFFSET + 0x00010010) 35 #define HDMI_LINK_STATUS_EN (HDMI_ADDR_OFFSET + 0x00010020) 36 37 #define HDMI_LINK_HDCP_SHA1_REN0 (HDMI_ADDR_OFFSET + 0x00010024) 38 #define HDMI_LINK_HDCP_SHA1_REN1 (HDMI_ADDR_OFFSET + 0x00010028) 39 40 #define HDMI_LINK_MODE_SEL (HDMI_ADDR_OFFSET + 0x00010040) 41 #define HDMI_LINK_ENC_EN (HDMI_ADDR_OFFSET + 0x00010044) 42 #define HDMI_LINK_HDMI_YMAX (HDMI_ADDR_OFFSET + 0x00010060) 43 #define HDMI_LINK_HDMI_YMIN (HDMI_ADDR_OFFSET + 0x00010064) 44 #define HDMI_LINK_HDMI_CMAX (HDMI_ADDR_OFFSET + 0x00010068) 45 #define HDMI_LINK_HDMI_CMIN (HDMI_ADDR_OFFSET + 0x0001006C) 46 #define HDMI_LINK_H_BLANK_0 (HDMI_ADDR_OFFSET + 0x000100A0) 47 #define HDMI_LINK_H_BLANK_1 (HDMI_ADDR_OFFSET + 0x000100A4) 48 #define HDMI_LINK_V2_BLANK_0 (HDMI_ADDR_OFFSET + 0x000100B0) 49 #define HDMI_LINK_V2_BLANK_1 (HDMI_ADDR_OFFSET + 0x000100B4) 50 #define HDMI_LINK_V1_BLANK_0 (HDMI_ADDR_OFFSET + 0x000100B8) 51 #define HDMI_LINK_V1_BLANK_1 (HDMI_ADDR_OFFSET + 0x000100BC) 52 #define HDMI_LINK_V_LINE_0 (HDMI_ADDR_OFFSET + 0x000100C0) 53 #define HDMI_LINK_V_LINE_1 (HDMI_ADDR_OFFSET + 0x000100C4) 54 #define HDMI_LINK_H_LINE_0 (HDMI_ADDR_OFFSET + 0x000100C8) 55 #define HDMI_LINK_H_LINE_1 (HDMI_ADDR_OFFSET + 0x000100CC) 56 #define HDMI_LINK_HSYNC_POL (HDMI_ADDR_OFFSET + 0x000100E0) 57 #define HDMI_LINK_VSYNC_POL (HDMI_ADDR_OFFSET + 0x000100E4) 58 #define HDMI_LINK_INT_PRO_MODE (HDMI_ADDR_OFFSET + 0x000100E8) 59 #define HDMI_LINK_SEND_START_0 (HDMI_ADDR_OFFSET + 0x000100F0) 60 #define HDMI_LINK_SEND_START_1 (HDMI_ADDR_OFFSET + 0x000100F4) 61 #define HDMI_LINK_SEND_END_0 (HDMI_ADDR_OFFSET + 0x00010100) 62 #define HDMI_LINK_SEND_END_1 (HDMI_ADDR_OFFSET + 0x00010104) 63 #define HDMI_LINK_SEND_END_2 (HDMI_ADDR_OFFSET + 0x00010108) 64 #define HDMI_LINK_V_BLANK_F0_0 (HDMI_ADDR_OFFSET + 0x00010110) 65 #define HDMI_LINK_V_BLANK_F0_1 (HDMI_ADDR_OFFSET + 0x00010114) 66 #define HDMI_LINK_V_BLANK_F1_0 (HDMI_ADDR_OFFSET + 0x00010118) 67 #define HDMI_LINK_V_BLANK_F1_1 (HDMI_ADDR_OFFSET + 0x0001011C) 68 #define HDMI_LINK_H_SYNC_START_0 (HDMI_ADDR_OFFSET + 0x00010120) 69 #define HDMI_LINK_H_SYNC_START_1 (HDMI_ADDR_OFFSET + 0x00010124) 70 #define HDMI_LINK_H_SYNC_END_0 (HDMI_ADDR_OFFSET + 0x00010128) 71 #define HDMI_LINK_H_SYNC_END_1 (HDMI_ADDR_OFFSET + 0x0001012C) 72 #define HDMI_LINK_V_SYNC_LINE_BEF_2_0 (HDMI_ADDR_OFFSET + 0x00010130) 73 #define HDMI_LINK_V_SYNC_LINE_BEF_2_1 (HDMI_ADDR_OFFSET + 0x00010134) 74 #define HDMI_LINK_V_SYNC_LINE_BEF_1_0 (HDMI_ADDR_OFFSET + 0x00010138) 75 #define HDMI_LINK_V_SYNC_LINE_BEF_1_1 (HDMI_ADDR_OFFSET + 0x0001013C) 76 #define HDMI_LINK_V_SYNC_LINE_AFT_2_0 (HDMI_ADDR_OFFSET + 0x00010140) 77 #define HDMI_LINK_V_SYNC_LINE_AFT_2_1 (HDMI_ADDR_OFFSET + 0x00010144) 78 #define HDMI_LINK_V_SYNC_LINE_AFT_1_0 (HDMI_ADDR_OFFSET + 0x00010148) 79 #define HDMI_LINK_V_SYNC_LINE_AFT_1_1 (HDMI_ADDR_OFFSET + 0x0001014C) 80 #define HDMI_LINK_V_SYNC_LINE_AFT_PXL_2_0 (HDMI_ADDR_OFFSET + 0x00010150) 81 #define HDMI_LINK_V_SYNC_LINE_AFT_PXL_2_1 (HDMI_ADDR_OFFSET + 0x00010154) 82 #define HDMI_LINK_V_SYNC_LINE_AFT_PXL_1_0 (HDMI_ADDR_OFFSET + 0x00010158) 83 #define HDMI_LINK_V_SYNC_LINE_AFT_PXL_1_1 (HDMI_ADDR_OFFSET + 0x0001015C) 84 #define HDMI_LINK_V_BLANK_F2_0 (HDMI_ADDR_OFFSET + 0x00010160) 85 #define HDMI_LINK_V_BLANK_F2_1 (HDMI_ADDR_OFFSET + 0x00010164) 86 #define HDMI_LINK_V_BLANK_F3_0 (HDMI_ADDR_OFFSET + 0x00010168) 87 #define HDMI_LINK_V_BLANK_F3_1 (HDMI_ADDR_OFFSET + 0x0001016C) 88 #define HDMI_LINK_V_BLANK_F4_0 (HDMI_ADDR_OFFSET + 0x00010170) 89 #define HDMI_LINK_V_BLANK_F4_1 (HDMI_ADDR_OFFSET + 0x00010174) 90 #define HDMI_LINK_V_BLANK_F5_0 (HDMI_ADDR_OFFSET + 0x00010178) 91 #define HDMI_LINK_V_BLANK_F5_1 (HDMI_ADDR_OFFSET + 0x0001017C) 92 #define HDMI_LINK_V_SYNC_LINE_AFT_3_0 (HDMI_ADDR_OFFSET + 0x00010180) 93 #define HDMI_LINK_V_SYNC_LINE_AFT_3_1 (HDMI_ADDR_OFFSET + 0x00010184) 94 #define HDMI_LINK_V_SYNC_LINE_AFT_4_0 (HDMI_ADDR_OFFSET + 0x00010188) 95 #define HDMI_LINK_V_SYNC_LINE_AFT_4_1 (HDMI_ADDR_OFFSET + 0x0001018C) 96 #define HDMI_LINK_V_SYNC_LINE_AFT_5_0 (HDMI_ADDR_OFFSET + 0x00010190) 97 #define HDMI_LINK_V_SYNC_LINE_AFT_5_1 (HDMI_ADDR_OFFSET + 0x00010194) 98 #define HDMI_LINK_V_SYNC_LINE_AFT_6_0 (HDMI_ADDR_OFFSET + 0x00010198) 99 #define HDMI_LINK_V_SYNC_LINE_AFT_6_1 (HDMI_ADDR_OFFSET + 0x0001019C) 100 #define HDMI_LINK_V_SYNC_LINE_AFT_PXL_3_0 (HDMI_ADDR_OFFSET + 0x000101A0) 101 #define HDMI_LINK_V_SYNC_LINE_AFT_PXL_3_1 (HDMI_ADDR_OFFSET + 0x000101A4) 102 #define HDMI_LINK_V_SYNC_LINE_AFT_PXL_4_0 (HDMI_ADDR_OFFSET + 0x000101A8) 103 #define HDMI_LINK_V_SYNC_LINE_AFT_PXL_4_1 (HDMI_ADDR_OFFSET + 0x000101AC) 104 #define HDMI_LINK_V_SYNC_LINE_AFT_PXL_5_0 (HDMI_ADDR_OFFSET + 0x000101B0) 105 #define HDMI_LINK_V_SYNC_LINE_AFT_PXL_5_1 (HDMI_ADDR_OFFSET + 0x000101B4) 106 #define HDMI_LINK_V_SYNC_LINE_AFT_PXL_6_0 (HDMI_ADDR_OFFSET + 0x000101B8) 107 #define HDMI_LINK_V_SYNC_LINE_AFT_PXL_6_1 (HDMI_ADDR_OFFSET + 0x000101BC) 108 #define HDMI_LINK_VACT_SPACE1_0 (HDMI_ADDR_OFFSET + 0x000101C0) 109 #define HDMI_LINK_VACT_SPACE1_1 (HDMI_ADDR_OFFSET + 0x000101C4) 110 #define HDMI_LINK_VACT_SPACE2_0 (HDMI_ADDR_OFFSET + 0x000101C8) 111 #define HDMI_LINK_VACT_SPACE2_1 (HDMI_ADDR_OFFSET + 0x000101CC) 112 #define HDMI_LINK_VACT_SPACE3_0 (HDMI_ADDR_OFFSET + 0x000101D0) 113 #define HDMI_LINK_VACT_SPACE3_1 (HDMI_ADDR_OFFSET + 0x000101D4) 114 #define HDMI_LINK_VACT_SPACE4_0 (HDMI_ADDR_OFFSET + 0x000101D8) 115 #define HDMI_LINK_VACT_SPACE4_1 (HDMI_ADDR_OFFSET + 0x000101DC) 116 #define HDMI_LINK_VACT_SPACE5_0 (HDMI_ADDR_OFFSET + 0x000101E0) 117 #define HDMI_LINK_VACT_SPACE5_1 (HDMI_ADDR_OFFSET + 0x000101E4) 118 #define HDMI_LINK_VACT_SPACE6_0 (HDMI_ADDR_OFFSET + 0x000101E8) 119 #define HDMI_LINK_VACT_SPACE6_1 (HDMI_ADDR_OFFSET + 0x000101EC) 120 121 #define HDMI_LINK_CSC_MUX (HDMI_ADDR_OFFSET + 0x000101F0) 122 #define HDMI_LINK_SYNC_GEN_MUX (HDMI_ADDR_OFFSET + 0x000101F4) 123 124 #define HDMI_LINK_GCP_CON (HDMI_ADDR_OFFSET + 0x00010200) 125 #define HDMI_LINK_GCP_BYTE1 (HDMI_ADDR_OFFSET + 0x00010210) 126 #define HDMI_LINK_GCP_BYTE2 (HDMI_ADDR_OFFSET + 0x00010214) 127 #define HDMI_LINK_GCP_BYTE3 (HDMI_ADDR_OFFSET + 0x00010218) 128 #define HDMI_LINK_ASP_CON (HDMI_ADDR_OFFSET + 0x00010300) 129 #define HDMI_LINK_ASP_SP_FLAT (HDMI_ADDR_OFFSET + 0x00010304) 130 #define HDMI_LINK_ASP_CHCFG0 (HDMI_ADDR_OFFSET + 0x00010310) 131 #define HDMI_LINK_ASP_CHCFG1 (HDMI_ADDR_OFFSET + 0x00010314) 132 #define HDMI_LINK_ASP_CHCFG2 (HDMI_ADDR_OFFSET + 0x00010318) 133 #define HDMI_LINK_ASP_CHCFG3 (HDMI_ADDR_OFFSET + 0x0001031C) 134 #define HDMI_LINK_ACR_CON (HDMI_ADDR_OFFSET + 0x00010400) 135 #define HDMI_LINK_ACR_MCTS0 (HDMI_ADDR_OFFSET + 0x00010410) 136 #define HDMI_LINK_ACR_MCTS1 (HDMI_ADDR_OFFSET + 0x00010414) 137 #define HDMI_LINK_ACR_MCTS2 (HDMI_ADDR_OFFSET + 0x00010418) 138 #define HDMI_LINK_ACR_N0 (HDMI_ADDR_OFFSET + 0x00010430) 139 #define HDMI_LINK_ACR_N1 (HDMI_ADDR_OFFSET + 0x00010434) 140 #define HDMI_LINK_ACR_N2 (HDMI_ADDR_OFFSET + 0x00010438) 141 #define HDMI_LINK_ACP_CON (HDMI_ADDR_OFFSET + 0x00010500) 142 #define HDMI_LINK_ACP_TYPE (HDMI_ADDR_OFFSET + 0x00010514) 143 #define HDMI_LINK_ACP_DATAX (HDMI_ADDR_OFFSET + 0x00010520) 144 #define HDMI_LINK_ISRC_CON (HDMI_ADDR_OFFSET + 0x00010600) 145 #define HDMI_LINK_ISRC1_HEADER1 (HDMI_ADDR_OFFSET + 0x00010614) 146 #define HDMI_LINK_ISRC1_DATAX (HDMI_ADDR_OFFSET + 0x00010620) 147 #define HDMI_LINK_ISRC2_DATAX (HDMI_ADDR_OFFSET + 0x000106A0) 148 #define HDMI_LINK_AVI_CON (HDMI_ADDR_OFFSET + 0x00010700) 149 #define HDMI_LINK_AVI_HEADER0 (HDMI_ADDR_OFFSET + 0x00010710) 150 #define HDMI_LINK_AVI_HEADER1 (HDMI_ADDR_OFFSET + 0x00010714) 151 #define HDMI_LINK_AVI_HEADER2 (HDMI_ADDR_OFFSET + 0x00010718) 152 #define HDMI_LINK_AVI_CHECK_SUM (HDMI_ADDR_OFFSET + 0x0001071C) 153 #define HDMI_LINK_AVI_BYTEX (HDMI_ADDR_OFFSET + 0x00010720) 154 #define HDMI_LINK_AVI_BYTE00 (HDMI_ADDR_OFFSET + 0x00010720) 155 #define HDMI_LINK_AVI_BYTE01 (HDMI_ADDR_OFFSET + 0x00010724) 156 #define HDMI_LINK_AVI_BYTE02 (HDMI_ADDR_OFFSET + 0x00010728) 157 #define HDMI_LINK_AVI_BYTE03 (HDMI_ADDR_OFFSET + 0x0001073C) 158 #define HDMI_LINK_AVI_BYTE04 (HDMI_ADDR_OFFSET + 0x00010730) 159 #define HDMI_LINK_AVI_BYTE05 (HDMI_ADDR_OFFSET + 0x00010734) 160 #define HDMI_LINK_AVI_BYTE06 (HDMI_ADDR_OFFSET + 0x00010738) 161 #define HDMI_LINK_AVI_BYTE07 (HDMI_ADDR_OFFSET + 0x0001074C) 162 #define HDMI_LINK_AVI_BYTE08 (HDMI_ADDR_OFFSET + 0x00010740) 163 #define HDMI_LINK_AVI_BYTE09 (HDMI_ADDR_OFFSET + 0x00010744) 164 #define HDMI_LINK_AVI_BYTE10 (HDMI_ADDR_OFFSET + 0x00010748) 165 #define HDMI_LINK_AVI_BYTE11 (HDMI_ADDR_OFFSET + 0x0001074C) 166 #define HDMI_LINK_AVI_BYTE12 (HDMI_ADDR_OFFSET + 0x00010750) 167 #define HDMI_LINK_AUI_CON (HDMI_ADDR_OFFSET + 0x00010800) 168 #define HDMI_LINK_AUI_HEADER0 (HDMI_ADDR_OFFSET + 0x00010810) 169 #define HDMI_LINK_AUI_HEADER1 (HDMI_ADDR_OFFSET + 0x00010814) 170 #define HDMI_LINK_AUI_HEADER2 (HDMI_ADDR_OFFSET + 0x00010818) 171 #define HDMI_LINK_AUI_CHECK_SUM (HDMI_ADDR_OFFSET + 0x0001081C) 172 #define HDMI_LINK_AUI_BYTEX (HDMI_ADDR_OFFSET + 0x00010820) 173 #define HDMI_LINK_MPG_CON (HDMI_ADDR_OFFSET + 0x00010900) 174 #define HDMI_LINK_MPG_CHECK_SUM (HDMI_ADDR_OFFSET + 0x0001091C) 175 #define HDMI_LINK_MPG_DATAX (HDMI_ADDR_OFFSET + 0x00010920) 176 #define HDMI_LINK_SPD_CON (HDMI_ADDR_OFFSET + 0x00010A00) 177 #define HDMI_LINK_SPD_HEADER0 (HDMI_ADDR_OFFSET + 0x00010A10) 178 #define HDMI_LINK_SPD_HEADER1 (HDMI_ADDR_OFFSET + 0x00010A14) 179 #define HDMI_LINK_SPD_HEADER2 (HDMI_ADDR_OFFSET + 0x00010A18) 180 #define HDMI_LINK_SPD_DATAX (HDMI_ADDR_OFFSET + 0x00010A20) 181 #define HDMI_LINK_GAMUT_CON (HDMI_ADDR_OFFSET + 0x00010B00) 182 #define HDMI_LINK_GAMUT_HEADER0 (HDMI_ADDR_OFFSET + 0x00010B10) 183 #define HDMI_LINK_GAMUT_HEADER1 (HDMI_ADDR_OFFSET + 0x00010B14) 184 #define HDMI_LINK_GAMUT_HEADER2 (HDMI_ADDR_OFFSET + 0x00010B18) 185 #define HDMI_LINK_GAMUT_METADATAX (HDMI_ADDR_OFFSET + 0x00010B20) 186 #define HDMI_LINK_VSI_CON (HDMI_ADDR_OFFSET + 0x00010C00) 187 #define HDMI_LINK_VSI_HEADER0 (HDMI_ADDR_OFFSET + 0x00010C10) 188 #define HDMI_LINK_VSI_HEADER1 (HDMI_ADDR_OFFSET + 0x00010C14) 189 #define HDMI_LINK_VSI_HEADER2 (HDMI_ADDR_OFFSET + 0x00010C18) 190 #define HDMI_LINK_VSI_DATAX (HDMI_ADDR_OFFSET + 0x00010C20) 191 #define HDMI_LINK_VSI_DATA00 (HDMI_ADDR_OFFSET + 0x00010C20) 192 #define HDMI_LINK_VSI_DATA01 (HDMI_ADDR_OFFSET + 0x00010C24) 193 #define HDMI_LINK_VSI_DATA02 (HDMI_ADDR_OFFSET + 0x00010C28) 194 #define HDMI_LINK_VSI_DATA03 (HDMI_ADDR_OFFSET + 0x00010C2C) 195 #define HDMI_LINK_VSI_DATA04 (HDMI_ADDR_OFFSET + 0x00010C30) 196 #define HDMI_LINK_VSI_DATA05 (HDMI_ADDR_OFFSET + 0x00010C34) 197 #define HDMI_LINK_VSI_DATA06 (HDMI_ADDR_OFFSET + 0x00010C38) 198 #define HDMI_LINK_VSI_DATA07 (HDMI_ADDR_OFFSET + 0x00010C3C) 199 #define HDMI_LINK_VSI_DATA08 (HDMI_ADDR_OFFSET + 0x00010C40) 200 #define HDMI_LINK_VSI_DATA09 (HDMI_ADDR_OFFSET + 0x00010C44) 201 #define HDMI_LINK_VSI_DATA10 (HDMI_ADDR_OFFSET + 0x00010C48) 202 #define HDMI_LINK_VSI_DATA11 (HDMI_ADDR_OFFSET + 0x00010c4c) 203 #define HDMI_LINK_VSI_DATA12 (HDMI_ADDR_OFFSET + 0x00010C50) 204 #define HDMI_LINK_VSI_DATA13 (HDMI_ADDR_OFFSET + 0x00010C54) 205 #define HDMI_LINK_VSI_DATA14 (HDMI_ADDR_OFFSET + 0x00010C58) 206 #define HDMI_LINK_VSI_DATA15 (HDMI_ADDR_OFFSET + 0x00010C5c) 207 #define HDMI_LINK_VSI_DATA16 (HDMI_ADDR_OFFSET + 0x00010C60) 208 #define HDMI_LINK_VSI_DATA17 (HDMI_ADDR_OFFSET + 0x00010C64) 209 #define HDMI_LINK_VSI_DATA18 (HDMI_ADDR_OFFSET + 0x00010C68) 210 #define HDMI_LINK_VSI_DATA19 (HDMI_ADDR_OFFSET + 0x00010C6c) 211 #define HDMI_LINK_VSI_DATA20 (HDMI_ADDR_OFFSET + 0x00010C70) 212 #define HDMI_LINK_VSI_DATA21 (HDMI_ADDR_OFFSET + 0x00010c74) 213 #define HDMI_LINK_VSI_DATA22 (HDMI_ADDR_OFFSET + 0x00010C78) 214 #define HDMI_LINK_VSI_DATA23 (HDMI_ADDR_OFFSET + 0x00010C7c) 215 #define HDMI_LINK_VSI_DATA24 (HDMI_ADDR_OFFSET + 0x00010C80) 216 #define HDMI_LINK_VSI_DATA25 (HDMI_ADDR_OFFSET + 0x00010C84) 217 #define HDMI_LINK_VSI_DATA26 (HDMI_ADDR_OFFSET + 0x00010C88) 218 #define HDMI_LINK_VSI_DATA27 (HDMI_ADDR_OFFSET + 0x00010C8C) 219 #define HDMI_LINK_DC_CONTROL (HDMI_ADDR_OFFSET + 0x00010D00) 220 #define HDMI_LINK_VIDEO_PATTERN_GEN (HDMI_ADDR_OFFSET + 0x00010D04) 221 #define HDMI_LINK_AN_SEED_SEL (HDMI_ADDR_OFFSET + 0x00010E48) 222 #define HDMI_LINK_AN_SEED_0 (HDMI_ADDR_OFFSET + 0x00010E58) 223 #define HDMI_LINK_AN_SEED_1 (HDMI_ADDR_OFFSET + 0x00010E5C) 224 #define HDMI_LINK_AN_SEED_2 (HDMI_ADDR_OFFSET + 0x00010E60) 225 #define HDMI_LINK_AN_SEED_3 (HDMI_ADDR_OFFSET + 0x00010E64) 226 #define HDMI_LINK_HDCP_SHA1_X (HDMI_ADDR_OFFSET + 0x00017000) 227 228 #define HDMI_LINK_HDCP_SHA1_0_0 (HDMI_LINK_HDCP_SHA1_x + 0x00) 229 #define HDMI_LINK_HDCP_SHA1_0_1 (HDMI_LINK_HDCP_SHA1_0_0 + 0x04) 230 #define HDMI_LINK_HDCP_SHA1_0_2 (HDMI_LINK_HDCP_SHA1_0_0 + 0x08) 231 #define HDMI_LINK_HDCP_SHA1_0_3 (HDMI_LINK_HDCP_SHA1_0_0 + 0x0C) 232 #define HDMI_LINK_HDCP_SHA1_1_0 (HDMI_LINK_HDCP_SHA1_x + 0x10) 233 #define HDMI_LINK_HDCP_SHA1_1_1 (HDMI_LINK_HDCP_SHA1_1_0 + 0x04) 234 #define HDMI_LINK_HDCP_SHA1_1_2 (HDMI_LINK_HDCP_SHA1_1_0 + 0x08) 235 #define HDMI_LINK_HDCP_SHA1_1_3 (HDMI_LINK_HDCP_SHA1_1_0 + 0x0C) 236 #define HDMI_LINK_HDCP_SHA1_2_0 (HDMI_LINK_HDCP_SHA1_x + 0x20) 237 #define HDMI_LINK_HDCP_SHA1_2_1 (HDMI_LINK_HDCP_SHA1_2_0 + 0x04) 238 #define HDMI_LINK_HDCP_SHA1_2_2 (HDMI_LINK_HDCP_SHA1_2_0 + 0x08) 239 #define HDMI_LINK_HDCP_SHA1_2_3 (HDMI_LINK_HDCP_SHA1_2_0 + 0x0C) 240 #define HDMI_LINK_HDCP_SHA1_3_0 (HDMI_LINK_HDCP_SHA1_x + 0x30) 241 #define HDMI_LINK_HDCP_SHA1_3_1 (HDMI_LINK_HDCP_SHA1_3_0 + 0x04) 242 #define HDMI_LINK_HDCP_SHA1_3_2 (HDMI_LINK_HDCP_SHA1_3_0 + 0x08) 243 #define HDMI_LINK_HDCP_SHA1_3_3 (HDMI_LINK_HDCP_SHA1_3_0 + 0x0C) 244 #define HDMI_LINK_HDCP_SHA1_4_0 (HDMI_LINK_HDCP_SHA1_x + 0x40) 245 #define HDMI_LINK_HDCP_SHA1_4_1 (HDMI_LINK_HDCP_SHA1_4_0 + 0x04) 246 #define HDMI_LINK_HDCP_SHA1_4_2 (HDMI_LINK_HDCP_SHA1_4_0 + 0x08) 247 #define HDMI_LINK_HDCP_SHA1_4_3 (HDMI_LINK_HDCP_SHA1_4_0 + 0x0C) 248 249 #define HDMI_LINK_HDCP_KSV_LIST_X (HDMI_ADDR_OFFSET + 0x00017050) 250 251 #define HDMI_LINK_HDCP_KSV_0_0 (HDMI_LINK_HDCP_KSV_LIST_X + 0x00) 252 #define HDMI_LINK_HDCP_KSV_0_1 (HDMI_LINK_HDCP_KSV_LIST_X + 0x04) 253 #define HDMI_LINK_HDCP_KSV_0_2 (HDMI_LINK_HDCP_KSV_LIST_X + 0x08) 254 #define HDMI_LINK_HDCP_KSV_0_3 (HDMI_LINK_HDCP_KSV_LIST_X + 0x0C) 255 #define HDMI_LINK_HDCP_KSV_1_0 (HDMI_LINK_HDCP_KSV_LIST_X + 0x10) 256 #define HDMI_LINK_HDCP_KSV_1_1 (HDMI_LINK_HDCP_KSV_LIST_X + 0x14) 257 258 #define HDMI_LINK_HDCP_KSV_LIST_0_0 (HDMI_LINK_HDCP_KSV_LIST_X + 0x00) 259 #define HDMI_LINK_HDCP_KSV_LIST_0_1 (HDMI_LINK_HDCP_KSV_LIST_X + 0x04) 260 #define HDMI_LINK_HDCP_KSV_LIST_0_2 (HDMI_LINK_HDCP_KSV_LIST_X + 0x08) 261 #define HDMI_LINK_HDCP_KSV_LIST_0_3 (HDMI_LINK_HDCP_KSV_LIST_X + 0x0C) 262 #define HDMI_LINK_HDCP_KSV_LIST_1_0 (HDMI_LINK_HDCP_KSV_LIST_X + 0x10) 263 #define HDMI_LINK_HDCP_KSV_LIST_1_1 (HDMI_LINK_HDCP_KSV_LIST_X + 0x14) 264 265 #define HDMI_LINK_HDCP_KSV_LIST_CON (HDMI_ADDR_OFFSET + 0x00017064) 266 #define HDMI_LINK_HDCP_SHA_RESULT (HDMI_ADDR_OFFSET + 0x00017070) 267 #define HDMI_LINK_HDCP_CTRL1 (HDMI_ADDR_OFFSET + 0x00017080) 268 #define HDMI_LINK_HDCP_CTRL2 (HDMI_ADDR_OFFSET + 0x00017084) 269 #define HDMI_LINK_HDCP_CHECK_RESULT (HDMI_ADDR_OFFSET + 0x00017090) 270 #define HDMI_LINK_HDCP_BKSV_X (HDMI_ADDR_OFFSET + 0x000170A0) 271 272 #define HDMI_LINK_HDCP_BKSV0_0 (HDMI_ADDR_OFFSET + 0x000170A0) 273 #define HDMI_LINK_HDCP_BKSV0_1 (HDMI_ADDR_OFFSET + 0x000170A4) 274 #define HDMI_LINK_HDCP_BKSV0_2 (HDMI_ADDR_OFFSET + 0x000170A8) 275 #define HDMI_LINK_HDCP_BKSV0_3 (HDMI_ADDR_OFFSET + 0x000170AC) 276 #define HDMI_LINK_HDCP_BKSV1 (HDMI_ADDR_OFFSET + 0x000170B0) 277 278 #define HDMI_LINK_HDCP_AKSV_X (HDMI_ADDR_OFFSET + 0x000170C0) 279 #define HDMI_LINK_HDCP_AN_X (HDMI_ADDR_OFFSET + 0x000170E0) 280 #define HDMI_LINK_HDCP_BCAPS (HDMI_ADDR_OFFSET + 0x00017100) 281 #define HDMI_LINK_HDCP_BSTATUS_0 (HDMI_ADDR_OFFSET + 0x00017110) 282 #define HDMI_LINK_HDCP_BSTATUS_1 (HDMI_ADDR_OFFSET + 0x00017114) 283 #define HDMI_LINK_HDCP_RI_0 (HDMI_ADDR_OFFSET + 0x00017140) 284 #define HDMI_LINK_HDCP_RI_1 (HDMI_ADDR_OFFSET + 0x00017144) 285 286 #define HDMI_LINK_HDCP_OFFSET_TX_0 (HDMI_ADDR_OFFSET + 0x00017160) 287 #define HDMI_LINK_HDCP_OFFSET_TX_1 (HDMI_ADDR_OFFSET + 0x00017164) 288 #define HDMI_LINK_HDCP_OFFSET_TX_2 (HDMI_ADDR_OFFSET + 0x00017168) 289 #define HDMI_LINK_HDCP_OFFSET_TX_3 (HDMI_ADDR_OFFSET + 0x0001716C) 290 #define HDMI_LINK_HDCP_CYCLE_AA (HDMI_ADDR_OFFSET + 0x00017170) 291 292 #define HDMI_LINK_HDCP_I2C_INT (HDMI_ADDR_OFFSET + 0x00017180) 293 #define HDMI_LINK_HDCP_AN_INT (HDMI_ADDR_OFFSET + 0x00017190) 294 #define HDMI_LINK_HDCP_WATCHDOG_INT (HDMI_ADDR_OFFSET + 0x000171A0) 295 #define HDMI_LINK_HDCP_RI_INT (HDMI_ADDR_OFFSET + 0x000171B0) 296 #define HDMI_LINK_HDCP_RI_COMPARE_0 (HDMI_ADDR_OFFSET + 0x000171D0) 297 #define HDMI_LINK_HDCP_RI_COMPARE_1 (HDMI_ADDR_OFFSET + 0x000171D4) 298 299 #define HDMI_LINK_HDCP_RI_INT (HDMI_ADDR_OFFSET + 0x000171B0) 300 #define HDMI_LINK_HDCP_RI_COMPARE_0 (HDMI_ADDR_OFFSET + 0x000171D0) 301 #define HDMI_LINK_HDCP_RI_COMPARE_1 (HDMI_ADDR_OFFSET + 0x000171D4) 302 303 #define HDMI_LINK_HDCP_FRAME_COUNT (HDMI_ADDR_OFFSET + 0x000171E0) 304 #define HDMI_LINK_RGB_ROUND_EN (HDMI_ADDR_OFFSET + 0x0001D500) 305 #define HDMI_LINK_VACT_SPACE_R_0 (HDMI_ADDR_OFFSET + 0x0001D504) 306 #define HDMI_LINK_VACT_SPACE_R_1 (HDMI_ADDR_OFFSET + 0x0001D508) 307 #define HDMI_LINK_VACT_SPACE_G_0 (HDMI_ADDR_OFFSET + 0x0001D50C) 308 #define HDMI_LINK_VACT_SPACE_G_1 (HDMI_ADDR_OFFSET + 0x0001D510) 309 #define HDMI_LINK_VACT_SPACE_B_0 (HDMI_ADDR_OFFSET + 0x0001D514) 310 #define HDMI_LINK_VACT_SPACE_B_1 (HDMI_ADDR_OFFSET + 0x0001D518) 311 #define HDMI_LINK_BLUE_SCREEN_R_0 (HDMI_ADDR_OFFSET + 0x0001D520) 312 #define HDMI_LINK_BLUE_SCREEN_R_1 (HDMI_ADDR_OFFSET + 0x0001D524) 313 #define HDMI_LINK_BLUE_SCREEN_G_0 (HDMI_ADDR_OFFSET + 0x0001D528) 314 #define HDMI_LINK_BLUE_SCREEN_G_1 (HDMI_ADDR_OFFSET + 0x0001D52C) 315 #define HDMI_LINK_BLUE_SCREEN_B_0 (HDMI_ADDR_OFFSET + 0x0001D530) 316 #define HDMI_LINK_BLUE_SCREEN_B_1 (HDMI_ADDR_OFFSET + 0x0001D534) 317 #define HDMI_LINK_AES_START (HDMI_ADDR_OFFSET + 0x00020000) 318 #define HDMI_LINK_AES_DATA_SIZE_L (HDMI_ADDR_OFFSET + 0x00020020) 319 #define HDMI_LINK_AES_DATA_SIZE_H (HDMI_ADDR_OFFSET + 0x00020024) 320 #define HDMI_LINK_AES_DATA (HDMI_ADDR_OFFSET + 0x00020040) 321 #define HDMI_LINK_SPDIFIN_CLK_CTRL (HDMI_ADDR_OFFSET + 0x00030000) 322 #define HDMI_LINK_SPDIFIN_OP_CTRL (HDMI_ADDR_OFFSET + 0x00030004) 323 #define HDMI_LINK_SPDIFIN_IRQ_MASK (HDMI_ADDR_OFFSET + 0x00030008) 324 #define HDMI_LINK_SPDIFIN_IRQ_STATUS (HDMI_ADDR_OFFSET + 0x0003000C) 325 #define HDMI_LINK_SPDIFIN_CONFIG_1 (HDMI_ADDR_OFFSET + 0x00030010) 326 #define HDMI_LINK_SPDIFIN_CONFIG_2 (HDMI_ADDR_OFFSET + 0x00030014) 327 #define HDMI_LINK_SPDIFIN_USER_VALUE_1 (HDMI_ADDR_OFFSET + 0x00030020) 328 #define HDMI_LINK_SPDIFIN_USER_VALUE_2 (HDMI_ADDR_OFFSET + 0x00030024) 329 #define HDMI_LINK_SPDIFIN_USER_VALUE_3 (HDMI_ADDR_OFFSET + 0x00030028) 330 #define HDMI_LINK_SPDIFIN_USER_VALUE_4 (HDMI_ADDR_OFFSET + 0x0003002C) 331 #define HDMI_LINK_SPDIFIN_CH_STATUS_0_1 (HDMI_ADDR_OFFSET + 0x00030030) 332 #define HDMI_LINK_SPDIFIN_CH_STATUS_0_2 (HDMI_ADDR_OFFSET + 0x00030034) 333 #define HDMI_LINK_SPDIFIN_CH_STATUS_0_3 (HDMI_ADDR_OFFSET + 0x00030038) 334 #define HDMI_LINK_SPDIFIN_CH_STATUS_0_4 (HDMI_ADDR_OFFSET + 0x0003003C) 335 #define HDMI_LINK_SPDIFIN_CH_STATUS_1 (HDMI_ADDR_OFFSET + 0x00030040) 336 #define HDMI_LINK_SPDIFIN_FRAME_PERIOD_1 (HDMI_ADDR_OFFSET + 0x00030048) 337 #define HDMI_LINK_SPDIFIN_FRAME_PERIOD_2 (HDMI_ADDR_OFFSET + 0x0003004C) 338 #define HDMI_LINK_SPDIFIN_PC_INFO_1 (HDMI_ADDR_OFFSET + 0x00030050) 339 #define HDMI_LINK_SPDIFIN_PC_INFO_2 (HDMI_ADDR_OFFSET + 0x00030054) 340 #define HDMI_LINK_SPDIFIN_PD_INFO_1 (HDMI_ADDR_OFFSET + 0x00030058) 341 #define HDMI_LINK_SPDIFIN_PD_INFO_2 (HDMI_ADDR_OFFSET + 0x0003005C) 342 #define HDMI_LINK_SPDIFIN_DATA_BUF_0_1 (HDMI_ADDR_OFFSET + 0x00030060) 343 #define HDMI_LINK_SPDIFIN_DATA_BUF_0_2 (HDMI_ADDR_OFFSET + 0x00030064) 344 #define HDMI_LINK_SPDIFIN_DATA_BUF_0_3 (HDMI_ADDR_OFFSET + 0x00030068) 345 #define HDMI_LINK_SPDIFIN_USER_BUF_0 (HDMI_ADDR_OFFSET + 0x0003006C) 346 #define HDMI_LINK_SPDIFIN_DATA_BUF_1_1 (HDMI_ADDR_OFFSET + 0x00030070) 347 #define HDMI_LINK_SPDIFIN_DATA_BUF_1_2 (HDMI_ADDR_OFFSET + 0x00030074) 348 #define HDMI_LINK_SPDIFIN_DATA_BUF_1_3 (HDMI_ADDR_OFFSET + 0x00030078) 349 #define HDMI_LINK_SPDIFIN_USER_BUF_1 (HDMI_ADDR_OFFSET + 0x0003007C) 350 #define HDMI_LINK_I2S_CLK_CON (HDMI_ADDR_OFFSET + 0x00040000) 351 #define HDMI_LINK_I2S_CON_1 (HDMI_ADDR_OFFSET + 0x00040004) 352 #define HDMI_LINK_I2S_CON_2 (HDMI_ADDR_OFFSET + 0x00040008) 353 #define HDMI_LINK_I2S_PIN_SEL_0 (HDMI_ADDR_OFFSET + 0x0004000C) 354 #define HDMI_LINK_I2S_PIN_SEL_1 (HDMI_ADDR_OFFSET + 0x00040010) 355 #define HDMI_LINK_I2S_PIN_SEL_2 (HDMI_ADDR_OFFSET + 0x00040014) 356 #define HDMI_LINK_I2S_PIN_SEL_3 (HDMI_ADDR_OFFSET + 0x00040018) 357 #define HDMI_LINK_I2S_DSD_CON (HDMI_ADDR_OFFSET + 0x0004001C) 358 #define HDMI_LINK_I2S_MUX_CON (HDMI_ADDR_OFFSET + 0x00040020) 359 #define HDMI_LINK_I2S_CH_ST_CON (HDMI_ADDR_OFFSET + 0x00040024) 360 #define HDMI_LINK_I2S_CH_ST_0 (HDMI_ADDR_OFFSET + 0x00040028) 361 #define HDMI_LINK_I2S_CH_ST_1 (HDMI_ADDR_OFFSET + 0x0004002C) 362 #define HDMI_LINK_I2S_CH_ST_2 (HDMI_ADDR_OFFSET + 0x00040030) 363 #define HDMI_LINK_I2S_CH_ST_3 (HDMI_ADDR_OFFSET + 0x00040034) 364 #define HDMI_LINK_I2S_CH_ST_4 (HDMI_ADDR_OFFSET + 0x00040038) 365 #define HDMI_LINK_I2S_CH_ST_SH_0 (HDMI_ADDR_OFFSET + 0x0004003C) 366 #define HDMI_LINK_I2S_CH_ST_SH_1 (HDMI_ADDR_OFFSET + 0x00040040) 367 #define HDMI_LINK_I2S_CH_ST_SH_2 (HDMI_ADDR_OFFSET + 0x00040044) 368 #define HDMI_LINK_I2S_CH_ST_SH_3 (HDMI_ADDR_OFFSET + 0x00040048) 369 #define HDMI_LINK_I2S_CH_ST_SH_4 (HDMI_ADDR_OFFSET + 0x0004004C) 370 #define HDMI_LINK_I2S_VD_DATA (HDMI_ADDR_OFFSET + 0x00040050) 371 #define HDMI_LINK_I2S_MUX_CH (HDMI_ADDR_OFFSET + 0x00040054) 372 #define HDMI_LINK_I2S_MUX_CUV (HDMI_ADDR_OFFSET + 0x00040058) 373 #define HDMI_LINK_I2S_CH0_L_0 (HDMI_ADDR_OFFSET + 0x00040064) 374 #define HDMI_LINK_I2S_CH0_L_1 (HDMI_ADDR_OFFSET + 0x00040068) 375 #define HDMI_LINK_I2S_CH0_L_2 (HDMI_ADDR_OFFSET + 0x0004006C) 376 #define HDMI_LINK_I2S_CH0_R_0 (HDMI_ADDR_OFFSET + 0x00040074) 377 #define HDMI_LINK_I2S_CH0_R_1 (HDMI_ADDR_OFFSET + 0x00040078) 378 #define HDMI_LINK_I2S_CH0_R_2 (HDMI_ADDR_OFFSET + 0x0004007C) 379 #define HDMI_LINK_I2S_CH0_R_3 (HDMI_ADDR_OFFSET + 0x00040080) 380 #define HDMI_LINK_I2S_CH1_L_0 (HDMI_ADDR_OFFSET + 0x00040084) 381 #define HDMI_LINK_I2S_CH1_L_1 (HDMI_ADDR_OFFSET + 0x00040088) 382 #define HDMI_LINK_I2S_CH1_L_2 (HDMI_ADDR_OFFSET + 0x0004008C) 383 #define HDMI_LINK_I2S_CH1_L_3 (HDMI_ADDR_OFFSET + 0x00040090) 384 #define HDMI_LINK_I2S_CH1_R_0 (HDMI_ADDR_OFFSET + 0x00040094) 385 #define HDMI_LINK_I2S_CH1_R_1 (HDMI_ADDR_OFFSET + 0x00040098) 386 #define HDMI_LINK_I2S_CH1_R_2 (HDMI_ADDR_OFFSET + 0x0004009C) 387 #define HDMI_LINK_I2S_CH1_R_3 (HDMI_ADDR_OFFSET + 0x000400A0) 388 #define HDMI_LINK_I2S_CH2_L_0 (HDMI_ADDR_OFFSET + 0x000400A4) 389 #define HDMI_LINK_I2S_CH2_L_1 (HDMI_ADDR_OFFSET + 0x000400A8) 390 #define HDMI_LINK_I2S_CH2_L_2 (HDMI_ADDR_OFFSET + 0x000400AC) 391 #define HDMI_LINK_I2S_CH2_L_3 (HDMI_ADDR_OFFSET + 0x000400B0) 392 #define HDMI_LINK_I2S_CH2_R_0 (HDMI_ADDR_OFFSET + 0x000400B4) 393 #define HDMI_LINK_I2S_CH2_R_1 (HDMI_ADDR_OFFSET + 0x000400B8) 394 #define HDMI_LINK_I2S_CH2_R_2 (HDMI_ADDR_OFFSET + 0x000400BC) 395 #define HDMI_LINK_I2S_CH2_R_3 (HDMI_ADDR_OFFSET + 0x000400C0) 396 #define HDMI_LINK_I2S_CH3_L_0 (HDMI_ADDR_OFFSET + 0x000400C4) 397 #define HDMI_LINK_I2S_CH3_L_1 (HDMI_ADDR_OFFSET + 0x000400C8) 398 #define HDMI_LINK_I2S_CH3_L_2 (HDMI_ADDR_OFFSET + 0x000400CC) 399 #define HDMI_LINK_I2S_CH3_R_0 (HDMI_ADDR_OFFSET + 0x000400D0) 400 #define HDMI_LINK_I2S_CH3_R_1 (HDMI_ADDR_OFFSET + 0x000400D4) 401 #define HDMI_LINK_I2S_CH3_R_2 (HDMI_ADDR_OFFSET + 0x000400D8) 402 #define HDMI_LINK_I2S_CUV_L_R (HDMI_ADDR_OFFSET + 0x000400DC) 403 404 #define HDMI_CEC_TX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000000) 405 #define HDMI_CEC_TX_STATUS_1 (OTHER_ADDR_OFFSET + 0x00000004) 406 #define HDMI_CEC_RX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000008) 407 #define HDMI_CEC_RX_STATUS_1 (OTHER_ADDR_OFFSET + 0x0000000C) 408 #define HDMI_CEC_INTR_MASK (OTHER_ADDR_OFFSET + 0x00000010) 409 #define HDMI_CEC_INTR_CLEAR (OTHER_ADDR_OFFSET + 0x00000014) 410 #define HDMI_CEC_LOGIC_ADDR (OTHER_ADDR_OFFSET + 0x00000020) 411 #define HDMI_CEC_DIVISOR_0 (OTHER_ADDR_OFFSET + 0x00000030) 412 #define HDMI_CEC_DIVISOR_1 (OTHER_ADDR_OFFSET + 0x00000034) 413 #define HDMI_CEC_DIVISOR_2 (OTHER_ADDR_OFFSET + 0x00000038) 414 #define HDMI_CEC_DIVISOR_3 (OTHER_ADDR_OFFSET + 0x0000003C) 415 #define HDMI_CEC_TX_CTRL (OTHER_ADDR_OFFSET + 0x00000040) 416 #define HDMI_CEC_TX_BYTE_NUM (OTHER_ADDR_OFFSET + 0x00000044) 417 #define HDMI_CEC_TX_STATUS_2 (OTHER_ADDR_OFFSET + 0x00000060) 418 #define HDMI_CEC_TX_STATUS_3 (OTHER_ADDR_OFFSET + 0x00000064) 419 #define HDMI_CEC_TX_BUFFER_x (OTHER_ADDR_OFFSET + 0x00000080) 420 #define HDMI_CEC_TX_BUFFER00 (OTHER_ADDR_OFFSET + 0x00000080) 421 #define HDMI_CEC_RX_CTRL (OTHER_ADDR_OFFSET + 0x000000C0) 422 #define HDMI_CEC_RX_STATUS_2 (OTHER_ADDR_OFFSET + 0x000000E0) 423 #define HDMI_CEC_RX_STATUS_3 (OTHER_ADDR_OFFSET + 0x000000E4) 424 #define HDMI_CEC_RX_BUFFER_x (OTHER_ADDR_OFFSET + 0x00000100) 425 #define HDMI_CEC_FILTER_CTRL (OTHER_ADDR_OFFSET + 0x00000180) 426 #define HDMI_CEC_FILTER_TH (OTHER_ADDR_OFFSET + 0x00000184) 427 428 #ifdef CONFIG_MACH_S5P6818 429 #define HDMI_PHY_OFFSET \ 430 (PHY_BASEADDR_HDMI_PHY_MODULE - PHY_BASEADDR_HDMI_MODULE) 431 #else 432 #define HDMI_PHY_OFFSET 0x400 433 #endif 434 435 #define HDMI_PHY_REG00 (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x00000000) 436 #define HDMI_PHY_REG04 (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x00000004) 437 #define HDMI_PHY_REG08 (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x00000008) 438 #define HDMI_PHY_REG0C (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x0000000C) 439 #define HDMI_PHY_REG10 (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x00000010) 440 #define HDMI_PHY_REG14 (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x00000014) 441 #define HDMI_PHY_REG18 (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x00000018) 442 #define HDMI_PHY_REG1C (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x0000001C) 443 #define HDMI_PHY_REG20 (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x00000020) 444 #define HDMI_PHY_REG24 (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x00000024) 445 #define HDMI_PHY_REG28 (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x00000028) 446 #define HDMI_PHY_REG2C (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x0000002C) 447 #define HDMI_PHY_REG30 (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x00000030) 448 #define HDMI_PHY_REG34 (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x00000034) 449 #define HDMI_PHY_REG38 (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x00000038) 450 #define HDMI_PHY_REG3C (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x0000003C) 451 #define HDMI_PHY_REG40 (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x00000040) 452 #define HDMI_PHY_REG44 (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x00000044) 453 #define HDMI_PHY_REG48 (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x00000048) 454 #define HDMI_PHY_REG4C (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x0000004C) 455 #define HDMI_PHY_REG50 (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x00000050) 456 #define HDMI_PHY_REG54 (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x00000054) 457 #define HDMI_PHY_REG58 (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x00000058) 458 #define HDMI_PHY_REG5C (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x0000005C) 459 #define HDMI_PHY_REG60 (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x00000060) 460 #define HDMI_PHY_REG64 (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x00000064) 461 #define HDMI_PHY_REG68 (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x00000068) 462 #define HDMI_PHY_REG6C (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x0000006C) 463 #define HDMI_PHY_REG70 (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x00000070) 464 #define HDMI_PHY_REG74 (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x00000074) 465 #define HDMI_PHY_REG78 (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x00000078) 466 #define HDMI_PHY_REG7C (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x0000007C) 467 #define HDMI_PHY_REG80 (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x00000080) 468 #define HDMI_PHY_REG84 (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x00000084) 469 #define HDMI_PHY_REG88 (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x00000088) 470 #define HDMI_PHY_REG8C (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x0000008C) 471 #define HDMI_PHY_REG90 (OTHER_ADDR_OFFSET + HDMI_PHY_OFFSET + 0x00000090) 472 473 enum hdmi_reset { 474 i_nRST = 0, 475 i_nRST_VIDEO = 1, 476 i_nRST_SPDIF = 2, 477 i_nRST_TMDS = 3, 478 i_nRST_PHY = 4, 479 }; 480 481 u32 nx_hdmi_get_reg(u32 module_index, u32 offset); 482 void nx_hdmi_set_reg(u32 module_index, u32 offset, u32 regvalue); 483 484 void nx_hdmi_set_base_address(u32 module_index, void *base_address); 485 void *nx_hdmi_get_base_address(u32 module_index); 486 u32 nx_hdmi_get_physical_address(u32 module_index); 487 488 #endif 489