1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_pmc.h]
4  *
5  * Copyright (C) 2005 Ivan Kokshaysky
6  * Copyright (C) SAN People
7  * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
8  *
9  * Power Management Controller (PMC) - System peripherals registers.
10  * Based on AT91RM9200 datasheet revision E.
11  */
12 
13 #ifndef AT91_PMC_H
14 #define AT91_PMC_H
15 
16 #ifdef __ASSEMBLY__
17 
18 #define	AT91_ASM_PMC_MOR	(ATMEL_BASE_PMC + 0x20)
19 #define	AT91_ASM_PMC_PLLAR	(ATMEL_BASE_PMC + 0x28)
20 #define	AT91_ASM_PMC_PLLBR	(ATMEL_BASE_PMC + 0x2c)
21 #define AT91_ASM_PMC_MCKR	(ATMEL_BASE_PMC + 0x30)
22 #define AT91_ASM_PMC_SR		(ATMEL_BASE_PMC + 0x68)
23 
24 #else
25 
26 #include <asm/types.h>
27 #include <linux/bitops.h>
28 
29 typedef struct at91_pmc {
30 	u32	scer;		/* 0x00 System Clock Enable Register */
31 	u32	scdr;		/* 0x04 System Clock Disable Register */
32 	u32	scsr;		/* 0x08 System Clock Status Register */
33 	u32	reserved0;
34 	u32	pcer;		/* 0x10 Peripheral Clock Enable Register */
35 	u32	pcdr;		/* 0x14 Peripheral Clock Disable Register */
36 	u32	pcsr;		/* 0x18 Peripheral Clock Status Register */
37 	u32	uckr;		/* 0x1C UTMI Clock Register */
38 	u32	mor;		/* 0x20 Main Oscilator Register */
39 	u32	mcfr;		/* 0x24 Main Clock Frequency Register */
40 	u32	pllar;		/* 0x28 PLL A Register */
41 	u32	pllbr;		/* 0x2C PLL B Register */
42 	u32	mckr;		/* 0x30 Master Clock Register */
43 	u32	reserved1;
44 	u32	usb;		/* 0x38 USB Clock Register */
45 	u32	reserved2;
46 	u32	pck[4];		/* 0x40 Programmable Clock Register 0 - 3 */
47 	u32	reserved3[4];
48 	u32	ier;		/* 0x60 Interrupt Enable Register */
49 	u32	idr;		/* 0x64 Interrupt Disable Register */
50 	u32	sr;		/* 0x68 Status Register */
51 	u32	imr;		/* 0x6C Interrupt Mask Register */
52 	u32	reserved4[4];
53 	u32	pllicpr;	/* 0x80 Change Pump Current Register (SAM9) */
54 	u32	reserved5[24];
55 	u32	wpmr;		/* 0xE4 Write Protect Mode Register (CAP0) */
56 	u32	wpsr;		/* 0xE8 Write Protect Status Register (CAP0) */
57 	u32	reserved6[5];
58 	u32	pcer1;		/* 0x100 Periperial Clock Enable Register 1 */
59 	u32	pcdr1;		/* 0x104 Periperial Clock Disable Register 1 */
60 	u32	pcsr1;		/* 0x108 Periperial Clock Status Register 1 */
61 	u32	pcr;		/* 0x10c Periperial Control Register */
62 	u32	ocr;		/* 0x110 Oscillator Calibration Register */
63 } at91_pmc_t;
64 
65 #endif	/* end not assembly */
66 
67 #define AT91_PMC_MOR_MOSCEN		0x01
68 #define AT91_PMC_MOR_OSCBYPASS		0x02
69 #define AT91_PMC_MOR_MOSCRCEN		0x08
70 #define AT91_PMC_MOR_OSCOUNT(x)		(((x) & 0xff) << 8)
71 #define AT91_PMC_MOR_KEY(x)		(((x) & 0xff) << 16)
72 #define AT91_PMC_MOR_MOSCSEL		(1 << 24)
73 
74 #define AT91_PMC_PLLXR_DIV(x)		((x) & 0xFF)
75 #define AT91_PMC_PLLXR_PLLCOUNT(x)	(((x) & 0x3F) << 8)
76 #define AT91_PMC_PLLXR_OUT(x)		(((x) & 0x03) << 14)
77 #if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D3) || \
78 	defined(CONFIG_SAMA5D4)
79 #define AT91_PMC_PLLXR_MUL(x)		(((x) & 0x7F) << 18)
80 #else
81 #define AT91_PMC_PLLXR_MUL(x)		(((x) & 0x7FF) << 16)
82 #endif
83 #define AT91_PMC_PLLAR_29		0x20000000
84 #define AT91_PMC_PLLBR_USBDIV_1		0x00000000
85 #define AT91_PMC_PLLBR_USBDIV_2		0x10000000
86 #define AT91_PMC_PLLBR_USBDIV_4		0x20000000
87 
88 #define AT91_PMC_MCFR_MAINRDY		0x00010000
89 #define AT91_PMC_MCFR_MAINF_MASK	0x0000FFFF
90 #define AT91_PMC_MCFR_RCMEAS		0x00100000
91 #define AT91_PMC_MCFR_CCSS_XTAL_OSC	0x01000000
92 
93 #define AT91_PMC_MCKR_CSS_SLOW		0x00000000
94 #define AT91_PMC_MCKR_CSS_MAIN		0x00000001
95 #define AT91_PMC_MCKR_CSS_PLLA		0x00000002
96 #define AT91_PMC_MCKR_CSS_PLLB		0x00000003
97 #define AT91_PMC_MCKR_CSS_MASK		0x00000003
98 
99 #if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D3) || \
100 	defined(CONFIG_SAMA5D4) || \
101 	defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
102 #define AT91_PMC_MCKR_PRES_1		0x00000000
103 #define AT91_PMC_MCKR_PRES_2		0x00000010
104 #define AT91_PMC_MCKR_PRES_4		0x00000020
105 #define AT91_PMC_MCKR_PRES_8		0x00000030
106 #define AT91_PMC_MCKR_PRES_16		0x00000040
107 #define AT91_PMC_MCKR_PRES_32		0x00000050
108 #define AT91_PMC_MCKR_PRES_64		0x00000060
109 #define AT91_PMC_MCKR_PRES_MASK		0x00000070
110 #else
111 #define AT91_PMC_MCKR_PRES_1		0x00000000
112 #define AT91_PMC_MCKR_PRES_2		0x00000004
113 #define AT91_PMC_MCKR_PRES_4		0x00000008
114 #define AT91_PMC_MCKR_PRES_8		0x0000000C
115 #define AT91_PMC_MCKR_PRES_16		0x00000010
116 #define AT91_PMC_MCKR_PRES_32		0x00000014
117 #define AT91_PMC_MCKR_PRES_64		0x00000018
118 #define AT91_PMC_MCKR_PRES_MASK		0x0000001C
119 #endif
120 
121 #ifdef CONFIG_AT91RM9200
122 #define AT91_PMC_MCKR_MDIV_1		0x00000000
123 #define AT91_PMC_MCKR_MDIV_2		0x00000100
124 #define AT91_PMC_MCKR_MDIV_3		0x00000200
125 #define AT91_PMC_MCKR_MDIV_4		0x00000300
126 #define AT91_PMC_MCKR_MDIV_MASK		0x00000300
127 #else
128 #define AT91_PMC_MCKR_MDIV_1		0x00000000
129 #define AT91_PMC_MCKR_MDIV_2		0x00000100
130 #define AT91_PMC_MCKR_MDIV_3		0x00000300
131 #define AT91_PMC_MCKR_MDIV_4		0x00000200
132 #define AT91_PMC_MCKR_MDIV_MASK		0x00000300
133 #endif
134 
135 #define AT91_PMC_MCKR_PLLADIV_MASK	0x00003000
136 #define AT91_PMC_MCKR_PLLADIV_1		0x00000000
137 #define AT91_PMC_MCKR_PLLADIV_2		0x00001000
138 
139 #define AT91_PMC_MCKR_H32MXDIV		0x01000000
140 
141 #define AT91_PMC_IXR_MOSCS		0x00000001
142 #define AT91_PMC_IXR_LOCKA		0x00000002
143 #define AT91_PMC_IXR_LOCKB		0x00000004
144 #define AT91_PMC_IXR_MCKRDY		0x00000008
145 #define AT91_PMC_IXR_LOCKU		0x00000040
146 #define AT91_PMC_IXR_PCKRDY0		0x00000100
147 #define AT91_PMC_IXR_PCKRDY1		0x00000200
148 #define AT91_PMC_IXR_PCKRDY2		0x00000400
149 #define AT91_PMC_IXR_PCKRDY3		0x00000800
150 #define AT91_PMC_IXR_MOSCSELS		0x00010000
151 
152 #define AT91_PMC_PCR_PID_MASK		(0x3f)
153 #define AT91_PMC_PCR_GCKCSS		(0x7 << 8)
154 #define AT91_PMC_PCR_GCKCSS_MASK	0x07
155 #define AT91_PMC_PCR_GCKCSS_OFFSET	8
156 #define AT91_PMC_PCR_GCKCSS_(x)		((x & 0x07) << 8)
157 #define		AT91_PMC_PCR_GCKCSS_SLOW_CLK	(0x0 << 8)
158 #define		AT91_PMC_PCR_GCKCSS_MAIN_CLK	(0x1 << 8)
159 #define		AT91_PMC_PCR_GCKCSS_PLLA_CLK	(0x2 << 8)
160 #define		AT91_PMC_PCR_GCKCSS_UPLL_CLK	(0x3 << 8)
161 #define		AT91_PMC_PCR_GCKCSS_MCK_CLK	(0x4 << 8)
162 #define		AT91_PMC_PCR_GCKCSS_AUDIO_CLK	(0x5 << 8)
163 #define AT91_PMC_PCR_CMD_WRITE		(0x1 << 12)
164 #define AT91_PMC_PCR_DIV		(0x3 << 16)
165 #define AT91_PMC_PCR_GCKDIV		(0xff << 20)
166 #define AT91_PMC_PCR_GCKDIV_MASK	0xff
167 #define AT91_PMC_PCR_GCKDIV_OFFSET	20
168 #define AT91_PMC_PCR_GCKDIV_(x)		((x & 0xff) << 20)
169 #define AT91_PMC_PCR_EN			(0x1 << 28)
170 #define AT91_PMC_PCR_GCKEN		(0x1 << 29)
171 
172 #define		AT91_PMC_PCK		(1 <<  0)		/* Processor Clock */
173 #define		AT91RM9200_PMC_UDP	(1 <<  1)		/* USB Devcice Port Clock [AT91RM9200 only] */
174 #define		AT91_PMC_DDR		(1 <<  2)		/* DDR Clock */
175 #define		AT91RM9200_PMC_MCKUDP	(1 <<  2)		/* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
176 #define		AT91RM9200_PMC_UHP	(1 <<  4)		/* USB Host Port Clock [AT91RM9200 only] */
177 #define		AT91SAM926x_PMC_UHP	(1 <<  6)		/* USB Host Port Clock [AT91SAM926x only] */
178 #define		AT91SAM926x_PMC_UDP	(1 <<  7)		/* USB Devcice Port Clock [AT91SAM926x only] */
179 #define		AT91_PMC_PCK0		(1 <<  8)		/* Programmable Clock 0 */
180 #define		AT91_PMC_PCK1		(1 <<  9)		/* Programmable Clock 1 */
181 #define		AT91_PMC_PCK2		(1 << 10)		/* Programmable Clock 2 */
182 #define		AT91_PMC_PCK3		(1 << 11)		/* Programmable Clock 3 */
183 #define		AT91_PMC_HCK0		(1 << 16)		/* AHB Clock (USB host) [AT91SAM9261 only] */
184 #define		AT91_PMC_HCK1		(1 << 17)		/* AHB Clock (LCD) [AT91SAM9261 only] */
185 
186 #define		AT91_PMC_UPLLEN		(1   << 16)		/* UTMI PLL Enable */
187 #define		AT91_PMC_UPLLCOUNT	(0xf << 20)		/* UTMI PLL Start-up Time */
188 #define		AT91_PMC_BIASEN		(1   << 24)		/* UTMI BIAS Enable */
189 #define		AT91_PMC_BIASCOUNT	(0xf << 28)		/* UTMI PLL Start-up Time */
190 
191 #define		AT91_PMC_MOSCEN		(1    << 0)		/* Main Oscillator Enable */
192 #define		AT91_PMC_OSCBYPASS	(1    << 1)		/* Oscillator Bypass [SAM9x] */
193 #define		AT91_PMC_OSCOUNT	(0xff << 8)		/* Main Oscillator Start-up Time */
194 
195 #define		AT91_PMC_MAINF		(0xffff <<  0)		/* Main Clock Frequency */
196 #define		AT91_PMC_MAINRDY	(1	<< 16)		/* Main Clock Ready */
197 
198 #define		AT91_PMC_DIV		(0xff  <<  0)		/* Divider */
199 #define		AT91_PMC_PLLCOUNT	(0x3f  <<  8)		/* PLL Counter */
200 #define		AT91_PMC_OUT		(3     << 14)		/* PLL Clock Frequency Range */
201 #define		AT91_PMC_MUL		(0x7ff << 16)		/* PLL Multiplier */
202 #define		AT91_PMC_USBDIV		(3     << 28)		/* USB Divisor (PLLB only) */
203 #define			AT91_PMC_USBDIV_1		(0 << 28)
204 #define			AT91_PMC_USBDIV_2		(1 << 28)
205 #define			AT91_PMC_USBDIV_4		(2 << 28)
206 #define		AT91_PMC_USB96M		(1     << 28)		/* Divider by 2 Enable (PLLB only) */
207 #define		AT91_PMC_PLLA_WR_ERRATA	(1     << 29)		/* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */
208 
209 #define		AT91_PMC_CSS		(3 <<  0)		/* Master Clock Selection */
210 #define			AT91_PMC_CSS_SLOW		(0 << 0)
211 #define			AT91_PMC_CSS_MAIN		(1 << 0)
212 #define			AT91_PMC_CSS_PLLA		(2 << 0)
213 #define			AT91_PMC_CSS_PLLB		(3 << 0)
214 #define		AT91_PMC_PRES		(7 <<  2)		/* Master Clock Prescaler */
215 #define			AT91_PMC_PRES_1			(0 << 2)
216 #define			AT91_PMC_PRES_2			(1 << 2)
217 #define			AT91_PMC_PRES_4			(2 << 2)
218 #define			AT91_PMC_PRES_8			(3 << 2)
219 #define			AT91_PMC_PRES_16		(4 << 2)
220 #define			AT91_PMC_PRES_32		(5 << 2)
221 #define			AT91_PMC_PRES_64		(6 << 2)
222 #define		AT91_PMC_MDIV		(3 <<  8)		/* Master Clock Division */
223 #define			AT91RM9200_PMC_MDIV_1		(0 << 8)	/* [AT91RM9200 only] */
224 #define			AT91RM9200_PMC_MDIV_2		(1 << 8)
225 #define			AT91RM9200_PMC_MDIV_3		(2 << 8)
226 #define			AT91RM9200_PMC_MDIV_4		(3 << 8)
227 #define			AT91SAM9_PMC_MDIV_1		(0 << 8)	/* [SAM9 only] */
228 #define			AT91SAM9_PMC_MDIV_2		(1 << 8)
229 #define			AT91SAM9_PMC_MDIV_4		(2 << 8)
230 #define			AT91SAM9_PMC_MDIV_3		(3 << 8)	/* [some SAM9 only] */
231 #define			AT91SAM9_PMC_MDIV_6		(3 << 8)
232 #define		AT91_PMC_PDIV		(1 << 12)		/* Processor Clock Division [some SAM9 only] */
233 #define			AT91_PMC_PDIV_1			(0 << 12)
234 #define			AT91_PMC_PDIV_2			(1 << 12)
235 
236 #define AT91_PMC_USB_USBS_MASK		0x1
237 #define AT91_PMC_USB_USBS_OFFSET		0
238 #define AT91_PMC_USB_USBS_(x)		(x & 0x1)
239 #define		AT91_PMC_USBS_USB_PLLA		(0x0)		/* USB Clock Input is PLLA */
240 #define		AT91_PMC_USBS_USB_UPLL		(0x1)		/* USB Clock Input is UPLL */
241 #define		AT91_PMC_USBS_USB_PLLB		(0x1)		/* USB Clock Input is PLLB, AT91SAM9N12 only */
242 #define AT91_PMC_USB_DIV_MASK		0xf
243 #define AT91_PMC_USB_DIV_OFFSET		8
244 #define AT91_PMC_USB_DIV_(x)		((x & 0xf) << 8)
245 #define		AT91_PMC_USB_DIV_2		(0x1 <<  8)	/* USB Clock divided by 2 */
246 #define		AT91_PMC_USBDIV_8		(0x7 <<  8)	/* USB Clock divided by 8 */
247 #define		AT91_PMC_USBDIV_10		(0x9 <<  8)	/* USB Clock divided by 10 */
248 
249 #define		AT91_PMC_MOSCS		(1 <<  0)		/* MOSCS Flag */
250 #define		AT91_PMC_LOCKA		(1 <<  1)		/* PLLA Lock */
251 #define		AT91_PMC_LOCKB		(1 <<  2)		/* PLLB Lock */
252 #define		AT91_PMC_MCKRDY		(1 <<  3)		/* Master Clock */
253 #define		AT91_PMC_LOCKU		(1 <<  6)		/* UPLL Lock */
254 #define		AT91_PMC_PCK0RDY	(1 <<  8)		/* Programmable Clock 0 */
255 #define		AT91_PMC_PCK1RDY	(1 <<  9)		/* Programmable Clock 1 */
256 #define		AT91_PMC_PCK2RDY	(1 << 10)		/* Programmable Clock 2 */
257 #define		AT91_PMC_PCK3RDY	(1 << 11)		/* Programmable Clock 3 */
258 #define		AT91_PMC_MOSCSELS	BIT(16)			/* Main Oscillator Selection Status */
259 #define		AT91_PMC_MOSCRCS	BIT(17)			/* 12 MHz RC Oscillator Status */
260 #define		AT91_PMC_GCKRDY		(1 << 24)
261 #define		AT91_PMC_PROTKEY	0x504d4301	/* Activation Code */
262 
263 /* PLL Charge Pump Current Register (PMC_PLLICPR) */
264 #define AT91_PMC_ICP_PLLA(x)		(((x) & 0x3) << 0)
265 #define AT91_PMC_IPLL_PLLA(x)		(((x) & 0x7) << 8)
266 #define AT91_PMC_ICP_PLLU(x)		(((x) & 0x3) << 16)
267 #define AT91_PMC_IVCO_PLLU(x)		(((x) & 0x3) << 24)
268 
269 #endif
270