1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2015 Google, Inc
4 * Copyright 2014 Rockchip Inc.
5 */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <display.h>
10 #include <dm.h>
11 #include <dm/device_compat.h>
12 #include <edid.h>
13 #include <log.h>
14 #include <malloc.h>
15 #include <panel.h>
16 #include <regmap.h>
17 #include <reset.h>
18 #include <syscon.h>
19 #include <asm/gpio.h>
20 #include <asm/io.h>
21 #include <asm/arch-rockchip/clock.h>
22 #include <asm/arch-rockchip/hardware.h>
23 #include <asm/arch-rockchip/edp_rk3288.h>
24 #include <asm/arch-rockchip/grf_rk3288.h>
25 #include <asm/arch-rockchip/grf_rk3399.h>
26
27 #define MAX_CR_LOOP 5
28 #define MAX_EQ_LOOP 5
29 #define DP_LINK_STATUS_SIZE 6
30
31 static const char * const voltage_names[] = {
32 "0.4V", "0.6V", "0.8V", "1.2V"
33 };
34 static const char * const pre_emph_names[] = {
35 "0dB", "3.5dB", "6dB", "9.5dB"
36 };
37
38 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
39 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5
40
41 #define RK3288_GRF_SOC_CON6 0x025c
42 #define RK3288_GRF_SOC_CON12 0x0274
43 #define RK3399_GRF_SOC_CON20 0x6250
44 #define RK3399_GRF_SOC_CON25 0x6264
45
46 enum rockchip_dp_types {
47 RK3288_DP = 0,
48 RK3399_EDP
49 };
50
51 struct rockchip_dp_data {
52 unsigned long reg_vop_big_little;
53 unsigned long reg_vop_big_little_sel;
54 unsigned long reg_ref_clk_sel;
55 unsigned long ref_clk_sel_bit;
56 enum rockchip_dp_types chip_type;
57 };
58
59 struct rk_edp_priv {
60 struct rk3288_edp *regs;
61 void *grf;
62 struct udevice *panel;
63 struct link_train link_train;
64 u8 train_set[4];
65 };
66
rk_edp_init_refclk(struct rk3288_edp * regs,enum rockchip_dp_types chip_type)67 static void rk_edp_init_refclk(struct rk3288_edp *regs, enum rockchip_dp_types chip_type)
68 {
69 writel(SEL_24M, ®s->analog_ctl_2);
70 u32 reg;
71
72 reg = REF_CLK_24M;
73 if (chip_type == RK3288_DP)
74 reg ^= REF_CLK_MASK;
75 writel(reg, ®s->pll_reg_1);
76
77
78 writel(LDO_OUTPUT_V_SEL_145 | KVCO_DEFALUT | CHG_PUMP_CUR_SEL_5US |
79 V2L_CUR_SEL_1MA, ®s->pll_reg_2);
80
81 writel(LOCK_DET_CNT_SEL_256 | LOOP_FILTER_RESET | PALL_SSC_RESET |
82 LOCK_DET_BYPASS | PLL_LOCK_DET_MODE | PLL_LOCK_DET_FORCE,
83 ®s->pll_reg_3);
84
85 writel(REGULATOR_V_SEL_950MV | STANDBY_CUR_SEL |
86 CHG_PUMP_INOUT_CTRL_1200MV | CHG_PUMP_INPUT_CTRL_OP,
87 ®s->pll_reg_5);
88
89 writel(SSC_OFFSET | SSC_MODE | SSC_DEPTH, ®s->ssc_reg);
90
91 writel(TX_SWING_PRE_EMP_MODE | PRE_DRIVER_PW_CTRL1 |
92 LP_MODE_CLK_REGULATOR | RESISTOR_MSB_CTRL | RESISTOR_CTRL,
93 ®s->tx_common);
94
95 writel(DP_AUX_COMMON_MODE | DP_AUX_EN | AUX_TERM_50OHM,
96 ®s->dp_aux);
97
98 writel(DP_BG_OUT_SEL | DP_DB_CUR_CTRL | DP_BG_SEL | DP_RESISTOR_TUNE_BG,
99 ®s->dp_bias);
100
101 writel(CH1_CH3_SWING_EMP_CTRL | CH0_CH2_SWING_EMP_CTRL,
102 ®s->dp_reserv2);
103 }
104
rk_edp_init_interrupt(struct rk3288_edp * regs)105 static void rk_edp_init_interrupt(struct rk3288_edp *regs)
106 {
107 /* Set interrupt pin assertion polarity as high */
108 writel(INT_POL, ®s->int_ctl);
109
110 /* Clear pending registers */
111 writel(0xff, ®s->common_int_sta_1);
112 writel(0x4f, ®s->common_int_sta_2);
113 writel(0xff, ®s->common_int_sta_3);
114 writel(0x27, ®s->common_int_sta_4);
115 writel(0x7f, ®s->dp_int_sta);
116
117 /* 0:mask,1: unmask */
118 writel(0x00, ®s->common_int_mask_1);
119 writel(0x00, ®s->common_int_mask_2);
120 writel(0x00, ®s->common_int_mask_3);
121 writel(0x00, ®s->common_int_mask_4);
122 writel(0x00, ®s->int_sta_mask);
123 }
124
rk_edp_enable_sw_function(struct rk3288_edp * regs)125 static void rk_edp_enable_sw_function(struct rk3288_edp *regs)
126 {
127 clrbits_le32(®s->func_en_1, SW_FUNC_EN_N);
128 }
129
rk_edp_get_pll_locked(struct rk3288_edp * regs)130 static bool rk_edp_get_pll_locked(struct rk3288_edp *regs)
131 {
132 u32 val;
133
134 val = readl(®s->dp_debug_ctl);
135
136 return val & PLL_LOCK;
137 }
138
rk_edp_init_analog_func(struct rk3288_edp * regs)139 static int rk_edp_init_analog_func(struct rk3288_edp *regs)
140 {
141 ulong start;
142
143 writel(0x00, ®s->dp_pd);
144 writel(PLL_LOCK_CHG, ®s->common_int_sta_1);
145
146 clrbits_le32(®s->dp_debug_ctl, F_PLL_LOCK | PLL_LOCK_CTRL);
147
148 start = get_timer(0);
149 while (!rk_edp_get_pll_locked(regs)) {
150 if (get_timer(start) > PLL_LOCK_TIMEOUT) {
151 printf("%s: PLL is not locked\n", __func__);
152 return -ETIMEDOUT;
153 }
154 }
155
156 /* Enable Serdes FIFO function and Link symbol clock domain module */
157 clrbits_le32(®s->func_en_2, SERDES_FIFO_FUNC_EN_N |
158 LS_CLK_DOMAIN_FUNC_EN_N | AUX_FUNC_EN_N |
159 SSC_FUNC_EN_N);
160
161 return 0;
162 }
163
rk_edp_init_aux(struct rk3288_edp * regs)164 static void rk_edp_init_aux(struct rk3288_edp *regs)
165 {
166 /* Clear inerrupts related to AUX channel */
167 writel(AUX_FUNC_EN_N, ®s->dp_int_sta);
168
169 /* Disable AUX channel module */
170 setbits_le32(®s->func_en_2, AUX_FUNC_EN_N);
171
172 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
173 writel(DEFER_CTRL_EN | DEFER_COUNT(1), ®s->aux_ch_defer_dtl);
174
175 /* Enable AUX channel module */
176 clrbits_le32(®s->func_en_2, AUX_FUNC_EN_N);
177 }
178
rk_edp_aux_enable(struct rk3288_edp * regs)179 static int rk_edp_aux_enable(struct rk3288_edp *regs)
180 {
181 ulong start;
182
183 setbits_le32(®s->aux_ch_ctl_2, AUX_EN);
184 start = get_timer(0);
185 do {
186 if (!(readl(®s->aux_ch_ctl_2) & AUX_EN))
187 return 0;
188 } while (get_timer(start) < 20);
189
190 return -ETIMEDOUT;
191 }
192
rk_edp_is_aux_reply(struct rk3288_edp * regs)193 static int rk_edp_is_aux_reply(struct rk3288_edp *regs)
194 {
195 ulong start;
196
197 start = get_timer(0);
198 while (!(readl(®s->dp_int_sta) & RPLY_RECEIV)) {
199 if (get_timer(start) > 10)
200 return -ETIMEDOUT;
201 }
202
203 writel(RPLY_RECEIV, ®s->dp_int_sta);
204
205 return 0;
206 }
207
rk_edp_start_aux_transaction(struct rk3288_edp * regs)208 static int rk_edp_start_aux_transaction(struct rk3288_edp *regs)
209 {
210 int val, ret;
211
212 /* Enable AUX CH operation */
213 ret = rk_edp_aux_enable(regs);
214 if (ret) {
215 debug("AUX CH enable timeout!\n");
216 return ret;
217 }
218
219 /* Is AUX CH command reply received? */
220 if (rk_edp_is_aux_reply(regs)) {
221 debug("AUX CH command reply failed!\n");
222 return ret;
223 }
224
225 /* Clear interrupt source for AUX CH access error */
226 val = readl(®s->dp_int_sta);
227 if (val & AUX_ERR) {
228 writel(AUX_ERR, ®s->dp_int_sta);
229 return -EIO;
230 }
231
232 /* Check AUX CH error access status */
233 val = readl(®s->dp_int_sta);
234 if (val & AUX_STATUS_MASK) {
235 debug("AUX CH error happens: %d\n\n", val & AUX_STATUS_MASK);
236 return -EIO;
237 }
238
239 return 0;
240 }
241
rk_edp_dpcd_transfer(struct rk3288_edp * regs,unsigned int val_addr,u8 * in_data,unsigned int length,enum dpcd_request request)242 static int rk_edp_dpcd_transfer(struct rk3288_edp *regs,
243 unsigned int val_addr, u8 *in_data,
244 unsigned int length,
245 enum dpcd_request request)
246 {
247 int val;
248 int i, try_times;
249 u8 *data;
250 int ret = 0;
251 u32 len = 0;
252
253 while (length) {
254 len = min(length, 16U);
255 for (try_times = 0; try_times < 10; try_times++) {
256 data = in_data;
257 /* Clear AUX CH data buffer */
258 writel(BUF_CLR, ®s->buf_data_ctl);
259
260 /* Select DPCD device address */
261 writel(AUX_ADDR_7_0(val_addr), ®s->aux_addr_7_0);
262 writel(AUX_ADDR_15_8(val_addr), ®s->aux_addr_15_8);
263 writel(AUX_ADDR_19_16(val_addr), ®s->aux_addr_19_16);
264
265 /*
266 * Set DisplayPort transaction and read 1 byte
267 * If bit 3 is 1, DisplayPort transaction.
268 * If Bit 3 is 0, I2C transaction.
269 */
270 if (request == DPCD_WRITE) {
271 val = AUX_LENGTH(len) |
272 AUX_TX_COMM_DP_TRANSACTION |
273 AUX_TX_COMM_WRITE;
274 for (i = 0; i < len; i++)
275 writel(*data++, ®s->buf_data[i]);
276 } else
277 val = AUX_LENGTH(len) |
278 AUX_TX_COMM_DP_TRANSACTION |
279 AUX_TX_COMM_READ;
280
281 writel(val, ®s->aux_ch_ctl_1);
282
283 /* Start AUX transaction */
284 ret = rk_edp_start_aux_transaction(regs);
285 if (ret == 0)
286 break;
287 else
288 printf("read dpcd Aux Transaction fail!\n");
289 }
290
291 if (ret)
292 return ret;
293
294 if (request == DPCD_READ) {
295 for (i = 0; i < len; i++)
296 *data++ = (u8)readl(®s->buf_data[i]);
297 }
298
299 length -= len;
300 val_addr += len;
301 in_data += len;
302 }
303
304 return 0;
305 }
306
rk_edp_dpcd_read(struct rk3288_edp * regs,u32 addr,u8 * values,size_t size)307 static int rk_edp_dpcd_read(struct rk3288_edp *regs, u32 addr, u8 *values,
308 size_t size)
309 {
310 return rk_edp_dpcd_transfer(regs, addr, values, size, DPCD_READ);
311 }
312
rk_edp_dpcd_write(struct rk3288_edp * regs,u32 addr,u8 * values,size_t size)313 static int rk_edp_dpcd_write(struct rk3288_edp *regs, u32 addr, u8 *values,
314 size_t size)
315 {
316 return rk_edp_dpcd_transfer(regs, addr, values, size, DPCD_WRITE);
317 }
318
319
rk_edp_link_power_up(struct rk_edp_priv * edp)320 static int rk_edp_link_power_up(struct rk_edp_priv *edp)
321 {
322 u8 value;
323 int ret;
324
325 /* DP_SET_POWER register is only available on DPCD v1.1 and later */
326 if (edp->link_train.revision < 0x11)
327 return 0;
328
329 ret = rk_edp_dpcd_read(edp->regs, DPCD_LINK_POWER_STATE, &value, 1);
330 if (ret)
331 return ret;
332
333 value &= ~DP_SET_POWER_MASK;
334 value |= DP_SET_POWER_D0;
335
336 ret = rk_edp_dpcd_write(edp->regs, DPCD_LINK_POWER_STATE, &value, 1);
337 if (ret)
338 return ret;
339
340 /*
341 * According to the DP 1.1 specification, a "Sink Device must exit the
342 * power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink
343 * Control Field" (register 0x600).
344 */
345 mdelay(1);
346
347 return 0;
348 }
349
rk_edp_link_configure(struct rk_edp_priv * edp)350 static int rk_edp_link_configure(struct rk_edp_priv *edp)
351 {
352 u8 values[2];
353
354 values[0] = edp->link_train.link_rate;
355 values[1] = edp->link_train.lane_count;
356
357 return rk_edp_dpcd_write(edp->regs, DPCD_LINK_BW_SET, values,
358 sizeof(values));
359 }
360
rk_edp_set_link_training(struct rk_edp_priv * edp,const u8 * training_values)361 static void rk_edp_set_link_training(struct rk_edp_priv *edp,
362 const u8 *training_values)
363 {
364 int i;
365
366 for (i = 0; i < edp->link_train.lane_count; i++)
367 writel(training_values[i], &edp->regs->ln_link_trn_ctl[i]);
368 }
369
edp_link_status(const u8 * link_status,int r)370 static u8 edp_link_status(const u8 *link_status, int r)
371 {
372 return link_status[r - DPCD_LANE0_1_STATUS];
373 }
374
rk_edp_dpcd_read_link_status(struct rk_edp_priv * edp,u8 * link_status)375 static int rk_edp_dpcd_read_link_status(struct rk_edp_priv *edp,
376 u8 *link_status)
377 {
378 return rk_edp_dpcd_read(edp->regs, DPCD_LANE0_1_STATUS, link_status,
379 DP_LINK_STATUS_SIZE);
380 }
381
edp_get_lane_status(const u8 * link_status,int lane)382 static u8 edp_get_lane_status(const u8 *link_status, int lane)
383 {
384 int i = DPCD_LANE0_1_STATUS + (lane >> 1);
385 int s = (lane & 1) * 4;
386 u8 l = edp_link_status(link_status, i);
387
388 return (l >> s) & 0xf;
389 }
390
rk_edp_clock_recovery(const u8 * link_status,int lane_count)391 static int rk_edp_clock_recovery(const u8 *link_status, int lane_count)
392 {
393 int lane;
394 u8 lane_status;
395
396 for (lane = 0; lane < lane_count; lane++) {
397 lane_status = edp_get_lane_status(link_status, lane);
398 if ((lane_status & DP_LANE_CR_DONE) == 0)
399 return -EIO;
400 }
401
402 return 0;
403 }
404
rk_edp_channel_eq(const u8 * link_status,int lane_count)405 static int rk_edp_channel_eq(const u8 *link_status, int lane_count)
406 {
407 u8 lane_align;
408 u8 lane_status;
409 int lane;
410
411 lane_align = edp_link_status(link_status,
412 DPCD_LANE_ALIGN_STATUS_UPDATED);
413 if (!(lane_align & DP_INTERLANE_ALIGN_DONE))
414 return -EIO;
415 for (lane = 0; lane < lane_count; lane++) {
416 lane_status = edp_get_lane_status(link_status, lane);
417 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
418 return -EIO;
419 }
420
421 return 0;
422 }
423
rk_edp_get_adjust_request_voltage(const u8 * link_status,int lane)424 static uint rk_edp_get_adjust_request_voltage(const u8 *link_status, int lane)
425 {
426 int i = DPCD_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
427 int s = ((lane & 1) ?
428 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
429 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
430 u8 l = edp_link_status(link_status, i);
431
432 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
433 }
434
rk_edp_get_adjust_request_pre_emphasis(const u8 * link_status,int lane)435 static uint rk_edp_get_adjust_request_pre_emphasis(const u8 *link_status,
436 int lane)
437 {
438 int i = DPCD_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
439 int s = ((lane & 1) ?
440 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
441 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
442 u8 l = edp_link_status(link_status, i);
443
444 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
445 }
446
edp_get_adjust_train(const u8 * link_status,int lane_count,u8 train_set[])447 static void edp_get_adjust_train(const u8 *link_status, int lane_count,
448 u8 train_set[])
449 {
450 uint v = 0;
451 uint p = 0;
452 int lane;
453
454 for (lane = 0; lane < lane_count; lane++) {
455 uint this_v, this_p;
456
457 this_v = rk_edp_get_adjust_request_voltage(link_status, lane);
458 this_p = rk_edp_get_adjust_request_pre_emphasis(link_status,
459 lane);
460
461 debug("requested signal parameters: lane %d voltage %s pre_emph %s\n",
462 lane,
463 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
464 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
465
466 if (this_v > v)
467 v = this_v;
468 if (this_p > p)
469 p = this_p;
470 }
471
472 if (v >= DP_VOLTAGE_MAX)
473 v |= DP_TRAIN_MAX_SWING_REACHED;
474
475 if (p >= DP_PRE_EMPHASIS_MAX)
476 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
477
478 debug("using signal parameters: voltage %s pre_emph %s\n",
479 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK)
480 >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
481 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK)
482 >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
483
484 for (lane = 0; lane < 4; lane++)
485 train_set[lane] = v | p;
486 }
487
rk_edp_link_train_cr(struct rk_edp_priv * edp)488 static int rk_edp_link_train_cr(struct rk_edp_priv *edp)
489 {
490 struct rk3288_edp *regs = edp->regs;
491 int clock_recovery;
492 uint voltage, tries = 0;
493 u8 status[DP_LINK_STATUS_SIZE];
494 int i, ret;
495 u8 value;
496
497 value = DP_TRAINING_PATTERN_1;
498 writel(value, ®s->dp_training_ptn_set);
499 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_PATTERN_SET, &value, 1);
500 if (ret)
501 return ret;
502 memset(edp->train_set, '\0', sizeof(edp->train_set));
503
504 /* clock recovery loop */
505 clock_recovery = 0;
506 tries = 0;
507 voltage = 0xff;
508
509 while (1) {
510 rk_edp_set_link_training(edp, edp->train_set);
511 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_LANE0_SET,
512 edp->train_set,
513 edp->link_train.lane_count);
514 if (ret)
515 return ret;
516
517 mdelay(1);
518
519 ret = rk_edp_dpcd_read_link_status(edp, status);
520 if (ret) {
521 printf("displayport link status failed, ret=%d\n", ret);
522 break;
523 }
524
525 clock_recovery = rk_edp_clock_recovery(status,
526 edp->link_train.lane_count);
527 if (!clock_recovery)
528 break;
529
530 for (i = 0; i < edp->link_train.lane_count; i++) {
531 if ((edp->train_set[i] &
532 DP_TRAIN_MAX_SWING_REACHED) == 0)
533 break;
534 }
535 if (i == edp->link_train.lane_count) {
536 printf("clock recovery reached max voltage\n");
537 break;
538 }
539
540 if ((edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
541 voltage) {
542 if (++tries == MAX_CR_LOOP) {
543 printf("clock recovery tried 5 times\n");
544 break;
545 }
546 } else {
547 tries = 0;
548 }
549
550 voltage = edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
551
552 /* Compute new train_set as requested by sink */
553 edp_get_adjust_train(status, edp->link_train.lane_count,
554 edp->train_set);
555 }
556 if (clock_recovery) {
557 printf("clock recovery failed: %d\n", clock_recovery);
558 return clock_recovery;
559 } else {
560 debug("clock recovery at voltage %d pre-emphasis %d\n",
561 edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
562 (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
563 DP_TRAIN_PRE_EMPHASIS_SHIFT);
564 return 0;
565 }
566 }
567
rk_edp_link_train_ce(struct rk_edp_priv * edp)568 static int rk_edp_link_train_ce(struct rk_edp_priv *edp)
569 {
570 struct rk3288_edp *regs = edp->regs;
571 int channel_eq;
572 u8 value;
573 int tries;
574 u8 status[DP_LINK_STATUS_SIZE];
575 int ret;
576
577 value = DP_TRAINING_PATTERN_2;
578 writel(value, ®s->dp_training_ptn_set);
579 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_PATTERN_SET, &value, 1);
580 if (ret)
581 return ret;
582
583 /* channel equalization loop */
584 channel_eq = 0;
585 for (tries = 0; tries < 5; tries++) {
586 rk_edp_set_link_training(edp, edp->train_set);
587 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_LANE0_SET,
588 edp->train_set,
589 edp->link_train.lane_count);
590 if (ret)
591 return ret;
592
593 udelay(400);
594
595 if (rk_edp_dpcd_read_link_status(edp, status) < 0) {
596 printf("displayport link status failed\n");
597 return -1;
598 }
599
600 channel_eq = rk_edp_channel_eq(status,
601 edp->link_train.lane_count);
602 if (!channel_eq)
603 break;
604 edp_get_adjust_train(status, edp->link_train.lane_count,
605 edp->train_set);
606 }
607
608 if (channel_eq) {
609 printf("channel eq failed, ret=%d\n", channel_eq);
610 return channel_eq;
611 }
612
613 debug("channel eq at voltage %d pre-emphasis %d\n",
614 edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
615 (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
616 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
617
618 return 0;
619 }
620
rk_edp_init_training(struct rk_edp_priv * edp)621 static int rk_edp_init_training(struct rk_edp_priv *edp)
622 {
623 u8 values[3];
624 int ret;
625
626 ret = rk_edp_dpcd_read(edp->regs, DPCD_DPCD_REV, values,
627 sizeof(values));
628 if (ret < 0)
629 return ret;
630
631 edp->link_train.revision = values[0];
632 edp->link_train.link_rate = values[1];
633 edp->link_train.lane_count = values[2] & DP_MAX_LANE_COUNT_MASK;
634
635 debug("max link rate:%d.%dGps max number of lanes:%d\n",
636 edp->link_train.link_rate * 27 / 100,
637 edp->link_train.link_rate * 27 % 100,
638 edp->link_train.lane_count);
639
640 if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
641 (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
642 debug("Rx Max Link Rate is abnormal :%x\n",
643 edp->link_train.link_rate);
644 return -EPERM;
645 }
646
647 if (edp->link_train.lane_count == 0) {
648 debug("Rx Max Lane count is abnormal :%x\n",
649 edp->link_train.lane_count);
650 return -EPERM;
651 }
652
653 ret = rk_edp_link_power_up(edp);
654 if (ret)
655 return ret;
656
657 return rk_edp_link_configure(edp);
658 }
659
rk_edp_hw_link_training(struct rk_edp_priv * edp)660 static int rk_edp_hw_link_training(struct rk_edp_priv *edp)
661 {
662 ulong start;
663 u32 val;
664 int ret;
665
666 /* Set link rate and count as you want to establish */
667 writel(edp->link_train.link_rate, &edp->regs->link_bw_set);
668 writel(edp->link_train.lane_count, &edp->regs->lane_count_set);
669
670 ret = rk_edp_link_train_cr(edp);
671 if (ret)
672 return ret;
673 ret = rk_edp_link_train_ce(edp);
674 if (ret)
675 return ret;
676
677 writel(HW_LT_EN, &edp->regs->dp_hw_link_training);
678 start = get_timer(0);
679 do {
680 val = readl(&edp->regs->dp_hw_link_training);
681 if (!(val & HW_LT_EN))
682 break;
683 } while (get_timer(start) < 10);
684
685 if (val & HW_LT_ERR_CODE_MASK) {
686 printf("edp hw link training error: %d\n",
687 val >> HW_LT_ERR_CODE_SHIFT);
688 return -EIO;
689 }
690
691 return 0;
692 }
693
rk_edp_select_i2c_device(struct rk3288_edp * regs,unsigned int device_addr,unsigned int val_addr)694 static int rk_edp_select_i2c_device(struct rk3288_edp *regs,
695 unsigned int device_addr,
696 unsigned int val_addr)
697 {
698 int ret;
699
700 /* Set EDID device address */
701 writel(device_addr, ®s->aux_addr_7_0);
702 writel(0x0, ®s->aux_addr_15_8);
703 writel(0x0, ®s->aux_addr_19_16);
704
705 /* Set offset from base address of EDID device */
706 writel(val_addr, ®s->buf_data[0]);
707
708 /*
709 * Set I2C transaction and write address
710 * If bit 3 is 1, DisplayPort transaction.
711 * If Bit 3 is 0, I2C transaction.
712 */
713 writel(AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
714 AUX_TX_COMM_WRITE, ®s->aux_ch_ctl_1);
715
716 /* Start AUX transaction */
717 ret = rk_edp_start_aux_transaction(regs);
718 if (ret != 0) {
719 debug("select_i2c_device Aux Transaction fail!\n");
720 return ret;
721 }
722
723 return 0;
724 }
725
rk_edp_i2c_read(struct rk3288_edp * regs,unsigned int device_addr,unsigned int val_addr,unsigned int count,u8 edid[])726 static int rk_edp_i2c_read(struct rk3288_edp *regs, unsigned int device_addr,
727 unsigned int val_addr, unsigned int count, u8 edid[])
728 {
729 u32 val;
730 unsigned int i, j;
731 unsigned int cur_data_idx;
732 unsigned int defer = 0;
733 int ret = 0;
734
735 for (i = 0; i < count; i += 16) {
736 for (j = 0; j < 10; j++) { /* try 10 times */
737 /* Clear AUX CH data buffer */
738 writel(BUF_CLR, ®s->buf_data_ctl);
739
740 /* Set normal AUX CH command */
741 clrbits_le32(®s->aux_ch_ctl_2, ADDR_ONLY);
742
743 /*
744 * If Rx sends defer, Tx sends only reads
745 * request without sending addres
746 */
747 if (!defer) {
748 ret = rk_edp_select_i2c_device(regs,
749 device_addr,
750 val_addr + i);
751 } else {
752 defer = 0;
753 }
754
755 /*
756 * Set I2C transaction and write data
757 * If bit 3 is 1, DisplayPort transaction.
758 * If Bit 3 is 0, I2C transaction.
759 */
760 writel(AUX_LENGTH(16) | AUX_TX_COMM_I2C_TRANSACTION |
761 AUX_TX_COMM_READ, ®s->aux_ch_ctl_1);
762
763 /* Start AUX transaction */
764 ret = rk_edp_start_aux_transaction(regs);
765 if (ret == 0) {
766 break;
767 } else {
768 debug("Aux Transaction fail!\n");
769 continue;
770 }
771
772 /* Check if Rx sends defer */
773 val = readl(®s->aux_rx_comm);
774 if (val == AUX_RX_COMM_AUX_DEFER ||
775 val == AUX_RX_COMM_I2C_DEFER) {
776 debug("Defer: %d\n\n", val);
777 defer = 1;
778 }
779 }
780
781 if (ret)
782 return ret;
783
784 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
785 val = readl(®s->buf_data[cur_data_idx]);
786 edid[i + cur_data_idx] = (u8)val;
787 }
788 }
789
790 return 0;
791 }
792
rk_edp_set_link_train(struct rk_edp_priv * edp)793 static int rk_edp_set_link_train(struct rk_edp_priv *edp)
794 {
795 int ret;
796
797 ret = rk_edp_init_training(edp);
798 if (ret) {
799 printf("DP LT init failed!\n");
800 return ret;
801 }
802
803 ret = rk_edp_hw_link_training(edp);
804 if (ret)
805 return ret;
806
807 return 0;
808 }
809
rk_edp_init_video(struct rk3288_edp * regs)810 static void rk_edp_init_video(struct rk3288_edp *regs)
811 {
812 writel(VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG,
813 ®s->common_int_sta_1);
814 writel(CHA_CRI(4) | CHA_CTRL, ®s->sys_ctl_2);
815 writel(VID_HRES_TH(2) | VID_VRES_TH(0), ®s->video_ctl_8);
816 }
817
rk_edp_config_video_slave_mode(struct rk3288_edp * regs)818 static void rk_edp_config_video_slave_mode(struct rk3288_edp *regs)
819 {
820 clrbits_le32(®s->func_en_1, VID_FIFO_FUNC_EN_N | VID_CAP_FUNC_EN_N);
821 }
822
rk_edp_set_video_cr_mn(struct rk3288_edp * regs,enum clock_recovery_m_value_type type,u32 m_value,u32 n_value)823 static void rk_edp_set_video_cr_mn(struct rk3288_edp *regs,
824 enum clock_recovery_m_value_type type,
825 u32 m_value,
826 u32 n_value)
827 {
828 if (type == REGISTER_M) {
829 setbits_le32(®s->sys_ctl_4, FIX_M_VID);
830 writel(m_value & 0xff, ®s->m_vid_0);
831 writel((m_value >> 8) & 0xff, ®s->m_vid_1);
832 writel((m_value >> 16) & 0xff, ®s->m_vid_2);
833
834 writel(n_value & 0xf, ®s->n_vid_0);
835 writel((n_value >> 8) & 0xff, ®s->n_vid_1);
836 writel((n_value >> 16) & 0xff, ®s->n_vid_2);
837 } else {
838 clrbits_le32(®s->sys_ctl_4, FIX_M_VID);
839
840 writel(0x00, ®s->n_vid_0);
841 writel(0x80, ®s->n_vid_1);
842 writel(0x00, ®s->n_vid_2);
843 }
844 }
845
rk_edp_is_video_stream_clock_on(struct rk3288_edp * regs)846 static int rk_edp_is_video_stream_clock_on(struct rk3288_edp *regs)
847 {
848 ulong start;
849 u32 val;
850
851 start = get_timer(0);
852 do {
853 val = readl(®s->sys_ctl_1);
854
855 /* must write value to update DET_STA bit status */
856 writel(val, ®s->sys_ctl_1);
857 val = readl(®s->sys_ctl_1);
858 if (!(val & DET_STA))
859 continue;
860
861 val = readl(®s->sys_ctl_2);
862
863 /* must write value to update CHA_STA bit status */
864 writel(val, ®s->sys_ctl_2);
865 val = readl(®s->sys_ctl_2);
866 if (!(val & CHA_STA))
867 return 0;
868
869 } while (get_timer(start) < 100);
870
871 return -ETIMEDOUT;
872 }
873
rk_edp_is_video_stream_on(struct rk_edp_priv * edp)874 static int rk_edp_is_video_stream_on(struct rk_edp_priv *edp)
875 {
876 ulong start;
877 u32 val;
878
879 start = get_timer(0);
880 do {
881 val = readl(&edp->regs->sys_ctl_3);
882
883 /* must write value to update STRM_VALID bit status */
884 writel(val, &edp->regs->sys_ctl_3);
885
886 val = readl(&edp->regs->sys_ctl_3);
887 if (!(val & STRM_VALID))
888 return 0;
889 } while (get_timer(start) < 100);
890
891 return -ETIMEDOUT;
892 }
893
rk_edp_config_video(struct rk_edp_priv * edp)894 static int rk_edp_config_video(struct rk_edp_priv *edp)
895 {
896 int ret;
897
898 rk_edp_config_video_slave_mode(edp->regs);
899
900 if (!rk_edp_get_pll_locked(edp->regs)) {
901 debug("PLL is not locked yet.\n");
902 return -ETIMEDOUT;
903 }
904
905 ret = rk_edp_is_video_stream_clock_on(edp->regs);
906 if (ret)
907 return ret;
908
909 /* Set to use the register calculated M/N video */
910 rk_edp_set_video_cr_mn(edp->regs, CALCULATED_M, 0, 0);
911
912 /* For video bist, Video timing must be generated by register */
913 clrbits_le32(&edp->regs->video_ctl_10, F_SEL);
914
915 /* Disable video mute */
916 clrbits_le32(&edp->regs->video_ctl_1, VIDEO_MUTE);
917
918 /* Enable video at next frame */
919 setbits_le32(&edp->regs->video_ctl_1, VIDEO_EN);
920
921 return rk_edp_is_video_stream_on(edp);
922 }
923
rockchip_edp_force_hpd(struct rk_edp_priv * edp)924 static void rockchip_edp_force_hpd(struct rk_edp_priv *edp)
925 {
926 setbits_le32(&edp->regs->sys_ctl_3, F_HPD | HPD_CTRL);
927 }
928
rockchip_edp_get_plug_in_status(struct rk_edp_priv * edp)929 static int rockchip_edp_get_plug_in_status(struct rk_edp_priv *edp)
930 {
931 u32 val;
932
933 val = readl(&edp->regs->sys_ctl_3);
934 if (val & HPD_STATUS)
935 return 1;
936
937 return 0;
938 }
939
940 /*
941 * support edp HPD function
942 * some hardware version do not support edp hdp,
943 * we use 200ms to try to get the hpd single now,
944 * if we can not get edp hpd single, it will delay 200ms,
945 * also meet the edp power timing request, to compatible
946 * all of the hardware version
947 */
rockchip_edp_wait_hpd(struct rk_edp_priv * edp)948 static void rockchip_edp_wait_hpd(struct rk_edp_priv *edp)
949 {
950 ulong start;
951
952 start = get_timer(0);
953 do {
954 if (rockchip_edp_get_plug_in_status(edp))
955 return;
956 udelay(100);
957 } while (get_timer(start) < 200);
958
959 debug("do not get hpd single, force hpd\n");
960 rockchip_edp_force_hpd(edp);
961 }
962
rk_edp_enable(struct udevice * dev,int panel_bpp,const struct display_timing * edid)963 static int rk_edp_enable(struct udevice *dev, int panel_bpp,
964 const struct display_timing *edid)
965 {
966 struct rk_edp_priv *priv = dev_get_priv(dev);
967 int ret = 0;
968
969 ret = rk_edp_set_link_train(priv);
970 if (ret) {
971 printf("link train failed!\n");
972 return ret;
973 }
974
975 rk_edp_init_video(priv->regs);
976 ret = rk_edp_config_video(priv);
977 if (ret) {
978 printf("config video failed\n");
979 return ret;
980 }
981 ret = panel_enable_backlight(priv->panel);
982 if (ret) {
983 debug("%s: backlight error: %d\n", __func__, ret);
984 return ret;
985 }
986
987 return 0;
988 }
989
rk_edp_read_edid(struct udevice * dev,u8 * buf,int buf_size)990 static int rk_edp_read_edid(struct udevice *dev, u8 *buf, int buf_size)
991 {
992 struct rk_edp_priv *priv = dev_get_priv(dev);
993 u32 edid_size = EDID_LENGTH;
994 int ret;
995 int i;
996
997 for (i = 0; i < 3; i++) {
998 ret = rk_edp_i2c_read(priv->regs, EDID_ADDR, EDID_HEADER,
999 EDID_LENGTH, &buf[EDID_HEADER]);
1000 if (ret) {
1001 debug("EDID read failed\n");
1002 continue;
1003 }
1004
1005 /*
1006 * check if the EDID has an extension flag, and read additional
1007 * EDID data if needed
1008 */
1009 if (buf[EDID_EXTENSION_FLAG]) {
1010 edid_size += EDID_LENGTH;
1011 ret = rk_edp_i2c_read(priv->regs, EDID_ADDR,
1012 EDID_LENGTH, EDID_LENGTH,
1013 &buf[EDID_LENGTH]);
1014 if (ret) {
1015 debug("EDID Read failed!\n");
1016 continue;
1017 }
1018 }
1019 goto done;
1020 }
1021
1022 /* After 3 attempts, give up */
1023 return ret;
1024
1025 done:
1026 return edid_size;
1027 }
1028
rk_edp_of_to_plat(struct udevice * dev)1029 static int rk_edp_of_to_plat(struct udevice *dev)
1030 {
1031 struct rk_edp_priv *priv = dev_get_priv(dev);
1032
1033 priv->regs = dev_read_addr_ptr(dev);
1034 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1035
1036 return 0;
1037 }
1038
rk_edp_remove(struct udevice * dev)1039 static int rk_edp_remove(struct udevice *dev)
1040 {
1041 struct rk_edp_priv *priv = dev_get_priv(dev);
1042 struct rk3288_edp *regs = priv->regs;
1043
1044 setbits_le32(®s->video_ctl_1, VIDEO_MUTE);
1045 clrbits_le32(®s->video_ctl_1, VIDEO_EN);
1046 clrbits_le32(®s->sys_ctl_3, F_HPD | HPD_CTRL);
1047 setbits_le32(®s->func_en_1, SW_FUNC_EN_N);
1048
1049 return 0;
1050 }
1051
rk_edp_probe(struct udevice * dev)1052 static int rk_edp_probe(struct udevice *dev)
1053 {
1054 struct display_plat *uc_plat = dev_get_uclass_plat(dev);
1055 struct rk_edp_priv *priv = dev_get_priv(dev);
1056 struct rk3288_edp *regs = priv->regs;
1057 struct rockchip_dp_data *edp_data = (struct rockchip_dp_data *)dev_get_driver_data(dev);
1058 struct reset_ctl dp_rst;
1059
1060 struct clk clk;
1061 int ret;
1062
1063 ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
1064 &priv->panel);
1065 if (ret) {
1066 debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
1067 dev->name, ret);
1068 return ret;
1069 }
1070
1071 ret = reset_get_by_name(dev, "dp", &dp_rst);
1072 if (ret) {
1073 dev_err(dev, "failed to get dp reset (ret=%d)\n", ret);
1074 return ret;
1075 }
1076
1077 ret = reset_assert(&dp_rst);
1078 if (ret) {
1079 dev_err(dev, "failed to assert dp reset (ret=%d)\n", ret);
1080 return ret;
1081 }
1082 udelay(20);
1083
1084 ret = reset_deassert(&dp_rst);
1085 if (ret) {
1086 dev_err(dev, "failed to deassert dp reset (ret=%d)\n", ret);
1087 return ret;
1088 }
1089
1090 int vop_id = uc_plat->source_id;
1091 debug("%s, uc_plat=%p, vop_id=%u\n", __func__, uc_plat, vop_id);
1092
1093 if (edp_data->chip_type == RK3288_DP) {
1094 ret = clk_get_by_index(dev, 1, &clk);
1095 if (ret >= 0) {
1096 ret = clk_set_rate(&clk, 0);
1097 clk_free(&clk);
1098 }
1099 if (ret) {
1100 debug("%s: Failed to set EDP clock: ret=%d\n", __func__, ret);
1101 return ret;
1102 }
1103 }
1104 ret = clk_get_by_index(uc_plat->src_dev, 0, &clk);
1105 if (ret >= 0) {
1106 ret = clk_set_rate(&clk, 192000000);
1107 clk_free(&clk);
1108 }
1109 if (ret < 0) {
1110 debug("%s: Failed to set clock in source device '%s': ret=%d\n",
1111 __func__, uc_plat->src_dev->name, ret);
1112 return ret;
1113 }
1114
1115 /* grf_edp_ref_clk_sel: from internal 24MHz or 27MHz clock */
1116 rk_setreg(priv->grf + edp_data->reg_ref_clk_sel,
1117 edp_data->ref_clk_sel_bit);
1118
1119 /* select epd signal from vop0 or vop1 */
1120 rk_clrsetreg(priv->grf + edp_data->reg_vop_big_little,
1121 edp_data->reg_vop_big_little_sel,
1122 (vop_id == 1) ? edp_data->reg_vop_big_little_sel : 0);
1123
1124 rockchip_edp_wait_hpd(priv);
1125
1126 rk_edp_init_refclk(regs, edp_data->chip_type);
1127 rk_edp_init_interrupt(regs);
1128 rk_edp_enable_sw_function(regs);
1129 ret = rk_edp_init_analog_func(regs);
1130 if (ret)
1131 return ret;
1132 rk_edp_init_aux(regs);
1133
1134 return 0;
1135 }
1136
1137 static const struct dm_display_ops dp_rockchip_ops = {
1138 .read_edid = rk_edp_read_edid,
1139 .enable = rk_edp_enable,
1140 };
1141
1142 static const struct rockchip_dp_data rk3399_edp = {
1143 .reg_vop_big_little = RK3399_GRF_SOC_CON20,
1144 .reg_vop_big_little_sel = BIT(5),
1145 .reg_ref_clk_sel = RK3399_GRF_SOC_CON25,
1146 .ref_clk_sel_bit = BIT(11),
1147 .chip_type = RK3399_EDP,
1148 };
1149
1150 static const struct rockchip_dp_data rk3288_dp = {
1151 .reg_vop_big_little = RK3288_GRF_SOC_CON6,
1152 .reg_vop_big_little_sel = BIT(5),
1153 .reg_ref_clk_sel = RK3288_GRF_SOC_CON12,
1154 .ref_clk_sel_bit = BIT(4),
1155 .chip_type = RK3288_DP,
1156 };
1157
1158 static const struct udevice_id rockchip_dp_ids[] = {
1159 { .compatible = "rockchip,rk3288-edp", .data = (ulong)&rk3288_dp },
1160 { .compatible = "rockchip,rk3399-edp", .data = (ulong)&rk3399_edp },
1161 { }
1162 };
1163
1164 U_BOOT_DRIVER(dp_rockchip) = {
1165 .name = "edp_rockchip",
1166 .id = UCLASS_DISPLAY,
1167 .of_match = rockchip_dp_ids,
1168 .ops = &dp_rockchip_ops,
1169 .of_to_plat = rk_edp_of_to_plat,
1170 .probe = rk_edp_probe,
1171 .remove = rk_edp_remove,
1172 .priv_auto = sizeof(struct rk_edp_priv),
1173 };
1174