1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * JZ4780 PLL setup
4 *
5 * Copyright (c) 2013 Imagination Technologies
6 * Author: Paul Burton <paul.burton@imgtec.com>
7 */
8
9 #include <config.h>
10 #include <common.h>
11 #include <asm/io.h>
12 #include <linux/bitops.h>
13 #include <linux/delay.h>
14 #include <mach/jz4780.h>
15
16 #define CPM_CPCCR 0x00
17 #define CPM_LCR 0x04
18 #define CPM_RSR 0x08
19 #define CPM_CPPCR 0x0c
20 #define CPM_CPAPCR 0x10
21 #define CPM_CPMPCR 0x14
22 #define CPM_CPEPCR 0x18
23 #define CPM_CPVPCR 0x1c
24 #define CPM_CLKGR0 0x20
25 #define CPM_OPCR 0x24
26 #define CPM_CLKGR1 0x28
27 #define CPM_DDCDR 0x2c
28 #define CPM_VPUCDR 0x30
29 #define CPM_CPSPR 0x34
30 #define CPM_CPSPPR 0x38
31 #define CPM_USBPCR 0x3c
32 #define CPM_USBRDT 0x40
33 #define CPM_USBVBFIL 0x44
34 #define CPM_USBPCR1 0x48
35 #define CPM_USBCDR 0x50
36 #define CPM_LPCDR 0x54
37 #define CPM_I2SCDR 0x60
38 #define CPM_LPCDR1 0x64
39 #define CPM_MSCCDR 0x68
40 #define CPM_UHCCDR 0x6c
41 #define CPM_SSICDR 0x74
42 #define CPM_CIMCDR 0x7c
43 #define CPM_PCMCDR 0x84
44 #define CPM_GPUCDR 0x88
45 #define CPM_HDMICDR 0x8c
46 #define CPM_I2S1CDR 0xa0
47 #define CPM_MSCCDR1 0xa4
48 #define CPM_MSCCDR2 0xa8
49 #define CPM_BCHCDR 0xac
50 #define CPM_SPCR0 0xb8
51 #define CPM_SPCR1 0xbc
52 #define CPM_CPCSR 0xd4
53 #define CPM_PSWCST(n) ((0x4 * (n)) + 0x90)
54
55 /* Clock control register */
56 #define CPM_CPCCR_SEL_SRC_BIT 30
57 #define CPM_CPCCR_SEL_SRC_MASK (0x3 << CPM_CPCCR_SEL_SRC_BIT)
58 #define CPM_SRC_SEL_STOP 0
59 #define CPM_SRC_SEL_APLL 1
60 #define CPM_SRC_SEL_EXCLK 2
61 #define CPM_SRC_SEL_RTCLK 3
62 #define CPM_CPCCR_SEL_CPLL_BIT 28
63 #define CPM_CPCCR_SEL_CPLL_MASK (0x3 << CPM_CPCCR_SEL_CPLL_BIT)
64 #define CPM_CPCCR_SEL_H0PLL_BIT 26
65 #define CPM_CPCCR_SEL_H0PLL_MASK (0x3 << CPM_CPCCR_SEL_H0PLL_BIT)
66 #define CPM_CPCCR_SEL_H2PLL_BIT 24
67 #define CPM_CPCCR_SEL_H2PLL_MASK (0x3 << CPM_CPCCR_SEL_H2PLL_BIT)
68 #define CPM_PLL_SEL_STOP 0
69 #define CPM_PLL_SEL_SRC 1
70 #define CPM_PLL_SEL_MPLL 2
71 #define CPM_PLL_SEL_EPLL 3
72 #define CPM_CPCCR_CE_CPU (0x1 << 22)
73 #define CPM_CPCCR_CE_AHB0 (0x1 << 21)
74 #define CPM_CPCCR_CE_AHB2 (0x1 << 20)
75 #define CPM_CPCCR_PDIV_BIT 16
76 #define CPM_CPCCR_PDIV_MASK (0xf << CPM_CPCCR_PDIV_BIT)
77 #define CPM_CPCCR_H2DIV_BIT 12
78 #define CPM_CPCCR_H2DIV_MASK (0xf << CPM_CPCCR_H2DIV_BIT)
79 #define CPM_CPCCR_H0DIV_BIT 8
80 #define CPM_CPCCR_H0DIV_MASK (0x0f << CPM_CPCCR_H0DIV_BIT)
81 #define CPM_CPCCR_L2DIV_BIT 4
82 #define CPM_CPCCR_L2DIV_MASK (0x0f << CPM_CPCCR_L2DIV_BIT)
83 #define CPM_CPCCR_CDIV_BIT 0
84 #define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT)
85
86 /* Clock Status register */
87 #define CPM_CPCSR_H2DIV_BUSY BIT(2)
88 #define CPM_CPCSR_H0DIV_BUSY BIT(1)
89 #define CPM_CPCSR_CDIV_BUSY BIT(0)
90
91 /* PLL control register */
92 #define CPM_CPPCR_PLLST_BIT 0
93 #define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT)
94
95 /* XPLL control register */
96 #define CPM_CPXPCR_XPLLM_BIT 19
97 #define CPM_CPXPCR_XPLLM_MASK (0x1fff << CPM_CPXPCR_XPLLM_BIT)
98 #define CPM_CPXPCR_XPLLN_BIT 13
99 #define CPM_CPXPCR_XPLLN_MASK (0x3f << CPM_CPXPCR_XPLLN_BIT)
100 #define CPM_CPXPCR_XPLLOD_BIT 9
101 #define CPM_CPXPCR_XPLLOD_MASK (0xf << CPM_CPXPCR_XPLLOD_BIT)
102 #define CPM_CPXPCR_XLOCK BIT(6)
103 #define CPM_CPXPCR_XPLL_ON BIT(4)
104 #define CPM_CPXPCR_XF_MODE BIT(3)
105 #define CPM_CPXPCR_XPLLBP BIT(1)
106 #define CPM_CPXPCR_XPLLEN BIT(0)
107
108 /* CPM scratch protected register */
109 #define CPM_CPSPPR_BIT 0
110 #define CPM_CPSPPR_MASK (0xffff << CPM_CPSPPR_BIT)
111
112 /* USB parameter control register */
113 #define CPM_USBPCR_USB_MODE BIT(31) /* 1: OTG, 0: UDC*/
114 #define CPM_USBPCR_AVLD_REG BIT(30)
115 #define CPM_USBPCR_IDPULLUP_MASK_BIT 28
116 #define CPM_USBPCR_IDPULLUP_MASK_MASK (0x02 << IDPULLUP_MASK_BIT)
117 #define CPM_USBPCR_INCR_MASK BIT(27)
118 #define CPM_USBPCR_CLK12_EN BIT(26)
119 #define CPM_USBPCR_COMMONONN BIT(25)
120 #define CPM_USBPCR_VBUSVLDEXT BIT(24)
121 #define CPM_USBPCR_VBUSVLDEXTSEL BIT(23)
122 #define CPM_USBPCR_POR BIT(22)
123 #define CPM_USBPCR_SIDDQ BIT(21)
124 #define CPM_USBPCR_OTG_DISABLE BIT(20)
125 #define CPM_USBPCR_COMPDISTUNE_BIT 17
126 #define CPM_USBPCR_COMPDISTUNE_MASK (0x07 << COMPDISTUNE_BIT)
127 #define CPM_USBPCR_OTGTUNE_BIT 14
128 #define CPM_USBPCR_OTGTUNE_MASK (0x07 << OTGTUNE_BIT)
129 #define CPM_USBPCR_SQRXTUNE_BIT 11
130 #define CPM_USBPCR_SQRXTUNE_MASK (0x7x << SQRXTUNE_BIT)
131 #define CPM_USBPCR_TXFSLSTUNE_BIT 7
132 #define CPM_USBPCR_TXFSLSTUNE_MASK (0x0f << TXFSLSTUNE_BIT)
133 #define CPM_USBPCR_TXPREEMPHTUNE BIT(6)
134 #define CPM_USBPCR_TXRISETUNE_BIT 4
135 #define CPM_USBPCR_TXRISETUNE_MASK (0x03 << TXRISETUNE_BIT)
136 #define CPM_USBPCR_TXVREFTUNE_BIT 0
137 #define CPM_USBPCR_TXVREFTUNE_MASK (0x0f << TXVREFTUNE_BIT)
138
139 /* DDR memory clock divider register */
140 #define CPM_DDRCDR_DCS_BIT 30
141 #define CPM_DDRCDR_DCS_MASK (0x3 << CPM_DDRCDR_DCS_BIT)
142 #define CPM_DDRCDR_DCS_STOP (0x0 << CPM_DDRCDR_DCS_BIT)
143 #define CPM_DDRCDR_DCS_SRC (0x1 << CPM_DDRCDR_DCS_BIT)
144 #define CPM_DDRCDR_DCS_MPLL (0x2 << CPM_DDRCDR_DCS_BIT)
145 #define CPM_DDRCDR_CE_DDR BIT(29)
146 #define CPM_DDRCDR_DDR_BUSY BIT(28)
147 #define CPM_DDRCDR_DDR_STOP BIT(27)
148 #define CPM_DDRCDR_DDRDIV_BIT 0
149 #define CPM_DDRCDR_DDRDIV_MASK (0xf << CPM_DDRCDR_DDRDIV_BIT)
150
151 /* USB reset detect timer register */
152 #define CPM_USBRDT_VBFIL_LD_EN BIT(25)
153 #define CPM_USBRDT_IDDIG_EN BIT(24)
154 #define CPM_USBRDT_IDDIG_REG BIT(23)
155 #define CPM_USBRDT_USBRDT_BIT 0
156 #define CPM_USBRDT_USBRDT_MASK (0x7fffff << CPM_USBRDT_USBRDT_BIT)
157
158 /* USB OTG PHY clock divider register */
159 #define CPM_USBCDR_UCS BIT(31)
160 #define CPM_USBCDR_UPCS BIT(30)
161 #define CPM_USBCDR_CEUSB BIT(29)
162 #define CPM_USBCDR_USB_BUSY BIT(28)
163 #define CPM_USBCDR_OTGDIV_BIT 0
164 #define CPM_USBCDR_OTGDIV_MASK (0xff << CPM_USBCDR_OTGDIV_BIT)
165
166 /* I2S device clock divider register */
167 #define CPM_I2SCDR_I2CS BIT(31)
168 #define CPM_I2SCDR_I2PCS BIT(30)
169 #define CPM_I2SCDR_I2SDIV_BIT 0
170 #define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT)
171
172 /* LCD0 pix clock divider register */
173 #define CPM_LPCDR_LPCS_BIT 30
174 #define CPM_LPCDR_LPCS_MASK (0x3 << CPM_LPCDR_LPCS_BIT)
175 #define CPM_LPCDR_CELCD BIT(28)
176 #define CPM_LPCDR_LCD_BUSY BIT(27)
177 #define CPM_LPCDR_LCD_STOP BIT(26)
178 #define CPM_LPCDR_PIXDIV_BIT 0
179 #define CPM_LPCDR_PIXDIV_MASK (0xff << CPM_LPCDR_PIXDIV_BIT)
180
181 /* MSC clock divider register */
182 #define CPM_MSCCDR_MPCS_BIT 30
183 #define CPM_MSCCDR_MPCS_MASK (3 << CPM_MSCCDR_MPCS_BIT)
184 #define CPM_MSCCDR_MPCS_STOP (0x0 << CPM_MSCCDR_MPCS_BIT)
185 #define CPM_MSCCDR_MPCS_SRC (0x1 << CPM_MSCCDR_MPCS_BIT)
186 #define CPM_MSCCDR_MPCS_MPLL (0x2 << CPM_MSCCDR_MPCS_BIT)
187 #define CPM_MSCCDR_CE BIT(29)
188 #define CPM_MSCCDR_MSC_BUSY BIT(28)
189 #define CPM_MSCCDR_MSC_STOP BIT(27)
190 #define CPM_MSCCDR_MSC_CLK0_SEL BIT(15)
191 #define CPM_MSCCDR_MSCDIV_BIT 0
192 #define CPM_MSCCDR_MSCDIV_MASK (0xff << CPM_MSCCDR_MSCDIV_BIT)
193
194 /* UHC 48M clock divider register */
195 #define CPM_UHCCDR_UHCS_BIT 30
196 #define CPM_UHCCDR_UHCS_MASK (0x3 << CPM_UHCCDR_UHCS_BIT)
197 #define CPM_UHCCDR_UHCS_SRC (0x0 << CPM_UHCCDR_UHCS_BIT)
198 #define CPM_UHCCDR_UHCS_MPLL (0x1 << CPM_UHCCDR_UHCS_BIT)
199 #define CPM_UHCCDR_UHCS_EPLL (0x2 << CPM_UHCCDR_UHCS_BIT)
200 #define CPM_UHCCDR_UHCS_OTG (0x3 << CPM_UHCCDR_UHCS_BIT)
201 #define CPM_UHCCDR_CE_UHC BIT(29)
202 #define CPM_UHCCDR_UHC_BUSY BIT(28)
203 #define CPM_UHCCDR_UHC_STOP BIT(27)
204 #define CPM_UHCCDR_UHCDIV_BIT 0
205 #define CPM_UHCCDR_UHCDIV_MASK (0xff << CPM_UHCCDR_UHCDIV_BIT)
206
207 /* SSI clock divider register */
208 #define CPM_SSICDR_SCS BIT(31)
209 #define CPM_SSICDR_SSIDIV_BIT 0
210 #define CPM_SSICDR_SSIDIV_MASK (0x3f << CPM_SSICDR_SSIDIV_BIT)
211
212 /* CIM MCLK clock divider register */
213 #define CPM_CIMCDR_CIMDIV_BIT 0
214 #define CPM_CIMCDR_CIMDIV_MASK (0xff << CPM_CIMCDR_CIMDIV_BIT)
215
216 /* GPS clock divider register */
217 #define CPM_GPSCDR_GPCS BIT(31)
218 #define CPM_GPSCDR_GPSDIV_BIT 0
219 #define CPM_GSPCDR_GPSDIV_MASK (0xf << CPM_GPSCDR_GPSDIV_BIT)
220
221 /* PCM device clock divider register */
222 #define CPM_PCMCDR_PCMS BIT(31)
223 #define CPM_PCMCDR_PCMPCS BIT(30)
224 #define CPM_PCMCDR_PCMDIV_BIT 0
225 #define CPM_PCMCDR_PCMDIV_MASK (0x1ff << CPM_PCMCDR_PCMDIV_BIT)
226
227 /* GPU clock divider register */
228 #define CPM_GPUCDR_GPCS BIT(31)
229 #define CPM_GPUCDR_GPUDIV_BIT 0
230 #define CPM_GPUCDR_GPUDIV_MASK (0x7 << CPM_GPUCDR_GPUDIV_BIT)
231
232 /* HDMI clock divider register */
233 #define CPM_HDMICDR_HPCS_BIT 30
234 #define CPM_HDMICDR_HPCS_MASK (0x3 << CPM_HDMICDR_HPCS_BIT)
235 #define CPM_HDMICDR_CEHDMI BIT(29)
236 #define CPM_HDMICDR_HDMI_BUSY BIT(28)
237 #define CPM_HDMICDR_HDMI_STOP BIT(26)
238 #define CPM_HDMICDR_HDMIDIV_BIT 0
239 #define CPM_HDMICDR_HDMIDIV_MASK (0xff << CPM_HDMICDR_HDMIDIV_BIT)
240
241 /* Low Power Control Register */
242 #define CPM_LCR_PD_SCPU BIT(31)
243 #define CPM_LCR_PD_VPU BIT(30)
244 #define CPM_LCR_PD_GPU BIT(29)
245 #define CPM_LCR_PD_GPS BIT(28)
246 #define CPM_LCR_SCPUS BIT(27)
247 #define CPM_LCR_VPUS BIT(26)
248 #define CPM_LCR_GPUS BIT(25)
249 #define CPM_LCR_GPSS BIT(24)
250 #define CPM_LCR_GPU_IDLE BIT(20)
251 #define CPM_LCR_PST_BIT 8
252 #define CPM_LCR_PST_MASK (0xfff << CPM_LCR_PST_BIT)
253 #define CPM_LCR_DOZE_DUTY_BIT 3
254 #define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT)
255 #define CPM_LCR_DOZE_ON BIT(2)
256 #define CPM_LCR_LPM_BIT 0
257 #define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT)
258 #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT)
259 #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT)
260
261 /* Clock Gate Register0 */
262 #define CPM_CLKGR0_DDR1 BIT(31)
263 #define CPM_CLKGR0_DDR0 BIT(30)
264 #define CPM_CLKGR0_IPU BIT(29)
265 #define CPM_CLKGR0_LCD1 BIT(28)
266 #define CPM_CLKGR0_LCD BIT(27)
267 #define CPM_CLKGR0_CIM BIT(26)
268 #define CPM_CLKGR0_I2C2 BIT(25)
269 #define CPM_CLKGR0_UHC BIT(24)
270 #define CPM_CLKGR0_MAC BIT(23)
271 #define CPM_CLKGR0_GPS BIT(22)
272 #define CPM_CLKGR0_PDMAC BIT(21)
273 #define CPM_CLKGR0_SSI2 BIT(20)
274 #define CPM_CLKGR0_SSI1 BIT(19)
275 #define CPM_CLKGR0_UART3 BIT(18)
276 #define CPM_CLKGR0_UART2 BIT(17)
277 #define CPM_CLKGR0_UART1 BIT(16)
278 #define CPM_CLKGR0_UART0 BIT(15)
279 #define CPM_CLKGR0_SADC BIT(14)
280 #define CPM_CLKGR0_KBC BIT(13)
281 #define CPM_CLKGR0_MSC2 BIT(12)
282 #define CPM_CLKGR0_MSC1 BIT(11)
283 #define CPM_CLKGR0_OWI BIT(10)
284 #define CPM_CLKGR0_TSSI BIT(9)
285 #define CPM_CLKGR0_AIC BIT(8)
286 #define CPM_CLKGR0_SCC BIT(7)
287 #define CPM_CLKGR0_I2C1 BIT(6)
288 #define CPM_CLKGR0_I2C0 BIT(5)
289 #define CPM_CLKGR0_SSI0 BIT(4)
290 #define CPM_CLKGR0_MSC0 BIT(3)
291 #define CPM_CLKGR0_OTG BIT(2)
292 #define CPM_CLKGR0_BCH BIT(1)
293 #define CPM_CLKGR0_NEMC BIT(0)
294
295 /* Clock Gate Register1 */
296 #define CPM_CLKGR1_P1 BIT(15)
297 #define CPM_CLKGR1_X2D BIT(14)
298 #define CPM_CLKGR1_DES BIT(13)
299 #define CPM_CLKGR1_I2C4 BIT(12)
300 #define CPM_CLKGR1_AHB BIT(11)
301 #define CPM_CLKGR1_UART4 BIT(10)
302 #define CPM_CLKGR1_HDMI BIT(9)
303 #define CPM_CLKGR1_OTG1 BIT(8)
304 #define CPM_CLKGR1_GPVLC BIT(7)
305 #define CPM_CLKGR1_AIC1 BIT(6)
306 #define CPM_CLKGR1_COMPRES BIT(5)
307 #define CPM_CLKGR1_GPU BIT(4)
308 #define CPM_CLKGR1_PCM BIT(3)
309 #define CPM_CLKGR1_VPU BIT(2)
310 #define CPM_CLKGR1_TSSI1 BIT(1)
311 #define CPM_CLKGR1_I2C3 BIT(0)
312
313 /* Oscillator and Power Control Register */
314 #define CPM_OPCR_O1ST_BIT 8
315 #define CPM_OPCR_O1ST_MASK (0xff << CPM_OPCR_O1ST_BIT)
316 #define CPM_OPCR_SPENDN BIT(7)
317 #define CPM_OPCR_GPSEN BIT(6)
318 #define CPM_OPCR_SPENDH BIT(5)
319 #define CPM_OPCR_O1SE BIT(4)
320 #define CPM_OPCR_ERCS BIT(2) /* 0: select EXCLK/512 clock, 1: RTCLK clock */
321 #define CPM_OPCR_USBM BIT(0) /* 0: select EXCLK/512 clock, 1: RTCLK clock */
322
323 /* Reset Status Register */
324 #define CPM_RSR_P0R BIT(2)
325 #define CPM_RSR_WR BIT(1)
326 #define CPM_RSR_PR BIT(0)
327
328 /* BCH clock divider register */
329 #define CPM_BCHCDR_BPCS_BIT 30
330 #define CPM_BCHCDR_BPCS_MASK (0x3 << CPM_BCHCDR_BPCS_BIT)
331 #define CPM_BCHCDR_BPCS_STOP (0X0 << CPM_BCHCDR_BPCS_BIT)
332 #define CPM_BCHCDR_BPCS_SRC_CLK (0x1 << CPM_BCHCDR_BPCS_BIT)
333 #define CPM_BCHCDR_BPCS_MPLL (0x2 << CPM_BCHCDR_BPCS_BIT)
334 #define CPM_BCHCDR_BPCS_EPLL (0x3 << CPM_BCHCDR_BPCS_BIT)
335 #define CPM_BCHCDR_CE_BCH BIT(29)
336 #define CPM_BCHCDR_BCH_BUSY BIT(28)
337 #define CPM_BCHCDR_BCH_STOP BIT(27)
338 #define CPM_BCHCDR_BCHCDR_BIT 0
339 #define CPM_BCHCDR_BCHCDR_MASK (0x7 << CPM_BCHCDR_BCHCDR_BIT)
340
341 /* CPM scratch pad protected register(CPSPPR) */
342 #define CPSPPR_CPSPR_WRITABLE 0x00005a5a
343 #define RECOVERY_SIGNATURE 0x1a1a /* means "RECY" */
344 #define RECOVERY_SIGNATURE_SEC 0x800 /* means "RECY" */
345
346 #define REBOOT_SIGNATURE 0x3535 /* means reboot */
347
348 /* XPLL control register */
349 #define XLOCK (1 << 6)
350 #define XPLL_ON (1 << 4)
351 #define XF_MODE (1 << 3)
352 #define XPLLBP (1 << 1)
353 #define XPLLEN (1 << 0)
354
355 enum PLLS {
356 EXTCLK = 0,
357 APLL,
358 MPLL,
359 EPLL,
360 VPLL,
361 };
362
363 #define M_N_OD(m, n, od) \
364 ((((m) - 1) << 19) | (((n) - 1) << 13) | (((od) - 1) << 9))
365
366 struct cgu_pll_select {
367 u8 reg;
368 u8 pll;
369 u8 pll_shift;
370 };
371
pll_init_one(int pll,int m,int n,int od)372 static void pll_init_one(int pll, int m, int n, int od)
373 {
374 void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
375 void __iomem *pll_reg = cpm_regs + CPM_CPAPCR + ((pll - 1) * 4);
376
377 setbits_le32(pll_reg, M_N_OD(m, n, od) | XPLLEN);
378
379 /* FIXME */
380 while (!(readl(pll_reg) & XPLL_ON))
381 ;
382 }
383
cpu_mux_select(int pll)384 static void cpu_mux_select(int pll)
385 {
386 void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
387 u32 clk_ctrl;
388 unsigned int selectplls[] = {
389 CPM_PLL_SEL_STOP,
390 CPM_PLL_SEL_SRC,
391 CPM_PLL_SEL_MPLL,
392 CPM_PLL_SEL_EPLL
393 };
394
395 /* Init CPU, L2CACHE, AHB0, AHB2, APB clock */
396 clk_ctrl = CPM_CPCCR_CE_CPU | CPM_CPCCR_CE_AHB0 | CPM_CPCCR_CE_AHB2 |
397 ((6 - 1) << CPM_CPCCR_H2DIV_BIT) |
398 ((3 - 1) << CPM_CPCCR_H0DIV_BIT) |
399 ((2 - 1) << CPM_CPCCR_L2DIV_BIT) |
400 ((1 - 1) << CPM_CPCCR_CDIV_BIT);
401
402 if (CONFIG_SYS_MHZ >= 1000)
403 clk_ctrl |= (12 - 1) << CPM_CPCCR_PDIV_BIT;
404 else
405 clk_ctrl |= (6 - 1) << CPM_CPCCR_PDIV_BIT;
406
407 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl);
408
409 while (readl(cpm_regs + CPM_CPCSR) & (CPM_CPCSR_CDIV_BUSY |
410 CPM_CPCSR_H0DIV_BUSY | CPM_CPCSR_H2DIV_BUSY))
411 ;
412
413 clk_ctrl = (selectplls[pll] << CPM_CPCCR_SEL_CPLL_BIT) |
414 (selectplls[MPLL] << CPM_CPCCR_SEL_H0PLL_BIT) |
415 (selectplls[MPLL] << CPM_CPCCR_SEL_H2PLL_BIT);
416 if (pll == APLL)
417 clk_ctrl |= CPM_PLL_SEL_SRC << CPM_CPCCR_SEL_SRC_BIT;
418 else
419 clk_ctrl |= CPM_SRC_SEL_EXCLK << CPM_CPCCR_SEL_SRC_BIT;
420
421 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl);
422 }
423
ddr_mux_select(int pll)424 static void ddr_mux_select(int pll)
425 {
426 void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
427 int selectplls[] = { CPM_DDRCDR_DCS_STOP,
428 CPM_DDRCDR_DCS_SRC,
429 CPM_DDRCDR_DCS_MPLL};
430
431 writel(selectplls[pll] | CPM_DDRCDR_CE_DDR | (JZ4780_SYS_MEM_DIV - 1),
432 cpm_regs + CPM_DDCDR);
433
434 while (readl(cpm_regs + CPM_DDCDR) & CPM_DDRCDR_DDR_BUSY)
435 ;
436
437 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_DDR0);
438
439 mdelay(200);
440 }
441
cgu_mux_init(struct cgu_pll_select * cgu,unsigned int num)442 static void cgu_mux_init(struct cgu_pll_select *cgu, unsigned int num)
443 {
444 void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
445 unsigned int selectplls[] = {0, 1, 2, 3, 2, 6};
446 int i;
447
448 for (i = 0; i < num; i++)
449 writel(selectplls[cgu[i].pll] << cgu[i].pll_shift,
450 cpm_regs + cgu[i].reg);
451 }
452
pll_init(void)453 void pll_init(void)
454 {
455 void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
456 struct cgu_pll_select cgu_mux[] = {
457 { CPM_MSCCDR, MPLL, 30 },
458 { CPM_LPCDR, VPLL, 30 },
459 { CPM_LPCDR1, VPLL, 30 },
460 { CPM_GPUCDR, MPLL, 30 },
461 { CPM_HDMICDR, VPLL, 30 },
462 { CPM_I2SCDR, EPLL, 30 },
463 { CPM_BCHCDR, MPLL, 30 },
464 { CPM_VPUCDR, 0x1, 30 },
465 { CPM_UHCCDR, 0x3, 30 },
466 { CPM_CIMCDR, 0x1, 31 },
467 { CPM_PCMCDR, 0x5, 29 },
468 { CPM_SSICDR, 0x3, 30 },
469 };
470
471 /* PLL stable time set to default -- 1ms */
472 clrsetbits_le32(cpm_regs + CPM_CPPCR, 0xfffff, (16 << 8) | 0x20);
473
474 pll_init_one(APLL, JZ4780_APLL_M, JZ4780_APLL_N, JZ4780_APLL_OD);
475 pll_init_one(MPLL, JZ4780_MPLL_M, JZ4780_MPLL_N, JZ4780_MPLL_OD);
476 pll_init_one(VPLL, JZ4780_VPLL_M, JZ4780_VPLL_N, JZ4780_VPLL_OD);
477 pll_init_one(EPLL, JZ4780_EPLL_M, JZ4780_EPLL_N, JZ4780_EPLL_OD);
478
479 cpu_mux_select(MPLL);
480 ddr_mux_select(MPLL);
481 cgu_mux_init(cgu_mux, ARRAY_SIZE(cgu_mux));
482 }
483
jz4780_clk_get_efuse_clk(void)484 const u32 jz4780_clk_get_efuse_clk(void)
485 {
486 void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
487 u32 cpccr = readl(cpm_regs + CPM_CPCCR);
488 u32 ahb2_div = ((cpccr & CPM_CPCCR_H2DIV_MASK) >>
489 CPM_CPCCR_H2DIV_BIT) + 1;
490 return JZ4780_SYS_MEM_SPEED / ahb2_div;
491 }
492
jz4780_clk_ungate_ethernet(void)493 void jz4780_clk_ungate_ethernet(void)
494 {
495 void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
496
497 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_MAC);
498 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_NEMC);
499 }
500
jz4780_clk_ungate_mmc(void)501 void jz4780_clk_ungate_mmc(void)
502 {
503 void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
504 u32 msc_cdr = JZ4780_SYS_MEM_SPEED / 24000000 / 2 - 1;
505
506 msc_cdr |= CPM_MSCCDR_MPCS_MPLL | CPM_MSCCDR_CE;
507 writel(msc_cdr, cpm_regs + CPM_MSCCDR);
508 writel(msc_cdr, cpm_regs + CPM_MSCCDR1);
509 writel(msc_cdr, cpm_regs + CPM_MSCCDR2);
510
511 /* The wait_for_bit() won't fit, thus unbounded loop here. */
512 while (readl(cpm_regs + CPM_MSCCDR1) & CPM_MSCCDR_MSC_BUSY)
513 ;
514 }
515
jz4780_clk_ungate_uart(const unsigned int uart)516 void jz4780_clk_ungate_uart(const unsigned int uart)
517 {
518 void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
519
520 if (uart == 0)
521 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_UART0);
522 else if (uart == 1)
523 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_UART1);
524 else if (uart == 2)
525 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_UART2);
526 else if (uart == 3)
527 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_UART3);
528 else if (uart == 4)
529 clrbits_le32(cpm_regs + CPM_CLKGR1, CPM_CLKGR1_UART4);
530 else
531 printf("%s[%i]: Invalid UART %d\n", __func__, __LINE__, uart);
532 }
533